Course 1: High-Speed PCB Design(November 5th ,6th and 7th 2012)

The speed of todays logic devices mandates that the interconnect on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that reach 17ps. This results in high-speed design problems such as: A lack of control over impedance and reflections Crosstalk and bypassing failures Time delays, false triggering and reflections Failure to meet EMI and FCC requirements It is the edge rate, more than frequency, which exacerbates high-speed design challenges. Even if your design is of moderate frequency, the edge rates can cause your design to exhibit high-speed effects. You Will Learn: How to cost effectively design and layout a high-speed PCB without sacrificing signal integrity How to comply with Signal Integrity (SI) & EMI standards Cookbook design rules that ensure your PCB will function properly in the prototype stage

Course Length: 3 Days Who Should Attend? Digital logic engineers and system architects EMC specialists Technicians PCB layout professionals IC designers Applications Engineers Engineering and project Managers

Course Contents: Fundamentals o o o o o o o Frequency, Time and Distance Lumped Versus Distributed Systems Four Kinds of Reactance Ordinary and Mutual Capacitance & Inductance EM Fields Geometry, C, L, & Zo, interrelationships C & L Resonance

 High-Speed Properties of Logic Gates o o o o Quiescent vs. Active Dissipation Driving Capacitive Loads Input Power and External Power TTL, CMOS, SiGe, In Pn, ECL, & GaAs; Output Power, Speed and engineering disciplines, Dv, di effects and Voltage Margins o ICs: Cu vs Al, what are the issues? o Low K Di-electrics o Intersymbol Interference (ISI), eye diagrams and jitter o Shoot Through Current (SSO) and how to minimize it o Ground Bounce, Lead Inductance, Simultaneous Switching Noise (SSN) o Electronic Packages: QFPs, PGAs, SOIC, PLCC, BGA, COB, TAB, FC, CSP and their relationship to SI o Lead Capacitance and Thermal Considerations Measurement Techniques o o o o o o o o o o o o Rise Time and Bandwidth of Oscilloscopes and probes Self-inductance and Spurious Signal Pickup of a Probe Ground Loop How Probes Load Down a Circuit Special Probing Fixtures Avoiding Pickup from Probe Shield Currents Viewing a Serial Data Transmission System, the eye pattern closure: ISI, Skin effect and tan loss. PLL and DLLs Communications - SONET, SERDES, OC 192/768, Fiber Slowing Down the System Clock Observing Crosstalk Measuring Operating Margins Observing Metastable States in Flip-Flops

Transmission Lines o o o o o o o o o The quality factor, Q, and why lumped circuits can ring and cause EMI. Infinite Uniform Transmission Line Effects of Source and Load Impedance Special Transmission Line Cases Determining Line Impedance & Propagation Delay using TDR and VNA Skin/proximity effect & Dielectric Loss The Capacitive Load - Zo and propagation delay Matching Z0 with trace alturations (neckdowns) - minimizing the C load 90, 45 bends - are they concerns?

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Characteristics of T. lines: coax, pair, micro strip, buried micro strip, stripline & differential: asymmetric, dual, edge. Even/odd, differential/common modes are their effects on LVDS.

Terminations o o o o o o o Vias o o o o o o Mechanical Properties of Vias Capacitance & Inductance of Vias Return Current and Its Relation to Vias Through Hole, Blind, Buried, Micro Vias Intelligent Vias and autorouters Via discontinuity and via resonance concerns End/Source/Middle Terminators AC Biasing for End Terminators, where should it be used and how to choose the capacitor Hairball networks, bifurcated lines and capactive stubs Terminating differentials - Eliminating common mode and minimizing power What causes differentials unbalance? Diode and active terminators, Resistor Selection and Crosstalk in Terminators

Ground Planes and Layer Stacking o o o o o o o o o o o o o High-Speed Current Follows the Path of Least Inductance Crosstalk in Solid and Slotted Ground Planes Inductive/capacitive ratios for micro strips, striplines, and asymmetric, dual, and edge LVDS Guard Traces - Do they stop crosstalk, can they resonate? Near-End and Far-End Crosstalk Separating analog from ECL/PECL and TTL/CMOS the concept of moats/floats/drawbridge Split planes - CMOS/TTL, PECL and analog using the same bias voltages How to Stack Printed Circuit Board Layers (e.g. 4, 6, and 10 layer) for Zo and crosstalk control, Cu fills on signal layers, minimizing warpage Interplane Capacitance - How thin, what material and stackup placement SIR vs. frequency, software for performing crosstalk and ground bounce tests

Power Systems o o o o Providing a stable Voltage Reference - Cu planes Distributing Uniform Voltage - Sense lines, bulk C and interplane C Choosing a Bypass Capacitor - Electrolytic/tantalum and ceramic Power plane resonance - serial and parallel, how to minimize both

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Designing a .1 ohm bypass system up to Fknee Designing for constant ESR IC die capacitance, discrete C in the IC package Why the 0201 - Both for better bypassing and EMI control Minimizing L-Capacitor layouts for SOICs, PLCCs, and various configurations of BGAs

Connectors & Cables o o o o o o Buses o o o o o Multidrop systems: Drivers, Transceivers, PCI, BTL, GTL & RAMBUS How they function, Clock rates, typical failures ISI - Minimize the effect with Equalization and Preemphasis LVDS: types, unbalance, noise, layout & making them function Methods to speed up busses - Distributive driving and load capacitance matching Mutual and Series Inductance - How Connectors Create Crosstalk and EMI Using Connectors on a Multidrop Bus (Z mismatch reflection) and how to match Zc to Zo Measuring Coupling in a Connector Continuity of Gnd Underneath a Connector Special Connectors for High-Speed requirements - Crosstalk and matching Zo Differential Signaling Through a Connector

Clock Distribution o o o o o o o o Timing Margin and Clock Skew Using Low-Impedance Drivers and Clock Distribution Lines Source Term. of Multiple Clock Lines Controlling Crosstalk on Clock Lines Delay Adjustments - Serpentine traces/DACs and varisters for dynamic delay Differential Distribution Controlling Clock Signal Duty Cycle using the integrator Source synchronous clocking, DDR & RDRAM

Recommended Prerequisites: Basic knowledge of ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course.

Course 2: Advanced High-Speed PCB Design (November 8th and 9th, 2012)
With edge rates ever decreasing and clock rates becoming faster, it is vital that engineers understand the underlying issues of the transmission line to insure signal integrity. Also, bypassing these higher frequency edge rates and the ever-increasing power of todays FPGAs and micros require a better grasp of signal power switching. PCBs are becoming more complex with finer traces and spaces and more layers with more blind and buried vias. This requires more attention to controlling crosstalk, EMI, impedance control. You Will Learn: How to cost effectively design and layout a high-speed PCB without sacrificing signal integrity How to comply with Signal Integrity (SI) & EMI standards Cookbook design rules that ensure your PCB will function properly in the prototype stage Course Length: 2 Days Who Should Attend? Digital logic engineers and system architects EMC specialists Technicians PCB layout professionals IC designers Applications Engineers Course Contents: Advanced High Speed Concepts o o o o Impedance of structures to both clock rate harmonics and edge rate harmonics Resonance on Transmission Lines: Serial and Parallel resonance. Quarter wave length differences of high and low end impedance termination. Near field and far field definitions and their effects on the magnetic and electric field strengths The quality factor for lumped circuitry: Why they can ring, crosstalk and cause EMI radiation.

Transmission Lines (TL) o o o o The TL Cell-Defining, Rdc, Rac, Skin Effect, Proximity, and the Dielectric Loss Current Travel on TLs: Converting the B field to eddy currents and how it creates the skin effect and proximity effect Characteristics of PCB Material: What material is used for high frequency: DF, Cost, DFM, DFA

 Performance Regions o o o o o o o The basic RLGC cell and its effect on rising and falling edges The Lumped Element region-parameters and model Practical applications of the lumped model The RC Region of the lumped model. Input/characteristic/Output impedance. Propagation velocity, Elmore's delay and lumped model algorithm The Constant Loss Region: Boundary Conditions, propagation coefficient, resonance, termination considerations The Skin Effect Region: Boundary Conditions, characteristic impedance, propagation delay parameters, termination options, speed and distance Dielectric Region: Boundary Conditions, characteristic impedance, dielectric loss/tangent loss, propagation delay, resonance, termination

The Printed Circuit Board (PCB) o o o o o o o o o Modeling PCB Traces Skin Effect and Dielectric Loss for PCB Traces: microstrip and stripline Dielectric Properties, relative costs and core/prepreg issues for high speed stackups Effects of temperature, frequency and mfg tolerance on characteristic impedance Solder Mask and Conformal Coating: effects on Z0, propagation delay and impedance equations Matching Capacitive and inductive loads using trace width modification Far end and Near end Crosstalk: Inductive and capacitive for microstrips and striplines Matching traces to connectors: Minimizing reflections, crosstalk and EMI Vias: C and L of vias (through hole, blind, buried), via discontinuities and eliminating reflections of vias

Advanced Topics in Bypassing o o o o o o o o Shoot through current and die capacitance Eliminating mode conversion Why the 0201, the long electrode and the Y cap may be essential to control switching impedance and EMI radiation Breakout and bypassing the 4, 5, 6 perimeter ring and fully populated BGA Do copperfills (pours) really help in bypassing? What is the present status of innerplane C materials (FR4, ceramic filled, and polymide) and how thin can they practically be made? How much C is needed and layout considerations for today's FPGAs and micros? Return current and intelligent via placement

Differential Signaling o o Attributes/drawbacks of loosely/tightly coupled differential pairs Definition and examples of differential and common mode V and I

o o o o o

Differential impedance: Odd and even modes Advantages and disadvantages of Edge (side by side), Broadside (dual), asymmetric, and microstrip differentials Reflections and crosstalk in differentials. Metastability, Clk skew, driver skew, bit pattern Sensitivity, ISI, skin effect and dielectric constant. Jitter, BER, and the eye diagram Matching electrical lengths

High Speed Clocking o o o o o Clock skew and jitter PLLs, DDLs, serpentine traces and programmable delays Source and end termination considerations for star, daisy chain and driving multiple loads Clock driving high speed buses: RAMbus and address drivers, minimizing the C load. Random and deterministic jitter. Power Supply noise and Clk jitter

High Speed Data Transmission o o o o Pre-emphasis and equalization Techniques The effects of ISI, Skin and dielectric losses The effect of various base materials of long haul transmission. The effects of eye closure on BER A real world example of compensation techniques

Recommended Prerequisites: An understanding of the course material contained in the high-speed digital design and PCB layout course. The high-speed digital design and PCB layout course is not a prerequisite but familiarity with the material would be helpful in understanding the advanced concepts in this class.

Both the Courses will be Conducted in Bangalore India.