What Is High Speed PCB Design

RAYMING PCB & ASSEMBLY
What is High Speed PCB Design?

High speed PCB design refers to laying out printed circuit boards with
capabilities to operate signal integrity at high frequencies typically above
100MHz. This requires paying special attention to trace parameters and overall
topology to prevent issues like reflections or EMI at these speeds.
We will explore what classifies as a high speed signal, associated design

challenges, layout techniques to address them, analysis steps for validation,
and evolutionary improvements in materials and fabrication enabling ever
higher frequency PCBs.
What Qualifies as a High Speed Signal?
A simple threshold for classifying a signal line as high speed is if its rise time is
shorter than the propagation time across the PCB trace.
For example, a 1GHz clock with 300ps rise time travelling along a 6 inch
(~150mm) FR-4 trace has a propagation delay of ~133ps.
As rise time < propagation delay, this clock would likely suffer from signal
integrity issues like reflections without high speed design precautions. Faster
rise times and longer trace lengths increase this likelihood.
PCB Manufacturing & Assembly Services https://www.raypcb.com/

More formally, signals above 100–200MHz or with edge rates faster than
1V/ns tend to require high speed treatment. Though with increasing PCB
performance, these thresholds are continually pushed higher.
High Speed Challenges
It helps to understand the root physical effects that make high speed design so
challenging:
1. Reflections
Sudden impedance changes along a trace cause partial signal reflections

accumulating signal distortion. Controlled uniform impedance is key.
2. Losses
Skin effect and dielectric losses become pronounced at higher frequencies. This
attenuates and smooths signals.
3. Cross Talk
Adjacent traces capacitively couple crossing signals between each other. Tight
design rules avoid this.

4. EMI Radiation
Rapidly changing currents radiate energy as electrical noise. It couples into

neighboring traces and air as EMI.
Rules of Thumb
Some general guidelines when laying out high speed signals:
 Keep traces short as possible
 Minimize vias and bends
 Maintain steady uniform impedance
 Provide shielding and distance between signals
 Carefully reference signals to ground planes
Next we see how to apply these in practice.
High Speed Routing Techniques

Specialized routing techniques help counter the various issues noted earlier.
1. Impedance Control
Matching trace impedance to terminals prevents reflections. This is measured

relative to ground so a proximate reference plane is key.
Wider traces have lower impedance — equations give exact width and height
above ground to achieve 50-Ohm or 75-Ohm targeted impedance.
2. Layer Stacking
Choosing the right signal layer helps shield from EMI or cross talk. Critical
high speed traces are routed on inner layers rather than external layers more
vulnerable to noise ingress/egress.
Adjacent layer reference planes also help control impedance.
3. Differential Pairs
Carrying a signal and its inverse on paired traces effectively nullifies external
noise coupling into the wiring. So small disturbances induce equal noise onto
the traces which gets cancelled by the receiver.
This enhances reliability and allows closer routing for density. The tradeoff is
doubling the interconnects.
4. Shielding
Adding coplanar ground floods or ground traces on adjacent layers shields

signals from EMI and cross talk. Electromagnetic fields terminate on the
nearby ground surface rather than affect neighboring traces.

5. Termination
Source and load end terminators match trace impedance avoiding any reflected
signal energy. Series resistors avoid resonances while parallel capacitors aid
DC stability for lightly loaded traces.
Mitigating Via Effects
Vias intrinsically disturb signals passing through the barrel connection:
1. The impedance drop reflects signal edges causing overshoot and ringing.
2. Further reflections occur from stub traces leading to the plated barrels.
3. Ground stitching vias also redirect return current flow.
Some via mitigation and avoidance methods help:

Analyzing High Speed Channel Performance
To validate high speed interface integrity prior to full system integration,

engineers use:
Electromagnetic Simulators
3D field solvers model entire PCB stackups detecting impedance

discontinuities, resonance modes and EMI leakage risks. Useful finding issues
early in design flow.
Lumped Circuit Models
Abstract the network into equivalent lumped transmission line elements. Then
transient SPICE-like circuit simulation predicts frequency response, eye
diagrams and potential failure points.
Vector Network Analyzers
Swept frequency S-parameter testing measures insertion loss and reflection

versus frequency on actual fabricated boards. Verifies impedance control and
resonances prior to system bring-up.

Time Domain Reflectometers
Sharp impulse stimulus with sampling scope plots trace impedance changes
along length by timing reflections. Remote faults detectable.
Eye Diagram Analysis
Overlaying repeated symbol periods on an oscilloscope reveals noise impact on

voltage and timing margins of high speed serial transmission eye.
The Continuing Rise of High Speed Digital
Rapid improvements in integrated circuits, fabrication processes and interface

standards continue boosting speeds:

Bandwidths and edge rates continue doubling each decade with no sign of
stopping. What used to be considered ultra high speed becomes mainstream —
posing fresh challenges to PCB materials, costs and fabrication limits which
race to keep up.
It is an exciting era pushing boundaries of high density integration and

performance with every product generation!
Enabling Technologies Driving Speed Improvements

Advances helping accelerate PCB interconnect capabilities include:
Faster Switching ICs
Silicon process scaling boosts transistor fT offering faster edge rates off-die.
Enabling use of faster substrates and T-lines downstream.
Low Loss Dielectrics
Materials like PTFE, ceramic filled hydrocarbon resins and polysiloxanes have
favorable electrical properties. Replacing traditional FR-4 matches the faster
rise times.
Tighter Design Rules
Stackups with thinner dielectrics between tightly coupled power and signal
planes control ever lower trace impedances.
Fine Line Fab Limit Pushing

Improved registration accuracy supports finer trace and spaces with reliable
yield.
Microvias
Enabling more layer transitions maintains impedance integrity. Stacking and

HDI techniques depend on this.
Embedded Actives
Burying active ICs like buffers inside the PCB layers avoids causing
discontinuities with intermediate connectors while also enabling high density
multi-die integration.
The Future — Will Limitations Emerge?
Can the pace of increased frequencies continue indefinitely? At some point

material properties and fabrication tolerances impose bottlenecks:
 Modern PCB dielectrics attain low loss only with increasingly expensive
ceramic fillers and processing. Driving costs higher.
 Shrinking insulator thicknesses struggle avoiding pinholes and

registration inconsistencies causing faults and yield loss.
 Fabricating smaller microvias and matching pad transitions becomes

statistically more prone to defects as clearances disappear.
 PCB embedded actives introduce thermal and coefficient of expansion

complexities negating performance gains.
While ingenious solutions continue advancing limits, they demand higher

investments with diminishing returns.

Economic factors may eventually dominate sheer technical capability in

determining mainstream high speed adoption. But niche applications will
likely keep pushing boundaries regardless of near term cost!
Conclusion
With serial speeds exceeding 100Gbps, what used to be exotic high speed
design techniques are now routine PCB practice. The barriers continue moving
as better materials and fabrication equipment become widespread allowing
designing for signal integrity up to 40GHz or faster.
What seemed impossible on 1990s era PCBs is now commonplace. No doubt

the definition of high speed design will only accelerate thanks to relentless
technology improvement delivering ever greater capability.
FAQ
What frequency range qualifies as high speed for PCB?

As a rule of thumb, trace-line signals above 100MHz begin entering the high
speed domain, though with increasing PCB performance this threshold
continues rising over time. More precisely signals with sub 1ns rise time or
above 5–10V/ns slew rate require high speed precautions.
Why are rise time and propagation delay important for
classifying speed?
If the signal rise time is shorter than the trace delay, edges smear together
causing reflection issues and distortion. So matching the trace length and
board dielectric to the expected rise time helps determine necessary
precautions.
What is most challenging for PCB designer in high speed
layout?
Maintaining smooth uniform trace impedance matched to source/load circuits

is hardest. Sudden variations anywhere causes reflections impacting signal
integrity. This demands tight dimensional tolerances including stable
dielectrics plus sophisticated verification Steps using accurate electromagnetic
modelling tools.
How is impedance matching achieved in PCB controlled?
Impedance depends on dielectric thickness above the reference ground plane

along with trace dimensions. So thinner dielectrics with properly sized trace
widths and spacing gives target 50 Ohm or 75 Ohm impedance needed.
Smooth transitions between sections avoids reflections.
What test equipment helps validate high speed signal integrity?
Time domain reflectometers inject step stimulus then plot impedance changes
along the line from resulting reflections. Network analyzers measures insertion

loss and return loss versus frequency identifying resonances. Real time
oscilloscopes verify eye-diagrams and jitter on high rate serial links using
customized test fixtures.

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RAYMING PCB & ASSEMBLY

What is High Speed PCB Design?

We will explore what classifies as a high speed signal, associated design

What Qualifies as a High Speed Signal?

PCB Manufacturing & Assembly Services https://www.raypcb.com/

High Speed Challenges

Sudden impedance changes along a trace cause partial signal reflections

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Rapidly changing currents radiate energy as electrical noise. It couples into

Some general guidelines when laying out high speed signals:

 Keep traces short as possible

 Minimize vias and bends

 Maintain steady uniform impedance

 Provide shielding and distance between signals

 Carefully reference signals to ground planes

Next we see how to apply these in practice.

High Speed Routing Techniques

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Matching trace impedance to terminals prevents reflections. This is measured

Adjacent layer reference planes also help control impedance.

Adding coplanar ground floods or ground traces on adjacent layers shields

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Mitigating Via Effects

Vias intrinsically disturb signals passing through the barrel connection:

3. Ground stitching vias also redirect return current flow.

Some via mitigation and avoidance methods help:

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Analyzing High Speed Channel Performance

To validate high speed interface integrity prior to full system integration,

3D field solvers model entire PCB stackups detecting impedance

Lumped Circuit Models

Vector Network Analyzers

Swept frequency S-parameter testing measures insertion loss and reflection

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Time Domain Reflectometers

Eye Diagram Analysis

Overlaying repeated symbol periods on an oscilloscope reveals noise impact on

The Continuing Rise of High Speed Digital

Rapid improvements in integrated circuits, fabrication processes and interface

PCB Manufacturing & Assembly Services https://www.raypcb.com/

It is an exciting era pushing boundaries of high density integration and

Enabling Technologies Driving Speed Improvements

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Advances helping accelerate PCB interconnect capabilities include:

Faster Switching ICs

Low Loss Dielectrics

Tighter Design Rules

Fine Line Fab Limit Pushing

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Enabling more layer transitions maintains impedance integrity. Stacking and

The Future — Will Limitations Emerge?

Can the pace of increased frequencies continue indefinitely? At some point

 Shrinking insulator thicknesses struggle avoiding pinholes and

 Fabricating smaller microvias and matching pad transitions becomes

 PCB embedded actives introduce thermal and coefficient of expansion

While ingenious solutions continue advancing limits, they demand higher

PCB Manufacturing & Assembly Services https://www.raypcb.com/

Economic factors may eventually dominate sheer technical capability in