CD54AC112, CD74AC112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

D AC Types Feature 1.5-V to 5.5-V Operation CD54AC112 . . . F PACKAGE

and Balanced Noise Immunity at 30% of the CD74AC112 . . . E OR M PACKAGE
(TOP VIEW)
Supply Voltage
D Speed of Bipolar F, AS, and S, With 1CLK 1 16 VCC
Significantly Reduced Power Consumption 1K 2 15 1CLR
D Balanced Propagation Delays 1J 3 14 2CLR
D ±24-mA Output Drive Current 1PRE 4 13 2CLK
– Fanout to 15 F Devices 1Q 5 12 2K
D SCR-Latchup-Resistant CMOS Process and 1Q 6 11 2J
Circuit Design 2Q 7 10 2PRE

D Exceeds 2-kV ESD Protection Per

GND 8 9 2Q

MIL-STD-883, Method 3015

description/ordering information
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – E Tube CD74AC112E CD74AC112E
Tube CD74AC112M
–55°C
55°C to 125°C SOIC – M AC112M
Tape and reel CD74AC112M96
CDIP – F Tube CD54AC112F3A CD54AC112F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X H† H†
H H ↓ L L Q0 Q0
H H ↓ H L H L
H H ↓ L H L H
H H ↓ H H Toggle
H H H X X Q0
Q0
† Output states are unpredictable if PRE and CLR go high
simultaneously after both being low at the same time.

logic diagram (positive logic)

Q Q

PRE CLR

K J

CLK

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

recommended operating conditions (see Note 3)

–55°C to –40°C to
TA = 25°C
125°C 85°C UNIT
MIN MAX MIN MAX MIN MAX
VCC Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
VCC = 1.5 V 1.2 1.2 1.2
VIH High-level input voltage VCC = 3 V 2.1 2.1 2.1 V
VCC = 5.5 V 3.85 3.85 3.85
VCC = 1.5 V 0.3 0.3 0.3
VIL Low-level input voltage VCC = 3 V 0.9 0.9 0.9 V
VCC = 5.5 V 1.65 1.65 1.65
VI Input voltage 0 VCC 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC 0 VCC V
IOH High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA
IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA
VCC = 1.5 V to 3 V 50 50 50
∆t/∆v Input transition rise or fall rate ns/V
VCC = 3.6 V to 5.5 V 20 20 20
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
–55°C to –40°C to
TA = 25°C
PARAMETER TEST CONDITIONS VCC 125°C 85°C UNIT
MIN MAX MIN MAX MIN MAX
1.5 V 1.4 1.4 1.4
IOH = –50 µA 3V 2.9 2.9 2.9
4.5 V 4.4 4.4 4.4
VOH VI = VIH or VIL IOH = –4 mA 3V 2.58 2.4 2.48 V
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA† 5.5 V 3.85
IOH = –75 mA† 5.5 V 3.85
1.5 V 0.1 0.1 0.1
IOL = 50 µA 3V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
VOL VI = VIH or VIL IOL = 12 mA 3V 0.36 0.5 0.44 V
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA† 5.5 V 1.65
IOL = 75 mA† 5.5 V 1.65
II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
Ci 10 10 10 pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unless
otherwise noted)
–55°C to –40°C to
125°C 85°C UNIT
MIN MAX MIN MAX
fclock Clock frequency 8 9 MHz
CLK high or low 63 55
tw Pulse duration ns
CLR or PRE low 56 49
tsu Setup time, before CLK↓ J or K 50 44 ns
th Hold time, after CLK↓ J or K 0 0 ns
trec Recovery time, before CLK↓ CLR↑ or PRE↑ 31 27 ns

timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted)
–55°C to –40°C to
125°C 85°C UNIT
MIN MAX MIN MAX
fclock Clock frequency 71 81 MHz
CLK high or low 7 6
tw Pulse duration ns
CLR or PRE low 6.3 5.5
tsu Setup time, before CLK↓ J or K 5.6 4.9 ns
th Hold time, after CLK↓ J or K 0 0 ns
trec Recovery time, before CLK↓ CLR↑ or PRE↑ 3.5 3..1 ns

timing requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V
(unless otherwise noted)
–55°C to –40°C to
125°C 85°C UNIT
MIN MAX MIN MAX
fclock Clock frequency 100 114 MHz
CLK high or low 5 4.4
tw Pulse duration ns
CLR or PRE low 4.5 3.9
tsu Setup time, before CLK↓ J or K 4 3.5 ns
th Hold time, after CLK↓ J or K 0 0 ns
trec Recovery time, before CLK↓ CLR↑ or PRE↑ 2.5 2.2 ns

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

switching characteristics over recommended operating free-air temperature range,

VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
–55°C to –40°C to
FROM TO 125°C 85°C
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX
fmax 8 9 MHz
CLK 129 117
tPLH Q or Q ns
CLR or PRE 153 139
CLK 129 117
tPHL Q or Q ns
CLR or PRE 153 139

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
–55°C to –40°C to
FROM TO 125°C 85°C
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX
fmax 71 81 MHz
CLK 3.6 14.4 3.7 13.1
tPLH Q or Q ns
CLR or PRE 4.3 17.1 4.4 15.5
CLK 3.6 14.4 3.7 13.1
tPHL Q or Q ns
CLR or PRE 4.3 17.1 4.4 15.5

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
–55°C to –40°C to
FROM TO 125°C 85°C
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX
fmax 100 114 MHz
CLK 2.6 10.3 2.7 9.4
tPLH Q or Q ns
CLR or PRE 3.1 12.2 3.2 11.1
CLK 2.6 10.3 2.7 9.4
tPHL Q or Q ns
CLR or PRE 3.1 12.2 3.2 11.1

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TYP UNIT
Cpd Power dissipation capacitance 56 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003

PARAMETER MEASUREMENT INFORMATION

2 × VCC TEST S1
R1 = 500 Ω† S1
From Output Open tPLH/tPHL Open
Under Test GND tPLZ/tPZL 2 × VCC
tPHZ/tPZH GND
CL = 50 pF R2 = 500 Ω†
(see Note A)

tw
VCC
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
Input 50% VCC 50% VCC
LOAD CIRCUIT 0V
VOLTAGE WAVEFORMS
PULSE DURATION

VCC
VCC Reference
Input 50% VCC
CLR 50% VCC 0V
Input
0V
tsu th
trec VCC
Data 90% 90%
VCC 50% 50% VCC
Input 10% 10% 0 V
CLK 50% VCC
0V tr tf

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VCC
Input 50% VCC 50% VCC VCC
Output
50% VCC 50% VCC
0V Control
0V
tPLH tPHL
tPZL tPLZ
In-Phase VOH Output
90% 90% ≈VCC
Output 50% 50% VCC Waveform 1
10% 10% 50% VCC 20% VCC
VOL S1 at 2 × VCC
tr tf (see Note B) VOL
tPHL tPLH
tPZH tPHZ
VOH
Out-of-Phase 90% 90% Output
50% VCC 50% VOH
Output 10% 10% Waveform 2
VOL 50% VCC 80% VCC
S1 at GND
tf tr (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
CD54AC112F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
CD74AC112E ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD74AC112EE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
CD74AC112M ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC112M96 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC112M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC112ME4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

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Addendum-Page 1
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