SN74LVC1G86

SINGLE 2-INPUT EXCLUSIVE-OR GATE

SCES222F – APRIL 1999 – REVISED DECEMBER 2001

D Available in the Texas Instruments DBV OR DCK PACKAGE

NanoStar Package (TOP VIEW)

D Supports 5-V VCC Operation

A 1 5 VCC
D Ioff Supports Partial-Power-Down Mode B 2
Operation GND 3 4 Y
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II YEA PACKAGE
D ESD Protection Exceeds JESD 22 (BOTTOM VIEW)
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A) GND 3 4 Y
– 1000-V Charged-Device Model (C101) B 2
A 1 5 VCC
description
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING‡
NanoStar
Tape and reel SN74LVC1G86YEAR _ _ _CH_
WCSP (DSBGA) – YEA
–40°C
40°C to 85°C
SOT (SOT-23) – DBV Tape and reel SN74LVC1G86DBVR C86_
SOT (SC-70) – DCK Tape and reel SN74LVC1G86DCKR CH_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
‡ DCK/DBV: The actual top-side marking has one additional character that designates the assembly/test site.
YEA: The actual top-side marking has three preceding characters to denote year, month, and sequence
code, and one following character to designate the assembly/test site.

FUNCTION TABLE
INPUTS OUTPUT
A B Y
L L L
L H H
H L H
H H L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222F – APRIL 1999 – REVISED DECEMBER 2001

exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
=1

These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.

LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT

= 2k 2k + 1

The output is active (low) if The output is active (low) if The output is active (high) if
all inputs stand at the same an even number of inputs an odd number of inputs
logic level (i.e., A = B). (i.e., 0 or 2) are active. (i.e., only 1 of the 2) are
active.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

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 SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222F – APRIL 1999 – REVISED DECEMBER 2001

recommended operating conditions (see Note 4)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High level input voltage
High-level V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low level input voltage
Low-level V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222F – APRIL 1999 – REVISED DECEMBER 2001

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT
IOH = –100 µA 1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±5 µA
Ioff VI or VO = 5.5 V 0 ±10 µA
ICC VI = VCC or GND, IO = 0 1.65 V to 5.5 V 10 µA
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µA
Ci VI = VCC or GND 3.3 V 6 pF
† All typical values are at VCC = 3.3 V, TA = 25°C.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 3.5 9.9 1.8 5.5 1.3 5 1 4 ns

operating characteristics, TA = 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 22 22 22 24 pF

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 SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222F – APRIL 1999 – REVISED DECEMBER 2001

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH – V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

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