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    Lab Assignment 1:: Design Issues

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    Abdul Wasay Jawaid
    This document describes Lab Assignment 3 which involves designing and simulating 4-bit ripple carry adders and subtractors using Verilog. It first discusses the theory behind 4-bit ripple carry adders using full adders with carry bits "ripping" to the next stage. It then shows the Verilog module code for the adder along with a test fixture and sample waveform. Next, it covers the theory of 4-bit subtractors using two's complement notation and full adders, with the borrow bit fed to the carry in. Finally, it provides the Verilog module code for the 4-bit subtractor and test fixture.

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    © All Rights Reserved
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    Lab Assignment 1:: Design Issues

    Uploaded by

    Abdul Wasay Jawaid
    41 views6 pages
    This document describes Lab Assignment 3 which involves designing and simulating 4-bit ripple carry adders and subtractors using Verilog. It first discusses the theory behind 4-bit ripple carry adders using full adders with carry bits "ripping" to the next stage. It then shows the Verilog module code for the adder along with a test fixture and sample waveform. Next, it covers the theory of 4-bit subtractors using two's complement notation and full adders, with the borrow bit fed to the carry in. Finally, it provides the Verilog module code for the 4-bit subtractor and test fixture.

    Original Description:

    digital system design making a 4 bit ripple carry adder !!

    Original Title

    Talha Lab3 DSD

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    This document describes Lab Assignment 3 which involves designing and simulating 4-bit ripple carry adders and subtractors using Verilog. It first discusses the theory behind 4-bit ripple carry adders using full adders with carry bits "ripping" to the next stage. It then shows the Verilog module code for the adder along with a test fixture and sample waveform. Next, it covers the theory of 4-bit subtractors using two's complement notation and full adders, with the borrow bit fed to the carry in. Finally, it provides the Verilog module code for the 4-bit subtractor and test fixture.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    41 views6 pages

    Lab Assignment 1:: Design Issues

    Uploaded by

    Abdul Wasay Jawaid
    This document describes Lab Assignment 3 which involves designing and simulating 4-bit ripple carry adders and subtractors using Verilog. It first discusses the theory behind 4-bit ripple carry adders using full adders with carry bits "ripping" to the next stage. It then shows the Verilog module code for the adder along with a test fixture and sample waveform. Next, it covers the theory of 4-bit subtractors using two's complement notation and full adders, with the borrow bit fed to the carry in. Finally, it provides the Verilog module code for the 4-bit subtractor and test fixture.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    LAB #3

    Lab Assignment 1:
    Design and simulate a 4-bit ripple carry adder using 4 full adders.

    THEORY

    4 BIT RIPPLE CARRY ADDER

    Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be
    implemented in digital computers using basic gates like AND, OR, NOR, NAND etc. Among all the
    arithmetic operations if we can implement addition then it is easy to perform multiplication (by
    repeated addition), subtraction (by negating one operand) or division (repeated subtraction).

    Half Adders can be used to add two one-bit binary numbers. It is also possible to create a logical
    circuit using multiple full adders to add N-bit binary numbers. Each full adder inputs a Cin, which is
    the Cout of the previous adder. This kind of adder is a Ripple Carry Adder, since each carry bit
    "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half
    adder. The block diagram of 4-bit Ripple Carry Adder is shown here below -

    Circuit Diagram

    DESIGN ISSUES:

    The corresponding Boolean expressions are given here to construct a ripple carry adder. In the half
    adder circuit, the sum and carry bits are defined as

    sum = A ⊕ B

    carry = AB

    Name: Muhammad Talha Saleem Roll no:2017-CE-103


    LAB #3

    Verilog Module Code:

    module ripplecarry(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] s,
    output cout);
    wire c1,c2,c3;

    fulladder FA0(
    .a(a[0]),
    .b(b[0]),
    .cin(cin),
    .sum(s[0]),
    .cout(c1));

    fulladder FA1(
    .a(a[1]),
    .b(b[1]),
    .cin(c1),
    .sum(s[1]),
    .cout(c2));

    fulladder FA2(
    .a(a[2]),
    .b(b[2]),
    .cin(c2),
    .sum(s[2]),
    .cout(c3));

    fulladder FA3(
    .a(a[3]),
    .b(b[3]),
    .cin(c3),
    .sum(s[3]),
    .cout(cout));

    endmodule

    Name: Muhammad Talha Saleem Roll no:2017-CE-103


    LAB #3

    Verilog Test Fixture


    module ripplecarry_tv;

    // Inputs
    reg [3:0] a;
    reg [3:0] b;
    reg cin;

    // Outputs
    wire [3:0] s;
    wire cout;

    // Instantiate the Unit Under Test (UUT)


    ripplecarry uut (
    .a(a),
    .b(b),
    .cin(cin),
    .s(s),
    .cout(cout));

    // Initialize Inputs
    initial begin
    a = 4'b0010; b = 4'b0001; cin =0;
    #200a = 4'b0011; b = 4'b0011; cin =0;
    #200a = 4'b0100; b = 4'b0101; cin =0;#200;
    end
    endmodule

    Waveform:

    Name: Muhammad Talha Saleem Roll no:2017-CE-103


    LAB #3

    Lab Assignment 2:
    Design and simulate a 4-bit subtractor using 4 full adders.

    THEORY

    4 BIT SUBTRACTOR
    By using full–adder, binary subtraction can be performed by following the standard rule from
    arithmetic: A – B = A + (–B). We just need to negate one of the inputs to the full–adder and
    we have a subtractor. How do we do that?
    All modern Arithmetic Logic Units implement integer arithmetic using the two’s–complement
    form. Thus we need to build a two’s–complement negator. As an aside, we note that it is
    possible to build an adder/subtractor for other formats, but that these designs are quite complex.
    It is the simplicity of the standard two’s–complement unit that lead to its being the standard.
    Remember the rule for negating an integer in two’s–complement arithmetic: take the
    one’s–complement and add one. As an expression, this is as follows:

    In order to get the negative of the number, all we need to do is add 1 to it. Of the several ways
    this could be done, the best way is to set the carry–in of the units full–adder to 1.

    Circuit Diagram

    Consider the case when A#/S = 0. This indicates that addition is to take place. This signal
    is fed into the exclusive OR gates feeding the right inputs of the adders, passing the plain form
    of the B input. This feeds the units carry–in; the result is A + B + 0, or just A + B.
    Now consider the case when A#/S = 1. This indicates that subtraction is to take place. This
    is fed into the exclusive OR gates, passing the one’s complement of B into the right inputs of
    the adder. The signal feeds the units carry–in, thus the result we get is
    .

    Name: Muhammad Talha Saleem Roll no:2017-CE-103


    LAB #3

    Verilog Module Code:

    module ripplecarry(
    input [3:0] a,
    input [3:0] b,
    input cin,
    output [3:0] s,
    output cout);
    wire c1,c2,c3;

    fulladder FA0(
    .a(a[0]),
    .b(b[0] ^ cin),
    .cin(cin),
    .sum(s[0]),
    .cout(c1));

    fulladder FA1(
    .a(a[1]),
    .b(b[1] ^ cin),
    .cin(c1),
    .sum(s[1]),
    .cout(c2));

    fulladder FA2(
    .a(a[2]),
    .b(b[2] ^ cin),
    .cin(c2),
    .sum(s[2]),
    .cout(c3));

    fulladder FA3(
    .a(a[3]),
    .b(b[3] ^ cin),
    .cin(c3),
    .sum(s[3]),
    .cout(cout));
    Endmodule

    Name: Muhammad Talha Saleem Roll no:2017-CE-103


    LAB #3

    Verilog Test Fixture


    module ripplecarry_tv;

    // Inputs
    reg [3:0] a;
    reg [3:0] b;
    reg cin;

    // Outputs
    wire [3:0] s;
    wire cout;

    // Instantiate the Unit Under Test (UUT)


    ripplecarry uut (
    .a(a),
    .b(b),
    .cin(cin),
    .s(s),
    .cout(cout));

    // Initialize Inputs
    initial begin
    a = 4'b1111; b = 4'b1110; cin =1;
    #200a = 4'b1010; b = 4'b1010; cin =1;
    #200a = 4'b0111; b = 4'b0100; cin =1;#200;
    end
    endmodule

    Waveform

    Name: Muhammad Talha Saleem Roll no:2017-CE-103

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