Scribd Logo
Upload

Welcome to Scribd!

  • 97 views

    VHDL2

    Uploaded by

    Jorge Alberto Ceballos Sabido
    This document describes a lab exercise on modeling and simulating ripple carry adders and subtractors using VHDL. It discusses implementing a 4-bit ripple adder and subtractor in VHDL using vectors and components. It also describes how to use a subtractor circuit to compare two 4-bit numbers and determine if they are equal by checking if the result is 0, with no overflow. The full VHDL code for the 4-bit adder and comparator circuit is provided.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    VHDL2

    Uploaded by

    Jorge Alberto Ceballos Sabido
    97 views4 pages
    This document describes a lab exercise on modeling and simulating ripple carry adders and subtractors using VHDL. It discusses implementing a 4-bit ripple adder and subtractor in VHDL using vectors and components. It also describes how to use a subtractor circuit to compare two 4-bit numbers and determine if they are equal by checking if the result is 0, with no overflow. The full VHDL code for the 4-bit adder and comparator circuit is provided.

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes a lab exercise on modeling and simulating ripple carry adders and subtractors using VHDL. It discusses implementing a 4-bit ripple adder and subtractor in VHDL using vectors and components. It also describes how to use a subtractor circuit to compare two 4-bit numbers and determine if they are equal by checking if the result is 0, with no overflow. The full VHDL code for the 4-bit adder and comparator circuit is provided.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    97 views4 pages

    VHDL2

    Uploaded by

    Jorge Alberto Ceballos Sabido
    This document describes a lab exercise on modeling and simulating ripple carry adders and subtractors using VHDL. It discusses implementing a 4-bit ripple adder and subtractor in VHDL using vectors and components. It also describes how to use a subtractor circuit to compare two 4-bit numbers and determine if they are equal by checking if the result is 0, with no overflow. The full VHDL code for the 4-bit adder and comparator circuit is provided.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    LAB-2 (Combinational Circuits) Ripple Carry Adder / Subtractor

    Lab Objective:1- To Model and Simulate Ripple Carry Adders and Subtractors 2- Introducing Components in VHDL. Example: The VHDL Code for the 4-bit Ripple Adder. (Low Level of Abstraction)

    Prepared By: Aws Yousif Al-Taie Computer Science & Engineering Department

    Command Window

    Wave form Window

    Process Statement
    Process (a, b, c) Process executed whenever there is a change on a signal in the sensitivity list. Statements executed in sequential order. All the statements inside the process block will run simultaneously, at the same time.

    Using Vectors
    Instead of naming each wire separately, we group them together and give them a common name For example, in a 4-bit adder, we use four inputs x3,x2,x1,x0 We can also declare a vector called X. X :in bit_vector(3 downto 0); X(3), X(2), X(1), X(0) can be referred individually We can declared a vector in ascending or descending order, as shown: X:in bit_vector(3 downto 0) or X:in bit_vector(0 to 3)

    Lab Excercise-1: Modify the 4-bit ripple adder design and the VHDL code to perform a ripple binary subtractor only, using a ripple binary adder. Use 2's Compliment representation for negative numbers. Dont use the process statement in your VHDL code.
    Subtracting a = 0001 from b = 0010 will yield to sum = F (Explain and then justify your answer)

    Adder/Subtractor: We can design a single logic circuit to perform both adder and subtractor, using the following fact:

    Prepared By: Aws Yousif Al-Taie Computer Science & Engineering Department

    Lab Excercise-2: In computer computation it is often necessary to compare numbers. Two four bits numbers, X = x3x2x1x0 and Y = y3y2y1y0, can be compared by using the subtracter circuit, which performs the operation X Y. The Z output denotes the following: Z = 1 if the result is 0; otherwise Z = 0 Show how Z can be used to determine the case X = Y, in other words show that X Y = 0. Check to see if you have an overflow bit from the subtraction. Finally write the VHDL code for this circuit, based on the above fact. Using Components:-

    .
    entity FullAdder is port( X,Y,Cin:in bit; Cout,Sum:out bit ); end entity; architecture function_adder of FullAdder is begin Sum<=X xor Y xor Cin; Cout<=(X and Y) or (Cin and (X xor Y)); end architecture; entity Adder4 is port (A, B: in bit_vector(3 downto 0); Ci: in bit; S: out bit_vector(3 downto 0); Co: out bit); end Adder4; architecture Structure of Adder4 is component FullAdder port (X, Y, Cin: in bit; Cout, Sum: out bit); end component; signal C: bit_vector(3 downto 1); begin --instantiate four copies of the FullAdder FA0: FullAdder port map (A(0), B(0), Ci, C(1), S(0)); FA1: FullAdder port map (A(1), B(1), C(1), C(2), S(1)); FA2: FullAdder port map (A(2), B(2), C(2), C(3), S(2)); FA3: FullAdder port map (A(3), B(3), C(3), Co, S(3)); end Structure;

    Note that the order of the signals in the port map must be the same as the order of the signals in the port of the component declaration.

    Prepared By: Aws Yousif Al-Taie Computer Science & Engineering Department

    From the figure below, notice that we have two entities and two architectures in the Designs tab, as shown in the screen below.

    Prepared By: Aws Yousif Al-Taie Computer Science & Engineering Department

    You might also like