VLSI LAB

Electrical Engineering Department

Lab Report : 08
Date Flow Modelling
Submitted to:
Sir Asad Ur Rahman

Submitted by:
M.Bilawal Bhutto (200401016)
Shaheer Arshad (200401014)
Amna Ahmad (200401031)
, 200401014, 200401011

Batch: 19(A) 2023

 Objective:
The objectives of this lab are to:
• To Design Arithmetic and Logic Unit (ALU)
• Implement 4-bit Adder using 1-bit Adder
• Implement 2x2 Multiplier
• Implement 8x1 MUX(Tertiary Operator)
• Implement BCD to 7-Segment Decoder
• Implement 4 bit binary to gray converter
• Implement program flow control using the ?: operator:

Equipment:
• Nexys4 DDR
• XILINX VIVADO

Introduction:
This lab is based on performing different task in Verilog using Data flow modeling. Assign key
word used for data flow modeling. Here is introduction of lab tasks that are being performed in
this lab.

1. Arithmetic and Logic Unit (ALU):

Design and implement an ALU in Verilog that performs eight different arithmetic and
logical operations on binary data by using Assign key word. In this task we will have 8 operation,
2 4-bit inputs, and 3-bit opcode.

2. 4-bit Adder using 1-bit Adder:

Implement a 4-bit adder using 1-bit adder. In this task we will call 1 bit adder four time
for 4-bit.

3.1 2x2 Multiplier:

• Design and implement a 2x2 multiplier using assign key word. In this task we will have two
input, one output and select of 1 bit.

3.2 8x1 MUX (Tertiary Operator):

Implement an 8x1 multiplexer using dataflow modeling and the ?: operator. Understand
the conditional behavior of the ?: operator and its applications in data selection. In this we
have 8 inputs, one output and 4-bit select.
3.3 BCD to 7-Segment Decoder:

Design and implement a decoder circuit that converts Binary-Coded Decimal (BCD)
values to corresponding 7-segment LED displays. In this task we will have 4 inputs , seven
output and one 7-bit output.

3.4 4-bit Binary to Gray Converter:

Implement a circuit that converts 4-bit binary numbers to their equivalent Gray code
representations. Understand the relationship between binary and Gray codes and their
applications.

4. Program Flow Control using ?: Operator:

Implement program flow control logic using the ?: operator in a single line of Verilog
code. Demonstrate the conciseness and efficiency of the ?: operator in conditional branching.

This lab will provide you with a solid foundation in Verilog dataflow modeling. You with the
necessary skills to design and implement various digital circuits and there Test bench files for
simulation.

All task will be performed using Data flow modeling(assign). XILINX VIVADO software will
be used to perform tasks. Nexys4 DDR FPGA board will be used for implementation. We can
also use zed board. In this we have to create two files one for main design (.v file) and other one
for testing generally as test bench file(simulation file). In test bench we have to specify inputs.
Test bench file is used only for simulation purpose to check weather our design working properly
or not. If design will work properly then we will move to hardware. For hardware we have to
create a user constrain file(UCF) file. In which we have to specify input and output pins of circuit
with hardware pins. Here is the general procedure to perform tasks on XILINX VIVADO
software.

Procedure:
• Open Vivado and click Create Project.
• You will see given window. Click on next:

• Click on next. You will see given Window:

• Click on next and select Nexys4 DDR FPGA Board:

• click on next and Finish:

• Project manager window will appear:

• In sources click add sources. And select Add or create design sources to create Main.v
file
• Click Next. Add sources window will appear.

• Click on create file and create:

• Double click on .v file:

• Again click on add source and create simulation file:

• Create simulation (tb) file:

• Click on finish button:

• Now write main code to design main.
• After completing design create a test bench file to check model.
• After creating both file click on the run behavioral simulation and check the wave form:

• After checking waveform check the schematic by given window:

• Take the screen shots of circuit and simulation wave form:

• Copy both main.v code and test bench code.
• Add them in lab report.
Lab Task 1: Design an Arithmetic and Logic Unit (ALU) that implements 8 functions.
Main code Test bench
module ALU(a, b, ans, op_code); module ALU_TB();
input [4:0] a, b; reg [4:0] a, b;
input [2:0] op_code; reg [2:0] op_code;
output [5:0] ans; wire [5:0] ans;

assign ans = (op_code == 3'b000) ? a + b : ALU uut(a, b, ans, op_code);

(op_code == 3'b001) ? a - b :
(op_code == 3'b010) ? a * b : initial
(op_code == 3'b011) ? a / b : begin
(op_code == 3'b100) ? a ^ b : op_code=3'b000; a =5'b01011; b =5'b01010
(op_code == 3'b101) ? ~(a ^ b) : ;
(op_code == 3'b110) ? (~b) : #10 op_code=3'b001; a =5'b01011; b
(op_code == 3'b111) ? (~a) : =5'b01010 ;
6'b000000; // Default case, output 0 when none
of the conditions match #10 op_code=3'b010; a =5'b01011; b
=5'b01010 ;
endmodule
#10 op_code=3'b011; a =5'b01011; b
=5'b01010 ;

#10 op_code=3'b100; a =5'b01011; b

=5'b01010 ;

#10 op_code=3'b101; a =5'b01011; b

=5'b01010 ;

#10 op_code=3'b110; a =5'b01011; b

=5'b01010 ;

#10 op_code=3'b111; a =5'b01011; b

=5'b01010 ;

#10 $finish;
end

initial
begin
$display("ALU_Design ");
$monitor("time=%0d a=%b b=%b ans=%b
op_code=%b " , $time, a, b, ans, op_code);
end
endmodule
Wave Form:

TCL console:

Schematic:
Lab Task 2: Implement 4-bit Adder by instantiating four 1-bit Full Adder designed in data
flow modelling.

Main code Test bench

module FOUR_BIT_ADDER(a, b, cin, sum, module FOUR_BIT_ADDER_TB();
,cout); reg [3:0] a , b;
reg cin;
input [3:0] a, b; wire [3:0] sum;
input cin; wire cout;
output [3:0] sum;
output cout; FOUR_BIT_ADDER uut( a, b, cin, sum,
,cout);
wire carryout1, carryout2, carryout3,
carryout4; initial
begin
FULL_ADDER a0(a[0], b[0], cin, sum[0], cin=0;
carryout1); a =4'd3; b =4'd4;
FULL_ADDER a1(a[1], b[1], #10 a =4'd5; b =4'd7;
carryout1,sum[1], carryout2); #10 a=4'd9; b= 4'd15;
FULL_ADDER a2(a[2], b[2], #10 $finish;
carryout2,sum[2], carryout3);
FULL_ADDER a3(a[3], b[3], end
carryout3,sum[3], cout);
initial
endmodule begin
$display("FOUR_BIT_ADDER ");
$monitor("time=%0d a=%b b=%b
sum=%b cout=%b " , $time, a, b, sum,
module FULL_ADDER( a, b, cin, sum, cout ); cout);
input a , b, cin; end
output sum , cout;
wire sum0,carry0,carry1; endmodule

HALF_ADDER a1(a,b,sum0,carry0);
HALF_ADDER a2(cin,sum0, sum,carry1);
assign cout=carry0 + carry1;
endmodule

module HALF_ADDER( a, b, sum, carry );

input a , b;
output sum, carry;

assign sum = a ^ b;
assign carry = a & b;

endmodule
Wave Form:

Source window: here you can see 4 1-bit adder are called:

TCL console:
Schematic:

Lab Task 3: Implement following designs using Data Flow modelling.

• 2x2 Multiplier

Main code Test bench

module TWO_BIT_MULTIPLIER(a, b, cin, module TWO_BIT_MULTIPLIER_TB( );

sum, cout ); reg [1:0] a,b;
input [1:0] a,b; reg cin=0;
input cin; wire [3:0] sum;
output [3:0] sum; wire cout;
output cout; TWO_BIT_MULTIPLIER uut(a, b, cin, sum,
wire k1, k2, k3; cout );

assign sum[0]= a[0] & b[0]; initial

assign k1= b[0] & a[1]; begin
assign k2= b[1] & a[0]; a =2'b00; b =2'b00;
assign k3= b[1] & a[1]; #10 a =2'b01; b =2'b00;
assign cout= sum[3]; #10 a =2'b01; b =2'b01;
#10 a =2'b10; b =2'b10;
HALF_ADDER a1( k1, k2, sum[1], cin ); #10 a =2'b11; b =2'b10;
HALF_ADDER a2( k3, cin, sum[2], sum[3] );
#10 $stop;

endmodule end
initial
module HALF_ADDER( a, b, sum, cin ); begin
$display("TWO_BIT_MULTIPLIER");
input a , b; $monitor("time=%0d a=%b b=%b sum=%b
output sum, cin; cout=%b " , $time, a,b, sum, cout);
end
assign sum = a ^ b;
assign cin = a & b;
endmodule
endmodule

Wave Form:

TCL console:

Schematic:
Lab Task 3: Implement following designs using Data Flow modelling.
• 8x1 MUX(Tertiary Operator)

Main code Test bench

module MUX_8x1 ( module MUX_8x1_tb();
input [3:0]A, B, C, D, E, F, G, H,
input [2:0] select, reg [3:0] A, B, C, D, E, F, G, H;
output [3:0]mux_output reg [2:0] select;
); wire [3:0]mux_output;

assign mux_output = (select == 3'b000) ? A : MUX_8x1 uut( A, B, C, D, E, F, G, H, select,

(select == 3'b001) ? B : mux_output );
(select == 3'b010) ? C: initial begin
(select == 3'b011) ? D: select = 3'b000; A=3'B001; B=3'B010;
(select == 3'b100) ? E: C=3'B011; D=3'B100; E=3'B101; F=3'B110;
(select == 3'b101) ? F: G=3'B111; H=3'B000;
(select == 3'b110) ? G: #10 select = 3'b001; A=3'B001; B=3'B010;
(select == 3'b111) ? H: 1'b0; C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
endmodule #10 select = 3'b010; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 select = 3'b011; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 select = 3'b100; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 select = 3'b101; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 select = 3'b110; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 select = 3'b111; A=3'B001; B=3'B010;
C=3'B011; D=3'B100; E=3'B101; F=3'B110;
G=3'B111; H=3'B000;
#10 $finish;

end
initial
begin
$display("MUX_8X1");
$monitor("time=%0d A=%b B=%b C=%b
D=%b E =%b F=%b H=%b select=%b
mux_output=%b " , $time, A, B, C, D, E, F,
H ,select, mux_output);
end
endmodule
Wave Form:

TCL console:

Schematic:
Lab Task 3: Implement following designs using Data Flow modelling.
• BCD to 7-Segment Decoder

Main code Test bench

module bcdtoseven(a,b,c,d,e,f,g,A,B,C,D, module BCD_TO_SEVEN_SEGMENT_TB( );
Sev_bit_out); reg A,B,C,D;
input A,B,C,D; wire a,b,c,d,e,f,g;
output a,b,c,d,e,f,g; wire [6:0]Sev_bit_out;
output [6:0]Sev_bit_out; bcdtoseven
wire s1,s2,s3,s4; uut(a,b,c,d,e,f,g,A,B,C,D,Sev_bit_out);
initial
not n1(s1,A); begin
not n2(s2,B);
not n3(s3,C); A =1'b0; B =1'b0; C =1'b0; D =1'b0;
not n4(s4,D); #10 A =1'b0; B =1'b0; C =1'b0; D =1'b1;
#10 A =1'b0; B =1'b0; C =1'b1; D =1'b0;
assign a=A|C|(B&D)|(s2&s4); #10 A =1'b0; B =1'b0; C =1'b1; D =1'b1;
assign b=s2|(C&D)|(s3&s4); #10 A =1'b0; B =1'b1; C =1'b0; D =1'b0;
assign c=B|(s2&s3)|(C&D); #10 A =1'b0; B =1'b1; C =1'b0; D =1'b1;
assign #10 A =1'b0; B =1'b1; C =1'b1; D =1'b0;
d=(s2&s4)+(C&s4)+(B&s3&D)+(s2&C)|A; #10 A =1'b0; B =1'b1; C =1'b1; D =1'b1;
assign e=(C&s4)|(s2&s4); #10 A =1'b1; B =1'b0; C =1'b0; D =1'b0;
assign f=(s3&s4)|A|(B&s3)|(B&s4); #10 $stop;
assign g=A|(C&s4)|(B&s3)|(s2&C); end
assign Sev_bit_out={g,f,e,d,c,b,a}; initial
endmodule begin
$display("BCD_T0_ SEVEN_SEGMENT ");
$monitor("time=%0d a=%b b=%b c=%b
d=%b e=%b f=%b g=%b " , $time, a, b, c,
d, e, f, g);
end

endmodule
Wave Form:
TCL console:

Schematic:
Lab Task 3: Implement following designs using Data Flow modelling.
• bit binary to gray converter

Main code Test bench

module BinaryToGrayConverter( module BinaryToGrayConverter_tb();
input [3:0] binary_input,
output [3:0] gray_output reg [3:0] binary_input;
); wire [3:0] gray_output;

assign gray_output[0] = binary_input[0] ^ BinaryToGrayConverter uut(binary_input,

binary_input[1]; gray_output);
assign gray_output[1] = binary_input[1] ^ initial begin
binary_input[2];
assign gray_output[2] = binary_input[2] ^ binary_input = 4'b0000;
binary_input[3];
assign gray_output[3] = binary_input[3];
#5 binary_input = 4'b0001;
endmodule

#5 binary_input = 4'b0010;

#5 binary_input = 4'b0011;

$finish;
end

initial
begin
$display("4-bit binary to gray converter ");
$monitor("time=%0d binary_input=%b
gray_output=%b " , $time, binary_input,
gray_output);
end

endmodule
Wave Form:

TCL console:

Schematic:
Lab Task 4: . Design code for an assembler to manage program flow of a microprocessor
i.e. handle Program counter PC. Try to code the functionality in one line using ?: operators.PC is
16-bit. OFFSET is 8-bit but in 2’s complement. If reset flag is high, jump PC to 0000. If branch
flag is high, jump PC to PC + OFFSET.

Main code Test bench

module ProgramCounterManager(PC, module ProgramCounterManager_tb;
OFFSET, RESET, BRANCH, NEXT_PC );
input [15:0]PC; reg [15:0] PC;
input [7:0]OFFSET; reg [7:0] OFFSET;
input RESET, BRANCH ; reg RESET, BRANCH;
output [15:0]NEXT_PC; wire [15:0] NEXT_PC;
ProgramCounterManager uut(PC, OFFSET,
assign NEXT_PC = (RESET) ? (16'D10) : RESET, BRANCH, NEXT_PC);
((BRANCH ) ? PC + OFFSET : PC);
initial
endmodule begin
PC = 16'd5;
OFFSET = 8'd5;
BRANCH = 1'b1;
RESET = 1'b1;
#10
PC = 16'd5;
OFFSET = 8'd6;
BRANCH = 1'b1;
RESET = 1'b0;

$finish;
end
initial
begin
$display("PROGRAM COUNTER");
$monitor("time=%0d NEXT_PC=%b
OFFSET=%b BRANCH=%b " , $time,
NEXT_PC,OFFSET,BRANCH );
end

endmodule
Wave Form:

Schematic:

Conclusion:
In this lab we had performed multiple task with the help of Verilog (Data Flow modeling)
codding by using XILINX VIVADO software. We had also observed Schematic and simulation
of all tasks. Some of the tasks are mentioned below:
• Successfully Implemented Designed ALU
• Successfully Implemented 4-bit Adder using 1-bit Adder
• Successfully Implemented 2x2 Multiplier
• Successfully Implemented 8x1 MUX(Tertiary Operator)
• Successfully Implemented BCD to 7-Segment Decoder
• Successfully Implemented 4 bit binary to gray converter
• Successfully Implemented program flow control using the ?: operator: