DE - UNIT 2 - Dec 2018 Updated

UNIT II
COMBINATIONAL CIRCUITS DESIGN

Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead
Adder, BCD Adder, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority
Encoder.
COMBINATIONAL CIRCUITS
 The digital system consists of two types of circuits, namely
(i) Combinational circuits and
(ii) Sequential circuits
Combinational circuits
 A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs without regard to previous inputs or previous state of outputs..
 A combinational circuit performs an operation that can be specified logically by a set of Boolean
functions.
Sequential circuits:
 Sequential circuits contain logic gates as well as memory cells. Their outputs depend on the present
inputs and also on the states of memory elements.
 Since the outputs of sequential circuits depend not only on the present inputs but also on past inputs.
 The circuit behavior must be specified by a time sequence of inputs and memory states.
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DESIGN PROCEDURE
Explain the procedure involved in designing combinational circuits. (May 2015)
Any combinational circuit can be designed by the following steps of design procedure.
1. The problem is stated.
2. Identify the input variables and output functions.
3. The input and output variables are assigned letter symbols.
4. The truth table is prepared that completely defines the relationship between the input variables
and output functions.
5. The simplified Boolean expression is obtained by any method of minimization algebraic method,
Karnaugh map method, or tabulation method.
6. A logic diagram is realized from the simplified expression using logic gates.
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HALF ADDER
P.PARUTHI ILAM VAZHUTHI, Asst. Prof.,/ECE V.R.S College of Engineering & Technology, Arasur. Page 1
Construct a half adder with necessary diagrams. (Nov-06,May- 07)
 A half-adder is an arithmetic circuit block that can be used to add two bits and produce two outputs such
as SUM and CARRY.
 The Boolean expressions for the SUM and CARRY outputs are given by the equations
S=AꞌB + ABꞌ
C= AB
Truth Table: Symbol:
 The outputs S and C functions are similar to Exclusive-OR and AND functions respectively.
 Below Figure shows the logic diagram to implement the half-adder circuit.
Logic Diagram: Half adder using NAND gate:
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FULL ADDER
Design a full adder using NAND and NOR gates respectively. (Nov -10)
 A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two outputs
such as SUM and CARRY.
 Let us consider the input variables augend as A, addend as B, and previous carry as X, and outputs sum
as S and carry as C.
 As there are three input variables, eight different input combinations are possible.
Truth table:
Karnaugh map:
K-Map for Sum K-Map for Carry

 The simplified Boolean expressions of the outputs are
S = X′A′B + X′AB′ + XA′B′ + XAB
C = AB + BX + AX
Logic diagram:
 The Boolean expressions of S and C are modified as follows
Full adder using Two half adder:
 Logic diagram according to the modified expression is shown Figure.
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HALF SUBTRACTOR
Design a half subtractor circuit. (Nov-2009)
 A half-subtractor is a combinational circuit that can be used to subtract one binary digit from another to
produce a DIFFERENCE output and a BORROW output.
Truth table:
 Boolean expressions of the outputs D and B functions can be written as

D = X′Y + XY′
B = X′Y
Logic diagram:
 Figure shows the logic diagram to realize the half-subtractor circuit\
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FULL SUBTRACTOR
Design a full subtractor. (Nov-2009,07)

 A combinational circuit of full-subtractor performs the operation of subtraction of three bits such as the
minuend, subtrahend, and borrow generated from the subtraction operation of previous significant digits
and produces the outputs difference and borrow.
Truth table:
Karnaugh map:
K-Map for D K-Map for B

 The simplified Boolean expressions of the outputs are
S = X′Y′Z + X′YZ′ + XY′Z′ + XYZ
C = X′Z + X′Y + YZ
Logic diagram:
 The Boolean expressions of D and B are modified as follows
 Logic diagram according to the modified expression is shown Figure.
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PARALLEL BINARY ADDER: (RIPPLE CARRY ADDER)

Explain about four bit adder with neat diagram.
 Two binary bits can be added and the addition of two binary bits with a carry.
 In practical situations it is required to add two data each containing more than one bit.
 Two binary numbers each of n bits can be added by means of a full adder circuit.
 Consider the example that two 4-bit binary numbers B4 B3 B2 B1 and A4 A3 A2 A1 are to be added with a
carry input C1 .
 This can be done by cascading four full adder circuits as shown in Figure.
 The least significant bits A1, B1, and C1 are added to the produce sum output S1 and carry output C2 .
 Carry output C2 is then added to the next significant bits A2 and B2 producing sum output S2 and carry
output C3 .
 C3 is then added to A3 and B3 and so on. Thus finally producing the four-bit sum output S4 S3 S2 S1 and
final carry output Cout.
 Such type of four-bit binary adder is commercially available in an IC package.
Fig: 4 bit adder
 For the addition of two n bits of data, n numbers of full adders can be cascaded as demonstrated in
figure .
 It can be constructed with 4-bit, 2-bit, and 1-bit full adder IC packages.
 The carry output of one package must be connected to the carry input of the next higher order bit IC
package of higher order bits.
 The addition technique adopted here is a parallel type as all the bit addition operations are performed in
parallel. Therefore, this type of adder is called a parallel adder.
 The 4-bit parallel binary adder IC package is useful to develop combinational circuits.
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PARALLEL BINARY SUBTRACTOR
Explain about four bit subtractor with neat diagram.
 By 1ꞌs complement method, the bits of subtrahend are complemented and added to the minuend.
If any carry is generated it is added to the sum output.
 Below Figure demonstrates the subtraction of B4 B3 B2 B1 from A4 A3 A2 A1.
 Each bit of B4 B3 B2 B1 is first complemented by using INVERTER gates and added to A4 A3 A2
A1 by a 4-bit binary adder.
 End round carry is again added using the Cin pin of the IC.
Fig: 4 bit subtractor Example

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Fast adder (or) Carry Look Ahead adder

Design a carry look ahead adder circuit. (Nov-2010),(May 2018)
Fast Adder:
 Every logic gate offers some delay when the signal passes from its input to output, which is called the
propagation delay of the logic gate.
 So every combinational circuit takes some time to produce its correct output after the arrival of all the
input, which is called total propagation time.
 Total propagation time is equal to the propagation delay of individual gates times the number of gate
levels in the circuit.
 For a 4-bit parallel binary adder, carry propagation takes the longest propagation time.
 One method to reduce the propagation delay time is to use faster gates.
 Another technique is to employ a little more complex combinational circuit, which can reduce the
carry propagation delay time.
 The most widely used method employs the principle of look ahead carry generation, which is
illustrated below.
 The carry look ahead adder is based on the principle of looking at the lower order bits of the augend
and addend to see if a higher order carry is to be generated.
 It uses two functions carry generate and carry propagate.
 Consider the circuit of the full adder shown in Fig. It defines two new binary variables
 The output sum and carry can respectively be expressed as
 Gi is called a carry generate, and it generates an output carry if both the inputs Ai and Bi are logic 1,
regardless of the input carry.
 Pi is called the carry propagate because it is the term associated with the propagation of the carry
from Ci to Ci+1.
Fig: Logic diagram
 Boolean expressions for the carry output of each stage can be written after substituting C i and
Ci+1 as
 In fact, all the intermediate carry as well as the final carry C2, C3 , C4 , and C5 can be
implemented by only two levels of gates and available at the same time.
 The final carry C5 need not have to wait for the intermediate carry to propagate.
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BCD Adder
Design to perform BBCD addition. (May -08)(Dec 2017)
 Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a
previous stage.
 Since each input cannot exceed 9, the output sum must not exceed 9 + 9 + 1 = 19 (1 in the sum is input
carry from a previous stage).
 If a four-bit binary adder is used, the normal sum output will be of binary form and may exceed 9 or
carry may be generated. So the sum output must be converted to BCD form.
 Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and
produce a result that ranges from 0 through 19.
 These binary numbers are listed in table and are labeled by symbols K, Z8, Z4, Z2, and Z1.
 K is the carry, and the subscripts under the letter Z represent the weights 8, 4, 2, and 1 that can be
assigned to the four bits in the BCD code.
Fig: BCD Adder
Karnaugh map:
Z2 Z1
00 01 11 10
Z8 Z4
 A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Fig.
 The two decimal digits, together with the input carry, are first added in the top four-bit adder to produce
the binary sum.
 When the output carry is equal to 0, nothing is added to the binary sum. When it is equal to 1, binary
0110 is added to the binary sum through the bottom four-bit adder.
 The condition for a correction and an output carry can be expressed by the Boolean function
C = K + Z8Z4 + Z8Z2
 The output carry generated from the bottom adder can be ignored, since it supplies information already
available at the output carry terminal.
 A decimal parallel adder that adds n decimal digits needs n BCD adder stages.
 The output carry from one stage must be connected to the input carry of the next higher order stage.
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MULTIPLEXERS AND DEMULTIPLEXERS
Multiplexer: (MUX)
Design a 2:1 and 4:1 multiplexer.
 A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line.
 The selection of a particular input line is controlled by a set of selection lines.
 Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected.
2 to 1 MUX:
 A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one
input of an AND gate.
 Selection lines S are decoded to select a particular AND gate.
 To derive the gate level implementation of 2:1 MUX we need to have truth table as shown in figure.
 Boolean expression for output Y,
Y = A.S' + B.S
Logic Diagram:
4 to 1 MUX: (Illustrate the concept of basic 4 –input Multiplexer) (Dec2018)

 A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input of
an AND gate.
 Selection lines S0 and S1 are decoded to select a particular AND gate.
 The truth table for the 4:1 mux is given in the table below.
ogic Diagram: Logic Diagram
Truth Table:
SELECT OUTPUT
LINES
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
 Let us consider that select input combination S1 S0 is 01.
 The AND gate associated with I1 will have two of inputs equal to logic 1 and a third input is connected
to I1.
 Therefore, output of this AND gate is according to the information provided by channel I1.
 Other three AND gates have logic 0 to at least one of their inputs which makes their outputs to logic 0.
 Hence, OR output (Y) is equal to the data provided by the channel I1.
 Thus, information from I1 is available at Y. Normally a multiplexer has an ENABLE input to also
control its operation.
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Problems :
Example: Implement the Boolean expression using MUX
F(A,B,C,D) = ∑m(0,1,5,6,8,10,12,15) (May 2018)
Logic Diagram:
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Design 8-to-1 line multiplexer is realized by two 4-to-1 line multiplexers.
Design 16-to-1 multiplexer can be realized with five 4-to-1 multiplexers.
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DEMULTIPLEXERS:
Explain about demultiplexers.
 Demultiplexing is the process that receives information from one channel and distributes the data over
several channels.
 It is the reverse operation of the multiplexer.
 A demultiplexer is the logic circuit that receives information through a single input line and transmits
the same information over one of the possible 2n output lines.
 The selection of a specifi c output line is controlled by the bit combinations of the selection lines.
 Example: 1-to-4 De-multiplexer
Logic Diagram: Truth Table:
INPUT OUTPUT
E D S0 S1 Y0 Y1 Y2 Y3
1 1 0 0 1 0 0 0
1 1 0 1 0 1 0 0
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1
 Example: 1-to-8 De-multiplexer
Truth Table:
Logic diagram:
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Example:
1. Implement full adder using De-multiplexer.
2. Implement the following functions using de-multiplexer.
f1 (A,B,C) = ∑m(1,5,7), f2 (A,B,C) = ∑m(3,6,7)
Solution:
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COMPARATORS
Design a 2 bit magnitude comparator. (May 2006)
It is a combinational circuit that compares two numbers and determine their relative magnitude.
The output of comparator is usually 3 binary variables indicating:
A<B, A=B, A>B
1-bit comparator: Let’s begin with 1 bit comparator and from the name we can easily make out
that this circuit would be used to compare 1 bit binary numbers.
A B A>B A=B A<B

0 0 0 1 0
1 0 1 0 0
0 1 0 0 1
1 1 0 1 0
For a 2-bit comparator we have four inputs A1A0 and B1B0 and three output E ( is 1 if two
numbers are equal) G (is 1 when A > B) and L (is 1 when A < B) If we use truth table and K-map the
result is
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(Dec 2018)
K-map:
Logic Diagram:
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DECODERS AND ENCODERS

Decoder:
Explain about decoders with necessary diagrams.
 A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines.
 Decoders have a wide variety of applications in digital systems such as data demultiplexing, digital
display, digital to analog converting, memory addressing, etc.
 2 to 4 decoder:
3 to 8 Decoder:
Design 3 to 8 line decoder with necessary diagram. (May -10)
 The 3-to-8 line decoder consists of three input variables and eight output lines.
 Each of the output lines represents one of the minterms generated from three variables.
 The internal combinational circuit is realized with the help of INVERTER gates and AND gates.
Truth table:
Logic diagram:
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Example: Implement the function F (A,B,C) = Σ (1,3,5,6).
Design for 3 to 8 decoder with 2 to 4 decoder:
 Its enable inputs can be used to build a three to eight decoder as follows.
 When A2 is logic 0, a lower decoder is activated and gives output D0 to D3 and an upper decoder is
activated for A2 is logic 1, output D4 to D7 are available this time.
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Implementation of Boolean function using decoder:
 Since the three to eight decoder provides all the minterms of three variables, the realization of function
in terms of the sum of products can be achieved using a decoder and OR gates as follows.
Example: Implement full adder using decoder.
Sum is given by ∑m(1, 2, 4, 7) while Carry is given by ∑ m(3, 5, 6, 7) as given by the minterms
each of the OR gates are connected to.
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Design for 4 to 16 decoder using 3 to 8 decoder:
 A 4-to-16 line decoder has four input variables and sixteen outputs, whereas a 3-to-8 line
decoder consists of three input variables and eight outputs.
 Input variables are designated as W, X, Y, and Z.
 W input is used as the ENABLE input of the upper 3-to-8 line decoder, which provides D8 to D16
outputs depending on other input variables X, Y, and Z.
 W is also used as an ENABLE input at inverted mode to a lower decoder, which provides D0 to
D7 outputs.
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BCD to seven segment decoder
Design a BCD to seven segment code converter. (May-06,10, Nov- 09)
Truth table:
 The specification above requires that the output be zeroes (none of the segments are lighted up) when
the input is not a BCD digit.
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ENCODERS
Explain about encoders.
 An encoder is a digital circuit that performs the inverse operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines, as an aggregate, generate the binary code corresponding to the input value.
Octal to Binary Encoder:
 The encoder can be implemented with OR gates whose inputs are determined directly from the truth
table.
 Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
 Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7.
 These conditions can be expressed by the following Boolean output functions:
The encoder can be implemented with three OR gates.
Truth table:
Logic Diagram:
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Priority Encoder:
Design a priority encoder with logic diagram. (May 2017)
 Special type of encoder that senses when two or more inputs are activated simultaneously and
then generates a code corresponding to the highest numbered input.
Truth table:
K-Map:
Logic Equations:
Logic diagram:
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4 bit-Parallel adder/subtractor:
Explain about binary parallel / adder subtractor. (Dec 2018)
 The addition and subtraction operations can be combined into one circuit with one common binary adder
by including an exclusive-OR gate with each full adder.
 The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1, the
circuit becomes a subtractor.
 It performs the operations of both addition and subtraction.

 It has two 4bit inputs A3A2A1A0 and B3B2B1B0.
 The mode input M controls the operation when M=0 the circuit is an adder and when M=1 the circuits
become subtractor.
 Each exclusive-OR gate receives input M and one of the inputs of B .
 When M = 0, we have B xor0 = B. The full adders receive the value of B , the input carry is 0, and the
circuit performs A plus B . This results in sum S3S2S1S0and carry C4.
 When M = 1, we have B xor 1 = B’ and C0 = 1. The B inputs are all complemented and a 1 is added
through the input carry thus producing 2’s complement of B.
 Now the data A3A2A1A0will be added with 2’s complement of B3B2B1B0to produce the sum i.e., A-B if
A≥B or the 2’s complement of B-A if A<B.
Parity Checker / Generator:
 A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or
even. The message, including the parity bit, is transmitted and then checked at the receiving end for
errors. An error is detected if the checked parity does not correspond with the one transmitted.
 The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called a parity checker.
 In even parity system, the parity bit is ‘0’ if there are even number of 1s in the data and the parity bit
is ‘1’ if there are odd number of 1s in the data.
 In odd parity system, the parity bit is ‘1’ if there are even number of 1s in the data and the parity bit is
‘0’ if there are odd number of 1s in the data.
3-bit Even Parity generator: (Dec 2018)

Design an even parity generator , that generates an even parity bit for every input string of 3 bits.
Truth Table:
Logic Diagram:
4-bit Even parity checker:
Truth Table:
Logic Diagram:
TWO MARK QUESTIONS-ANSWERS
1) Define combinational logic. (May 2008), (Dec 2014)
A combinational circuit consists of logic gates whose outputs at any time are determined from
only the present combination of inputs. A combinational circuit performs an operation that can be
specified logically by a set of Boolean functions.
2) What is sequential circuits?

 Sequential circuits contain logic gates as well as memory cells. Their outputs depend on the
present inputs and also on the states of memory elements.
 Since the outputs of sequential circuits depend not only on the present inputs but also on past
inputs.
3) Write the design procedure for combinational circuits?

The procedure involves the following steps:
1. The problem is stated.
2. Identify the input variables and output functions.
3. The input and output variables are assigned letter symbols.
4. The truth table is prepared that completely defines the relationship between the input variables
and output functions.
5. The simplified Boolean expression is obtained by any method of minimization algebraic method,
Karnaugh map method, or tabulation method.
6. A logic diagram is realized from the simplifi ed expression using logic gates.
4) What is Half adder?

A half-adder is an arithmetic circuit block that can be used to add two bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations
5) Draw the logic diagram of half adder using NAND gate. (May 2006,13)
Logic Diagram: Half adder using NAND gate:
6) What is Full adder? (Dec 2013)
A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations
7) Draw the Logic diagram of full adder.
8) What is Half subtractor? (May 2005)

A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output.
The Boolean expression for difference and barrow is:
D = X′Y + XY′
B = X′Y
9) Draw Full adder using Two half adder. (May 2017) (Dec 2018)
10) What is Full subtractor?
A combinational circuit of full-subtractor performs the operation of subtraction of three
bits such as the minuend, subtrahend, and borrow generated from the subtraction operation of
previous significant digits and produces the outputs difference and borrow.
The Boolean expression for difference and barrow is:
S = X′Y′Z + X′YZ′ + XY′Z′ + XYZ
C = X′Z + X′Y + YZ
11) Draw Full subtractor using two half subtractor.
12) What is Parallel Binary Adder (Ripple Carry Adder)?
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full adder
connected to the input carry of the next full adder in the chain.
13) Draw the logic diagram for four bit binary parallel adder.
14) What is 1’s complement of a number?

The 1’s complement of a binary number is formed by changing 1 to 0 and 0 to 1.
Example:
1. The 1’s complement of 1011000 is 0100111.
2. The 1’s complement of 0101101 is 1010010.
15) What is 2’s complement of a number?
The 2’s complement of a binary number is formed by adding 1 with 1’s complement of a binary
number.
Example:
1) The 2’s complement of 1101100 is 0010100
2) The 2’s complement of 0110111 is 1001001
16) How Subtraction of binary numbers perform using 2’s complement addition?
 The subtraction of unsigned binary number can be done by means of complements.
 Subtraction of A-B can be done by taking 2’s complement of B and adding it to A.
 Check the resulting number. If carry present, the number is positive and remove the carry.
 If no carry present, the resulting number is negative, take the 2’s complement of result and put
negative sign.
17) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X by using 2’s complements.
Solution:
(a) X = 1010100
2’s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001
(b) Y = 1000011
2’s complement of X = + 0101100
Sum= 1101111
There is no end carry.
Therefore, the answer is Y - X = -(2’s complement of 1101111) = -0010001.
18) Draw the logic diagram of Parallel Binary Subtractor. (May 2018)
19) Draw the logic diagram of 2’s complement adder/subtractor. (May 2013)
The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1,
the circuit becomes a subtractor.
20) What is Magnitude Comparator? (Dec 2017)
The comparison of two numbers is an operation that determines whether one number is
greater than, less than, or equal to the other number.
A magnitude comparator is a combinational circuit that compares two numbers A and B and
determines their relative magnitudes.
The outcome of the comparison is specified by three binary variables that indicate whether
A > B, A = B, or A < B.
21) Design a 1-bit Magnitude Comparator.

Truth table:
22) What is Decoder? (Dec 2014))

A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines.
23) Give some applications of Decoders.
Decoders have a wide variety of applications in digital systems such as data
demultiplexing, digital display, digital to analog converting, memory addressing, etc.
24) Design a 3 to 8 decoder with 2 to 4 decoder.
25) What is Encoder? (May 2012)
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary
code corresponding to the input value.
26) What is Priority Encoder?

 A priority encoder is an encoder circuit that includes the priority function.
 Special type of encoder that senses when two or more inputs are activated simultaneously and
then generates a code corresponding to the highest numbered input.
27) Define Multiplexer (MUX) (or) Data Selector. (Dec 2006, May 2011)
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line.
The selection of a particular input line is controlled by a set of selection lines. Normally, there
are 2n input lines and n selection lines whose bit combinations determine which input is selected.
28) What is De-multiplexer?

The de-multiplexer performs the inverse function of a multiplexer, that is it receives information
on one line and transmits its onto one of 2n possible output lines. The selection is by n input
select lines.
29) Give the applications of Demultiplexer.
i) It finds its application in Data transmission system with error detection.
ii) One simple application is binary to Decimal decoder.
30) Mention the uses of Demultiplexer. (May 2015)

Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only
in computers, but any time information from one source can be fed to several places.
33) Give other name for Multiplexer and Demultiplexer.

Multiplexer is otherwise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
34) What is the function of the enable input in a Multiplexer?

The function of the enable input in a MUX is to control the operation of the unit.
35) List out the applications of decoder? (Dec 2006)
a. Decoders are used in counter system.
b. They are used in analog to digital converter.
c. Decoder outputs can be used to drive a display system.
36) What are the Application of MUX?

1. They are used as a data selector to select one output of many data inputs.
2. They can be used to implement combinational logic circuits
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
5. They are used in A/D & D/A Converter.
6. They are used in data acquisition system.
37) List out the applications of comparators?

a. Comparators are used as a part of the address decoding circuitry in computers to
select a specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the
reference value.
c. They are used in control applications.
38) What is carry look-ahead addition?

The speed with which an addition is performed limited by the time required for the carries to propagate or
ripple through all of the stage of the adder. One method of speeding up the process is by eliminating the
ripple carry delay.
39) What are the Difference between Decoder & Demux.?

S.No Decoder Demux
1 Decoder is a many inputs to many Demux is a single input to many outputs
outputs
2 There are no selection lines. The selection of specific output line is
controlled by the value of selection lines.

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UNIT II

COMBINATIONAL CIRCUITS DESIGN

Truth Table: Symbol:

Logic Diagram: Half adder using NAND gate:

K-Map for Sum K-Map for Carry

 The Boolean expressions of S and C are modiﬁed as follows

 Boolean expressions of the outputs D and B functions can be written as

Design a full subtractor. (Nov-2009,07)

K-Map for D K-Map for B

 The Boolean expressions of D and B are modiﬁed as follows

 Logic diagram according to the modiﬁed expression is shown Figure.

PARALLEL BINARY ADDER: (RIPPLE CARRY ADDER)

Fig: 4 bit adder

PARALLEL BINARY SUBTRACTOR

Explain about four bit subtractor with neat diagram.

Fig: 4 bit subtractor Example

Fast adder (or) Carry Look Ahead adder

 The output sum and carry can respectively be expressed as

Fig: Logic diagram

Fig: BCD Adder

MULTIPLEXERS AND DEMULTIPLEXERS

4 to 1 MUX: (Illustrate the concept of basic 4 –input Multiplexer) (Dec2018)

ogic Diagram: Logic Diagram

Design 8-to-1 line multiplexer is realized by two 4-to-1 line multiplexers.

Logic Diagram: Truth Table:

 Example: 1-to-8 De-multiplexer

A B A>B A=B A<B

DECODERS AND ENCODERS

Example: Implement the function F (A,B,C) = Σ (1,3,5,6).

Design for 3 to 8 decoder with 2 to 4 decoder:

Example: Implement full adder using decoder.

Octal to Binary Encoder:

The encoder can be implemented with three OR gates.

 It performs the operations of both addition and subtraction.

Parity Checker / Generator:

3-bit Even Parity generator: (Dec 2018)

TWO MARK QUESTIONS-ANSWERS

2) What is sequential circuits?

3) Write the design procedure for combinational circuits?

4) What is Half adder?

7) Draw the Logic diagram of full adder.

8) What is Half subtractor? (May 2005)

12) What is Parallel Binary Adder (Ripple Carry Adder)?

14) What is 1’s complement of a number?

20) What is Magnitude Comparator? (Dec 2017)

21) Design a 1-bit Magnitude Comparator.

22) What is Decoder? (Dec 2014))

24) Design a 3 to 8 decoder with 2 to 4 decoder.

25) What is Encoder? (May 2012)

26) What is Priority Encoder?

28) What is De-multiplexer?

30) Mention the uses of Demultiplexer. (May 2015)

33) Give other name for Multiplexer and Demultiplexer.

34) What is the function of the enable input in a Multiplexer?

36) What are the Application of MUX?

37) List out the applications of comparators?

38) What is carry look-ahead addition?

39) What are the Difference between Decoder & Demux.?

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