ACS770 Datasheet

ACS770xCB
Thermally Enhanced, Fully Integrated, Hall-Effect-Based

High-Precision Linear Current Sensor IC with 100 µΩ Current Conductor
FEATURES AND BENEFITS DESCRIPTION

• Industry-leading total output accuracy achieved with new The Allegro™ ACS770 family of current sensor ICs provides
piecewise linear digital temperature compensation of economical and precise solutions for AC or DC current sensing.
offset and sensitivity Typical applications include motor control, load detection and
• Industry-leading noise performance through proprietary management, power supply and DC-to-DC converter control,
amplifier and filter design techniques inverter control, and overcurrent fault detection.
• 120 kHz typical bandwidth
The device consists of a precision, low-offset linear Hall
• 4.1 µs output rise time in response to step input current
circuit with a copper conduction path located near the die.
• Integrated shield greatly reduces capacitive coupling
Applied current flowing through this copper conduction
from current conductor to die due to high dV/dt signals,
path generates a magnetic field that is concentrated by a low
and prevents offset drift in high-side, high-voltage
magnetic hysteresis core, then converted by the Hall IC into a
applications
proportional voltage. Device accuracy is optimized through the
• Greatly improved total output error through digitally
close proximity of the magnetic signal to the Hall transducer.
programmed and compensated gain and offset over the
A precise, proportional output voltage is provided by the
full operating temperature range
low-offset, chopper-stabilized BiCMOS Hall IC, which is
• Small package size, with easy mounting capability
programmed for accuracy at the factory. Proprietary digital
• Monolithic Hall IC for high reliability
temperature compensation technology greatly improves the
• Ultralow power loss: 100 µΩ internal conductor
IC accuracy and temperature stability without influencing the
resistance
high-bandwidth operation of the analog output.
• Galvanic isolation allows use in economical, high-side
current sensing in high-voltage systems High-level immunity to current conductor dV/dt and stray
• 4.5 to 5.5 V, single supply operation electric fields is offered by Allegro proprietary integrated shield
• Output voltage proportional to AC or DC currents technology for low output voltage ripple and low offset drift
• Factory-trimmed for accuracy in high-side, high-voltage applications.
• Extremely stable output offset voltage
The output of the device has a positive slope (>VCC/2 for
Continued on the next page… bidirectional devices) when an increasing current flows
through the primary copper conduction path (from terminal 4
PACKAGE: 5-pin package (suffix CB) to terminal 5), which is the path used for current sampling. The
internal resistance of this conductive path is 100 µΩ typical,
providing low power loss.
Continued on the next page…
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Certificate Number:
Leadform Leadform Leadform U8V 14 05 54214 037
Additional leadforms available for qualifying volumes
5V
1
4 VCC
Application 1: the ACS770 outputs an analog IP+ CBYP
signal, VOUT , that varies linearly with the ACS770 0.1 µF
bidirectional AC or DC primary sampled cur- 2
rent, IP , within the range specified. RF and IP GND
CF are for optimal noise management, with CF
values that depend on the application. 5
IP– 3
VIOUT VOUT
RF
Typical Application
ACS770-DS, Rev. 9 April 18, 2018

MCO-0000205
ACS770xCB High-Precision Linear Current Sensor IC with 100 µΩ Current Conductor
FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

• Undervoltage lockout for VCC below specification The thickness of the copper conductor allows survival of the device
• AEC Q-100 automotive qualified at high overcurrent conditions. The terminals of the conductive path
• UL certified, File No. E316429 are electrically isolated from the signal leads (pins 1 through 3). This
allows the ACS770 family of sensor ICs to be used in applications
requiring electrical isolation without the use of opto-isolators or
other costly isolation techniques.
The device is fully calibrated prior to shipment from the factory.
The ACS770 family is lead (Pb) free. All leads are plated with 100%
matte tin, and there is no Pb inside the package. The heavy gauge
leadframe is made of oxygen-free copper.
SELECTION GUIDE
Package Primary Sampled Sensitivity
Sens (Typ.) Current TOP
Part Number [1] Current, IP Packing [2]
Terminals Signal Pins Directionality (°C)
(A) (mV/A)
ACS770LCB-050B-PFF-T Formed Formed ±50 40. Bidirectional
ACS770LCB-050U-PFF-T Formed Formed 50 80. Unidirectional
ACS770LCB-100B-PFF-T Formed Formed ±100 20. Bidirectional
–40 to 150
ACS770LCB-100B-PSS-T Straight Straight ±100 20 Bidirectional
ACS770LCB-100U-PFF-T Formed Formed 100 40. Unidirectional
ACS770LCB-100U-PSF-T [3] Straight Formed 100 40. Unidirectional
ACS770KCB-150B-PFF-T Formed Formed ±150 13.3 Bidirectional
34 pieces
ACS770KCB-150B-PSF-T Straight Formed ±150 13.3 Bidirectional
per tube
ACS770KCB-150B-PSS-T Straight Straight ±150 13.3 Bidirectional –40 to 125
ACS770KCB-150U-PFF-T Formed Formed 150 26.7 Unidirectional
ACS770KCB-150U-PSF-T Straight Formed 150 26.7 Unidirectional
ACS770ECB-200B-PFF-T Formed Formed ±200 10. Bidirectional
ACS770ECB-200B-PSF-T Straight Formed ±200 10. Bidirectional
–40 to 85
ACS770ECB-200U-PFF-T Formed Formed 200 20. Unidirectional
ACS770ECB-200U-PSF-T Straight Formed 200 20. Unidirectional
[1] Additionalleadform options available for qualified volumes.

[2] Contact Allegro for additional packing options.
[3] ACS770LCB-100U-PSF-T part variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the product is obsolete and no-
tice has been given. Sale of this device is currently restricted to existing customer applications. The device should not be purchased for new design applications because
of obsolescence in the near future. Samples are no longer available. Date of status change: June 5, 2017. Deadline for receipt of LAST TIME BUY orders: December 31,
2017. For existing customer transition, and for new customers or new applications, contact Allegro.
Allegro MicroSystems, LLC 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 6 V
Reverse Supply Voltage VRCC –0.5 V
Forward Output Voltage VIOUT 25 V
Reverse Output Voltage VRIOUT –0.5 V
Output Source Current IOUT(Source) VIOUT to GND 3 mA
Output Sink Current IOUT(Sink) Minimum pull-up resistor of 500 Ω, from VCC to VIOUT 10 mA
Range E –40 to 85 °C
Nominal Operating Ambient Temperature TOP Range K –40 to 125 °C
Range L –40 to 150 °C
Maximum Junction TJ(max) 165 °C
Storage Temperature Tstg –65 to 165 °C
ISOLATION CHARACTERISTICS
Tested ±5 pulses at 2/minute in compliance to IEC 61000-4-5
Dielectric Surge Strength Test Voltage VSURGE 8000 V
1.2 µs (rise) / 50 µs (width)
Agency type-tested for 60 seconds per
Dielectric Strength Test Voltage [1] VISO 4800 VAC
UL standard 60950-1, 2nd Edition
For basic (single) isolation per UL standard 60950-1, 2nd 990 VDC or Vpk
Working Voltage for Basic Isolation VWFSI
Edition 700 Vrms
For reinforced (double) isolation per UL standard 60950-1, 636 VDC or Vpk
Working Voltage for Reinforced Isolation VWFRI
2nd Edition 450 Vrms
[1] 60-second testing is only done during the UL certification process. In production, Allegro conducts 1-second isolation testing according to UL 60950-1, 2nd Edition.
THERMAL CHARACTERISTICS: May require derating at maximum conditions

Characteristic Symbol Test Conditions [2] Value Unit
Mounted on the Allegro evaluation board with 2800 mm2
(1400 mm2 on component side and 1400 mm2 on
opposite side) of 4 oz. copper connected to the primary
Package Thermal Resistance RθJA leadframe and with thermal vias connecting the copper 7 °C/W
layers. Performance is based on current flowing through
the primary leadframe and includes the power consumed
by the PCB.
[2] Additional thermal information available on the Allegro website.
TYPICAL OVERCURRENT CAPABILITIES [3][4]

TA = 25°C, 1 second duration, 1% duty cycle 1200 A
Overcurrent IPOC TA = 85°C, 1 second duration, 1% duty cycle 900 A
TA = 150°C, 1 second duration, 1% duty cycle 600 A
[3] Test was done with Allegro evaluation board. The maximum allowed current is limited by TJ(max) only.
[4] For more overcurrent profiles, please see FAQ on the Allegro website, www.allegromicro.com.

V+ IP+
VCC
To all subcircuits
Programming
Control
Temperature EEPROM and

Sensor Control Logic
C BYP
Sensitivity Control Offset Control
Dynamic Offset
Cancellation
VIOUT
Signal Recovery
CL
IP–
GND
Functional Block Diagram
Terminal List Table

IP+ 4
3 VIOUT Number Name Description
2 GND
1 VCC Device power supply terminal
1 VCC
IP– 5 2 GND Signal ground terminal
3 VIOUT Analog output signal
Pinout Diagram 4 IP+ Terminal for current being sampled
5 IP– Terminal for current being sampled

COMMON OPERATING CHARACTERISTICS: Valid at TOP = –40°C to 150°C, CBYP = 0.1 µF, and VCC = 5 V,
unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Current ICC Output open – 10 15 mA
Supply Zener Voltage VZ TA = 25°C, ICC = 30 mA 6.5 7.5 – V
Power-On Delay [1][2] tPOD TA = 25°C, CBYP = open – 90 – µs
Temperature Compensation
tTC TA = 25°C, CBYP = open – 90 – µs
Power-On Time [1]
Undervoltage Lockout (UVLO) VUVLOH TA = 25°C, VCC rising – 3.8 – V
Threshold [1] VUVLOL TA = 25°C, VCC falling – 3 – V
tUVLOE TA = 25°C, CBYP = open, VCC Fall Time (5 V to 3 V) = 1 μs – 75 – µs
UVLO Enable/Disable Delay
Time [1][2] TA = 25°C, CBYP = Open,
tUVLOD – 14 – µs
VCC Recover Time (3 V to 5 V) = 1 μs
VPORH TA = 25°C, VCC rising – 2.9 – V
Power-On Reset Voltage [1]
VPORL TA = 25°C, VCC falling – 2.7 – V
IP step = 60% of IP+, 10% to 90% rise time, TA = 25°C,
Rise Time [1][2] tr – 4.1 – µs
CL = 0.47 nF
IP step = 60% of IP+, 20% input to 20% output, TA = 25°C,
Propagation Delay Time [1][2] tPROP – 2.4 – µs
CL = 0.47 nF
IP step = 60% of IP+, 80% input to 80% output, TA = 25°C,
Response Time [1][2] tRESPONSE – 4.6 – µs
COUT = 0.47 nF
Internal Bandwidth BWi –3 dB; TA = 25°C, CL = 0.47 nF – 120 – kHz
Output Load Resistance RL VIOUT to GND 4.7 – – kΩ
Output Load Capacitance CL VIOUT to GND – – 10 nF
Primary Conductor Resistance RPRIMARY TA = 25°C – 100 – µΩ
VIOUT(QBI) Bidirectional variant, IP = 0 A, TA = 25°C – VCC/2 – V
Quiescent Output Voltage [1]
VIOUT(QUNI) Unidirectional variant, IP = 0 A, TA = 25°C – 0.5 – V
Ratiometry [1] VRAT VCC = 4.5 to 5.5 V – 100 – %
[1] See Characteristic Definitions section of this datasheet.

[2] See Timing Data Section of this datasheet.

X050B PERFORMANCE CHARACTERISTICS [1]: TOP = –40°C to 150°C, CBYP = 0.1 μF, VCC = 5 V, unless otherwise specified
Primary Sampled Current IP –50 – 50 A
SensTA Measured using full-scale IP , TA = 25°C 39.04 40 40.96 mV/A
Sensitivity [2] Sens(TOP)HT Measured using full-scale IP , TOP = 25°C to 150°C 39.04 40 40.96 mV/A
Sens(TOP)LT Measured using full-scale IP , TOP = –40°C to 25°C 38.6 40 41.4 mV/A
TOP = –40°C to 150°C, shift after AEC-Q100 grade 0
Sensitivity Drift Over Lifetime [3] ΔSensLIFE –0.72 ±0.24 0.72 mV/A
qualification testing
Noise [4] VNOISE TA= 25°C, 10 nF on VIOUT pin to GND – 10 – mV
Nonlinearity ELIN Measured using full-scale and half-scale IP, –1 – 1 %
VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
Electrical Offset Voltage [5][6] VOE(TOP)HT IP = 0 A, TOP = 25°C to 150°C –10 ±6 10 mV
VOE(TOP)LT IP = 0 A, TOP = –40°C to 25°C –20 ±6 20 mV
Electrical Offset Voltage Drift IP = 0 A, TOP = –40°C to 150°C, shift after AEC-Q100 grade 0
∆VOE(LIFE) –5 ±2 5 mV
Over Lifetime [3] qualification testing
Magnetic Offset Error IERROM IP = 0 A, TA = 25°C, after excursion of 50 A – 120 300 mA
ETOT(TA) Measured using full-scale IP , TA = 25°C –2.4 ±0.5 2.4 %
Total Output Error [7] ETOT(HT) Measured using full-scale IP , TOP = 25°C to 150°C –2.4 ±1.5 2.4 %
ETOT(LT) Measured using full-scale IP , TOP = –40°C to 25°C –3.5 ±2 3.5 %
Total Output Error Drift Over TOP = –40°C to 150°C, shift after AEC-Q100 grade 0
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
Lifetime [3] qualification testing
[1] See Characteristic Performance Data page for parameter distributions over temperature range.
[2] This parameter may drift a maximum of ΔSensLIFE over lifetime.
[3] Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits, including Package Hysteresis. Cannot be guaranteed.
Drift is a function of customer application conditions. Contact Allegro MicroSystems for further information.
[4] ±3 sigma noise voltage.
[5] Drift is referred to ideal V
IOUT(QBI) = 2.5 V.
[6] This parameter may drift a maximum of ΔV
OE(LIFE) over lifetime.
[7] This parameter may drift a maximum of ΔE
TOT(LIFE) over lifetime.

X050U PERFORMANCE CHARACTERISTICS [1]: TOP = –40°C to 150°C, CBYP = 0.1 μF, VCC = 5 V, unless otherwise specified
Primary Sampled Current IP 0 – 50 A
Nonlinearity ELIN Measured using full-scale and half-scale IP –1 – 1 %
VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
IOUT(QBI) = 0.5 V.

VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
IOUT(QBI) = 2.5 V.

VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
IOUT(QBI) = 0.5 V.

SensTA Measured using full-scale IP , TA = 25°C 13.01 13.33 13.65 mV/A
Sensitivity [2] Sens(TOP)HT Measured using full-scale IP , TOP = 25°C to 125°C 13.01 13.33 13.65 mV/A
Sens(TOP)LT Measured using full-scale IP , TOP = –40°C to 25°C 12.86 13.33 13.8 mV/A
VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
Symmetry ESYM Over half-scale of IP 99 100 101 %
IOUT(QBI) = 2.5 V.

SensTA Measured using full-scale IP , TA = 25°C 26.02 26.66 27.30 mV/A
Sensitivity [2] Sens(TOP)HT Measured using full-scale IP , TOP = 25°C to 125°C 26.02 26.66 27.30 mV/A
Sens(TOP)LT Measured using full-scale IP , TOP = –40°C to 25°C 25.73 26.66 27.59 mV/A
VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
IOUT(QBI) = 0.5 V.

VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
[3] Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits, including Package Hysteresis. Cannot be guaranteed. Drift
is a function of customer application conditions. Contact Allegro MicroSystems for further information.
IOUT(QBI) = 2.5 V.

VOE(TA) IP = 0 A, TA = 25°C –10 ±4 10 mV
ΔETOT(LIFE) –1.9 ±0.6 1.9 %
IOUT(QBI) = 0.5 V.

CHARACTERISTIC PERFORMANCE DATA

Data Taken using the ACS770LCB-050B
Accuracy Data
Electrical Offset Voltage versus Ambient Temperature Sensitivity versus Ambient Temperature
6 41.0
4 40.8
40.6
Sens (mV/A)
2
40.4
VOE (mV)
0
40.2
-2
40.0
-4 39.8
-6 39.6
-8 39.4
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Nonlinearity versus Ambient Temperature Magnetic Offset Error versus Ambient Temperature
0 250
-0.1
-0.2 200
-0.3
ELIN (%)
IERROM (mA)
150
-0.4
-0.5
100
-0.6
-0.7
50
-0.8
-0.9 0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Total Output Error versus Ambient Temperature

2.5
2.0
1.5
1.0
ETOT (%)
0.5
0
-0.5
-1.0
-1.5
–50 -25 0 25 50 75 100 125 150
TA (°C)
Mean + 3 sigma Mean Mean – 3 sigma


Accuracy Data
8 20.4
6 20.3
4 20.2
Sens (mV/A)
2 20.1
VOE (mV)
0 20.0
-2 19.9
-4 19.8
-6 19.7
-8 19.6
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
0 400
-0.1 350
300
-0.2
250
ELIN (%)
IERROM (mA)
-0.3
200
-0.4
150
-0.5
100
-0.6
50
-0.7 0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

2.5
2.0
1.5
1.0
0.5
ETOT (%)
0
-0.5
-1.0
-1.5
-2.0
–50 -25 0 25 50 75 100 125 150
TA (°C)

Data Taken using the ACS770KCB-150B

Accuracy Data
8 13.60
6 13.55
13.50
Sens (mV/A)
4 13.45
VOE (mV)
2 13.40
13.35
0 13.30
-2 13.25
13.20
-4
13.15
-6 13.10
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
0 450
-0.1 400
-0.2 350
300
-0.3
ELIN (%)
IERROM (mA)
250
-0.4
200
-0.5
150
-0.6
100
-0.7 50
-0.8 0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

2.0
1.5
1.0
0.5
ETOT (%)
0
-0.5
-1.0
-1.5
-2.0
–50 -25 0 25 50 75 100 125 150
TA (°C)

Data Taken using the ACS770ECB-200B

Accuracy Data
6 10.15
4 10.10
Sens (mV/A)
10.05
2
VOE (mV)
10.00
0
9.95
-2
9.90
-4 9.85
-6 9.80
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
0 600
-0.1 500
-0.2 400
ELIN (%)
IERROM (mA)
-0.3 300
-0.4 200
-0.5 100
-0.6 0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

1.5
1.0
0.5
0
ETOT (%)
-0.5
-1.0
-1.5
-2.0
–50 -25 0 25 50 75 100 125 150
TA (°C)


Timing Data
Response Time
IP = 60 A , 10% to 90% rise time = 1 µs, CBYPASS = 0.1 µF, CL = 0.47 nF
IP = 60 A
VIOUT
80% of input
80% of output
tRESPONSE = 4.56 µs
Rise Time
IP = 60 A
VIOUT
90% of output
tr = 4.1 µs
10% of output

Propagation Time
IP = 60 A
VIOUT
tPROP = 2.4 µs
20% of input 20% of output
Power-On Delay
IP = 60 A DC, CBYPASS = Open, CL = 0.47 nF
VCC
VCC (min)
tPOD = 88 µs
90% of output
VIOUT

UVLO Enable Time ( tUVLOE )

IP = 0 A , CBYPASS = Open, CL = Open, VCC 5 V to 3 V fall time = 1 µs
tUVLOE = 75.3 µs
VCC
VUVLOL
VIOUT
VIOUT = 0 V
UVLO Disable Time ( tUVLOD )

IP = 0 A , CBYPASS = Open, CL = Open, VCC 3 V to 5 V recovery time = 1 µs
tUVLOD = 13.9 µs
VCC
VCC (min)
VIOUT
90% of output

CHARACTERISTIC DEFINITIONS
Definitions of Accuracy Characteristics

SENSITIVITY (Sens) Sens(VCC) Sens(5V)
∆Sens(∆V) = × 100 (%)
The change in device output in response to a 1 A change through VCC 5V
the primary conductor. The sensitivity is the product of the mag-
netic circuit sensitivity (G / A) and the linear IC amplifier gain
QUIESCENT OUTPUT VOLTAGE (VIOUT(Q))
(mV/G). The linear IC amplifier gain is programmed at the factory
to optimize the sensitivity (mV/A) for the half-scale current of the The output of the device when the primary current is zero. For
device. bidirectional current flow, it nominally remains at VCC ⁄ 2. Thus,
VCC = 5 V translates into VIOUT(QBI) = 2.5 V. For unidirectional
NOISE (V NOISE) devices, when VCC = 5 V, VIOUT(QUNI) = 0.5 V. Variation in
The noise floor is derived from the thermal and shot noise VIOUT(Q) can be attributed to the resolution of the Allegro linear
observed in Hall elements. Dividing the noise (mV) by the sensi- IC quiescent voltage trim, magnetic hysteresis, and thermal drift.
tivity (mV/A) provides the smallest current that the device is able
ELECTRICAL OFFSET VOLTAGE (VOE)
to resolve.
The deviation of the device output from its ideal quiescent value
NONLINEARITY (E LIN) of VCC ⁄ 2 for bidirectional sensor ICs and 0.5 V for unidirectional
The ACS770 is designed to provide a linear output in response sensor ICs, due to nonmagnetic causes.
to a ramping current. Consider two current levels: I1 and I2. Ide-
MAGNETIC OFFSET ERROR (I ERROM)
ally, the sensitivity of a device is the same for both currents, for
a given supply voltage and temperature. Nonlinearity is present The magnetic offset is due to the residual magnetism (remnant
when there is a difference between the sensitivities measured at field) of the core material. The magnetic offset error is highest
I1 and I2. Nonlinearity is calculated separately for the positive when the magnetic circuit has been saturated, usually when the
(ELINpos ) and negative (ELINneg ) applied currents as follows: device has been subjected to a full-scale or high-current overload
condition. The magnetic offset is largely dependent on the mate-
ELINpos = 100 (%) × {1 – (SensIPOS2 / SensIPOS1 ) } rial used as a flux concentrator.
ELINneg = 100 (%) × {1 – (SensINEG2 / SensINEG1 )} TOTAL OUTPUT ERROR (E TOT)
where: The maximum deviation of the actual output from its ideal value,
also referred to as accuracy, illustrated graphically in the output
SensIx = (VIOUT(Ix) – VIOUT(Q))/ Ix
voltage versus current chart on the following page.
and IPOSx and INEGx are positive and negative currents.
ETOT is divided into four areas:
Then:
• 0 A at 25°C. Accuracy at the zero current flow at 25°C,
ELIN = max( ELINpos , ELINneg ) without the effects of temperature.
• 0 A over Δ temperature. Accuracy at the zero current flow
RATIOMETRY
including temperature effects.
The device features a ratiometric output. This means that the
• Full-scale current at 25°C. Accuracy at the full-scale current at
quiescent voltage output, VIOUTQ, and the magnetic sensitivity,
25°C, without the effects of temperature.
Sens, are proportional to the supply voltage, VCC.The ratiometric
change (%) in the quiescent voltage output is defined as: • Full-scale current over Δ temperature. Accuracy at the full-
scale current flow including temperature effects.
VIOUTQ(VCC) VIOUTQ(5V)
∆VIOUTQ(∆V) = × 100 (%)
VCC 5V VIOUT(IP) – VIOUT_IDEAL(IP)
ETOT(IP) = × 100 (%)
SensIDEAL × IP
and the ratiometric change (%) in sensitivity is defined as: where
VIOUT_IDEAL(IP) = VIOUT(Q) + (SensIDEAL × IP )

Definitions of Dynamic Response Characteristics (%) Applied Magnetic Field
POWER-ON DELAY (tPOD) 90

Transducer Output
When the supply is ramped to its operating voltage, the device
requires a finite time to power its internal components before
responding to an input magnetic field. Rise Time, tr
Power-On Delay, tPOD , is defined as the time it takes for the out- 20
put voltage to settle within ±10% of its steady-state value under 10
an applied magnetic field, after the power supply has reached its 0
Propagation Delay, tPROP t
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
TEMPERATURE COMPENSATION POWER-ON TIME

(tTC )
After Power-On Delay, tPOD , elapses, tTC also is required before a
valid temperature compensated output.
RISE TIME (tr)

The time interval between a) when the device reaches 10% of
its full-scale value, and b) when it reaches 90% of its full-scale
value. Both tr and tRESPONSE are detrimentally affected by eddy
current losses observed in the conductive IC ground plane.
RESPONSE TIME (tRESPONSE)

The time interval between a) when the applied current reaches
80% of its final value, and b) when the sensor reaches 80% of its Output Voltage versus Sampled Current
Total Output Error at 0 A and at Full-Scale Current
output corresponding to the applied current.
PROPAGATION DELAY (tPROP) Accuracy

Increasing VIOUT(V) Over ∆Temp erature
The time interval between a) when the input current reaches 20%
of its final value, and b) when the output reaches 20% of its final Accuracy
25°C Only
value.
Average
VIOUT
POWER-ON RESET VOLTAGE (V POR ) Accuracy

Over ∆Temp erature
At power-up, to initialize to a known state and avoid current

spikes, the ACS770 is held in Reset state. The Reset signal is Accuracy
25°C Only
disabled when VCC reaches VUVLOH and time tPORR has elapsed, IP(min)
allowing output voltage to go from a high-impedance state –IP (A) +IP (A)
into normal operation. During power-down, the Reset signal is Half Scale
IP(max)
enabled when VCC reaches VPORL , causing output voltage to go

into a high-impedance state. (Note that a detailed description 0A
of POR and UVLO operation can be found in the Functional Decreasing VIOUT(V)
Description section.)
Accuracy
25°C Only
Accuracy
Over ∆Temp erature

POWER-ON RESET RELEASE TIME (tPORR) SYMMETRY (ESYM)

When VCC rises to VPORH , the Power-On Reset Counter starts. The degree to which the absolute voltage output from the IC
The ACS770 output voltage will transition from a high-imped- varies in proportion to either a positive or negative half-scale pri-
ance state to normal operation only when the Power-On Reset mary current. The following equation is used to derive symmetry:
Counter has reached tPORR and VCC has exceeded VUVLOH .
UNDERVOLTAGE LOCKOUT THRESHOLD (VUVLO )

100 (VVIOUT_+half-scale amperes
IOUT(Q)
– VIOUT(Q)
– VIOUT_–half-scale amperes )
If VCC drops below VUVLOL , output voltage will be locked to
UVLO ENABLE/DISABLE RELEASE TIME (tUVLO )
GND. If VCC starts rising, the ACS770 will come out of the
locked state when VCC reaches VUVLOH . When a falling VCC reaches VUVLOL , time tUVLOE is required
to engage Undervoltage Lockout state. When VCC rises above
VUVLOH , time tUVLOD is required to disable UVLO and have a
valid output voltage.

FUNCTIONAL DESCRIPTION
Power-On Reset (POR) and Undervoltage

Lock-Out (UVLO) Operation
The descriptions in this section assume: VCC drops below VCC(min) = 4.5 V
If VCC drops below VUVLOL [ 4′, 5 ] , the UVLO Enable Counter
Temperature = 25°C,
starts counting. If VCC is still below VUVLOL when the counter
VCC = 5 V, reaches tUVLOE , the UVLO function will be enabled and the
ouput will be pulled near GND [ 6 ] . If VCC exceeds VUVLOL
no output load, and
before the UVLO Enable Counter reaches tUVLOE [ 5′ ] , the output
no significant current flow through the sensor IC.
will continue to be VCC / 2.
Voltage levels shown are specific to a bidirectional ACS770;
however, the POR and UVLO functionality described also applies Coming Out of UVLO
to unidirectional sensors. While UVLO is enabled [ 6 ] , if VCC exceeds VUVLOH [ 7 ] ,
The reference numbers section refer to figures 1 and 2. UVLO will be disabled after tUVLOD , and the output will be
VCC / 2 [ 8 ] .
Power-Up
Power-Down
At power-up, as VCC ramps up, the output is in a high-impedance
state. When VCC crosses VPORH (location [1] in figure 1 and [ 1′ ] As VCC ramps down below VUVLOL [ 6′, 9 ] , the UVLO Enable
in figure 2), the POR Release counter starts counting for tPORR . Counter will start counting. If VCC is higher than VPORL when
At this point, if VCC exceeds VUVLOH [ 2′ ], the output will go to the counter reaches tUVLOE , the UVLO function will be enabled
VCC / 2 after tUVLOD [ 3′ ] . If VCC does not exceed VUVLOH [2], and the output will be pulled near GND [ 10 ] . The output will
the output will stay in the high-impedance state until VCC reaches enter a high-impedance state as VCC goes below VPORL [ 11 ] . If
VUVLOH [3] and then will go to VCC / 2 after tUVLOD [ 4 ]. VCC falls below VPORL before the UVLO Enable Counter reaches
tUVLOE , the output will transition directly into a high-impedance
state [ 7′ ].
EEPROM Error Checking And Correction

Hamming code methodology is implemented for EEPROM
checking and correction. The device has ECC enabled after
power-up. If an uncorrectable error has occurred, the VOUT pin
will go to high impedance and the device will not respond to
applied magnetic field.

VCC
1 2 3 5 6 7 9 10 11
4 8
5.0
VUVLOH
VUVLOL
VPORH
VPORL
tUVLOE tUVLOE
GND
Time
VOUT Slope =
VCC / 2
2.5
tPORR
tUVLOD tUVLOD
GND
High Impedance High Impedance Time
Figure 1: POR and UVLO Operation: Slow Rise Time Case
VCC
1’ 2’ 4’ 5’ 6’ 7’
3’
5.0
VUVLOH
VUVLOL
VPORH
VPORL < tUVLOE
GND
Time
VOUT
tPORR < tUVLOE
Slope = Slope =
VCC / 2 VCC / 2
2.5
tUVLOD
GND
High Impedance High Impedance Time
Figure 2: POR and UVLO Operation: Fast Rise Time Case

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for sourced signal then can pass through a low-pass filter, while the
switchpoint accuracy is the small signal voltage developed across modulated DC offset is suppressed.
the Hall element. This voltage is disproportionally small relative
In addition to the removal of the thermal and stress related offset,
to the offset that can be produced at the output of the Hall sensor
this novel technique also reduces the amount of thermal noise
IC. This makes it difficult to process the signal while maintaining
in the Hall sensor IC while completely removing the modulated
an accurate, reliable output over the specified operating tempera-
residue resulting from the chopper operation. The chopper sta-
ture and voltage ranges.
bilization technique uses a high-frequency sampling clock. For
Chopper stabilization is a unique approach used to minimize demodulation process, a sample-and-hold technique is used. This
Hall offset on the chip. Allegro employs a technique to remove high-frequency operation allows a greater sampling rate, which
key sources of the output drift induced by thermal and mechani- results in higher accuracy and faster signal-processing capability.
cal stresses. This offset reduction technique is based on a signal This approach desensitizes the chip to the effects of thermal and
modulation-demodulation process. The undesired offset signal is mechanical stresses, and produces devices that have extremely
separated from the magnetic field-induced signal in the frequency stable quiescent Hall output voltages and precise recoverabil-
domain, through modulation. The subsequent demodulation acts ity after temperature cycling. This technique is made possible
as a modulation process for the offset, causing the magnetic field- through the use of a BiCMOS process, which allows the use of
induced signal to recover its original spectrum at baseband, while low-offset, low-noise amplifiers in combination with high-density
the DC offset becomes a high-frequency signal. The magnetic- logic integration and sample-and-hold circuits.
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing Tuned
LP Filter Filter
Figure 3: Concept of Chopper Stabilization Technique

PACKAGE OUTLINE DRAWINGS
For Reference Only – Not for Tooling Use

(Reference DWG-9111 & DWG-9110)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
14.0 ±0.2 0.5

4.0 ±0.2 3.5 ±0.2 R 1.0
R 2.05
3.0 ±0.2 R 3.0
1.50 ±0.10 1º±2°
5 4
Ø 0.5 B
3 4
17.5 ±0.2
21.4
13.00 ±0.10
Branded
Face
4.40 ±0.10
Ø 0.8
1.9 ±0.2 Ø 1.5

2.9 ±0.2
0.51 ±0.10
1 2 3
+0.060 1.91
0.381
–0.030 5º±5°
10.00 ±0.10 B PCB Layout Reference View
3.5 ±0.2
NNNNNNN
7.00 ±0.10 TTT-AAA
LLLLLLL
A Dambar removal intrusion
B Perimeter through-holes recommended YYWW
C Branding scale and appearance at supplier discretion 1

C Standard Branding Reference View
N = Device part number
T = Temperature code
A = Amperage range
L = Lot number
Y = Last two digits of year of
manufacture
W = Week of manufacture
= Supplier emblem
Creepage distance, current terminals to signal pins: 7.25 mm

Clearance distance, current terminals to signal pins: 7.25 mm
Package mass: 4.63 g typical
Figure 4: Package CB, 5-Pin, Leadform PFF


(Reference DWG-9111, DWG-9110)
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
14.0 ±0.2
4.0 ±0.2
3.0 ±0.2
∅ 0.8
5 4 ∅ 1.5
1.50 ±0.10
1.91

A
23.50 ±0.5
NNNNNNN
TTT-AAA
13.00 ±0.10
4.40 ±0.10 Branded LLLLLLL

Face
YYWW
1.9 ±0.2
2.9 ±0.2
0.51 ±0.10 1
1 2 3 C Standard Branding Reference View
+0.060 N = Device part number
0.381
–0.030 5º±5° T = Temperature code
A = Amperage range
3.5 ±0.2 L = Lot number
Y = Last two digits of year of
manufacture
10.00 ±0.10 = Supplier emblem
7.00 ±0.10
B Perimeter through-holes recommended
C Branding scale and appearance at supplier discretion

Figure 5: Package CB, 5-Pin, Leadform PSF


(Reference DWG-9111, DWG-9110)
Dimensions exclusive of mold ﬂash, gate burs, and dambar protrusions
Exact case and lead conﬁguration at supplier discretion within limits shown
14.0 ±0.2
∅ 0.8
4.0 ±0.2
3.0 ±0.2 ∅ 1.5
5 4
1.91
2.75 ±0.10
A NNNNNNN
TTT-AAA
23.50 ±0.5
LLLLLLL
13.00 ±0.10
YYWW
4.40 ±0.10 Branded 1

Face
C Standard Branding Reference View
1 2 3 N = Device part number
3.18 ±0.10 T = Temperature code
11.0 ±0.05 1.9 ±0.2 A = Amperage range
L = Lot number
+0.060
0.51 ±0.10 0.381 Y = Last two digits of year of
–0.030
manufacture
= Supplier emblem
10.00 ±0.10
7.00 ±0.10
B Perimeter through-holes recommended
C Branding scale and appearance at supplier discretion

Figure 6: Package CB, 5-Pin, Leadform PSS

Revision History
Number Date Description
1 December 8, 2014 Revised Selection Guide
2 January 20, 2015 Revised VPORH Typical Value
Revised VRCC, VRIOUT, IOUT(Source), IERROM (100 A and 150 A) values, and added Symmetry to
3 March 11, 2015
X150B PERFORMANCE CHARACTERISTICS table
4 April 8, 2015 Updated TUV certification
5 November 2, 2016 Updated PCB Layout Reference View in Package Outline Drawing on page 27
6 June 5, 2017 Updated status of ACS770LCB-100U-PSF-T part variant to Last-Time Buy
7 November 16, 2017 Added PSS leadform
Added Dielectric Surge Strength Test Voltage characteristic (page 3) and EEPROM Error Checking
8 January 30, 2018
and Correction section (page 24)
9 April 18, 2018 Corrected TUV certification
Copyright ©2011-2018, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com


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ACS770xCB

Thermally Enhanced, Fully Integrated, Hall-Effect-Based

FEATURES AND BENEFITS DESCRIPTION

PFF PSF PSS

Additional leadforms available for qualifying volumes

ACS770-DS, Rev. 9 April 18, 2018

FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

[1] Additionalleadform options available for qualified volumes.

Allegro MicroSystems, LLC 2

THERMAL CHARACTERISTICS: May require derating at maximum conditions

[2] Additional thermal information available on the Allegro website.

TYPICAL OVERCURRENT CAPABILITIES [3][4]

Allegro MicroSystems, LLC 3

Temperature EEPROM and

Functional Block Diagram

Terminal List Table

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[1] See Characteristic Definitions section of this datasheet.

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CHARACTERISTIC PERFORMANCE DATA

Total Output Error versus Ambient Temperature

Mean + 3 sigma Mean Mean – 3 sigma

Allegro MicroSystems, LLC 14

Data Taken using the ACS770LCB-100B

Total Output Error versus Ambient Temperature

Mean + 3 sigma Mean Mean – 3 sigma

Allegro MicroSystems, LLC 15

Data Taken using the ACS770KCB-150B

Total Output Error versus Ambient Temperature

Mean + 3 sigma Mean Mean – 3 sigma

Allegro MicroSystems, LLC 16

Data Taken using the ACS770ECB-200B

Total Output Error versus Ambient Temperature

Mean + 3 sigma Mean Mean – 3 sigma

Allegro MicroSystems, LLC 17

Data Taken using the ACS770LCB-100B

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20% of input 20% of output

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UVLO Enable Time ( tUVLOE )

UVLO Disable Time ( tUVLOD )

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Definitions of Accuracy Characteristics

Allegro MicroSystems, LLC 21

Definitions of Dynamic Response Characteristics (%) Applied Magnetic Field

POWER-ON DELAY (tPOD) 90

TEMPERATURE COMPENSATION POWER-ON TIME

RISE TIME (tr)

RESPONSE TIME (tRESPONSE)

PROPAGATION DELAY (tPROP) Accuracy

POWER-ON RESET VOLTAGE (V POR ) Accuracy