Sherman L.

Sherman L.

San Francisco, California, United States
5K followers 500+ connections

About

Hi guys, I'm one of the co-founders of Raven Protocol along with Rahul, Kailash, and…

Articles by Sherman

Activity

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Experience

  • Raven Protocol Graphic
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    Decentralized

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    San Francisco Bay Area

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    Decentralized

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    San Francisco Bay Area and Hong Kong

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    Hong Kong

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    San Francisco Bay Area

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    Sunnyvale, California, USA

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    Sunnyvale, California, USA

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    Oakland, California, USA

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    Sunnyvale, California, USA

Education

  • University of California, Berkeley Graphic

    University of California, Berkeley

    Activities and Societies: Upsilon Pi Epsilon, Computer Science Undergraduate Association

    Still get nightmares about the Soda Hall computer lab? Yeah, me too ;)

Volunteer Experience

  • Techstars Graphic

    Mentor

    Techstars

    - 2 years 1 month

    Science and Technology

    Advised startups on scaling, growth, marketing, customer development, and fundraising globally.

  • Manos Accelerator via Google Launchpad Graphic

    Mentor

    Manos Accelerator via Google Launchpad

    - 5 months

    Science and Technology

    - Advised startups on customer development, user acquisition, product design and execution.
    - Partnered with Google to accelerate startups in US and international markets.

  • Free Ventures Graphic

    Mentor

    Free Ventures

    - Present 10 years

    Science and Technology

    Mentor to my alma mater’s pre-seed incubator. Exciting to see the next generation of coders coming out Soda Hall every year!

Patents

  • Wireless data communications using FIFO for synchronization memory

    Issued USPTO 07228392

    A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with…

    A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.

    See patent

Projects

  • Crowd Cameo

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    - Event based mobile photo sharing for sports teams and concert venues.
    - While at the event, fans send in mobile photos that are instantly distributed for display on a big screen, a sponsor-able website gallery, and through social networks.
    - Used by sports teams like the Dallas Mavericks, Marquette, LSU, Baylor, etc.

    Other creators
    See project

Honors & Awards

  • 1st Place UC Data Mining Competition

    Fair Isaac and UC San Diego

    - 1st place for Berkeley in both classification and time series analysis competitions
    - Determined whether a customer credit card account was bad and when it turned bad

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