Day 2
Day 2
My Primary Expertise
Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning,
Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising.
Neural Networks : SVM,RBF,BPN
Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman
Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE, Matlab, Open CV
www.pantechsolutions.net https://www.linkedin.com/in/jeevarajan/
Announcement
● Attendance Link at 8.30 pm
● Minimum attendance required for an E-Certificate is 18
Days. Attendance link will be valid for 2 hrs. after the
event.
● For Internship Candidates no attendance required ,it will
be accessed from the LMS Portal.
(learn.pantechsolutions.net)
● Recorded Video Streaming for some classes to improve
Learning Experience
● Only Xilinx FPGA and tools will be covered.
History of VHDL
● 1981- United States Department of defense initiated the requirements
for the Very High speed integrated Circuit (VHSIC) Program
● 1983- IBM and Texas Instruments begin development
● 1984 –Xilinx produces the First FPGA
○ Signal or variable must match exact size of the Variable on the left hand side
● VHDL are concurrent in nature
● VHDL Supports and encourage Hierarchy and partitioning
● Analysis order
entity Half_adder is
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
SUM : OUT STD_LOGIC;
COUT : OUT STD_LOGIC);
end Half_adder;
learn.pantechsolutions.net
● Practice on your own time.
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(Join the 30 Days Challenge )
Thank You
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For learning hub visit learn.pantechsolutions.net