xpc98v1 L

Xilinx
Training Course
Chip Implementation Center

CIC
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1998 V 1
- Outline -
Outline I
Introduction to Programmable Logic Device

CPLD and FPGA Hardware Architectures
Foundation and XACTstep Software
Library Types
Project Manager
Foundation Schematic Design
Basic Design

Manage Large Design
Combinational Logic Design

Lab 1, Lab 2
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- Outline -
Outline II
Synchronous Logic Design
Input / Output Design
Lab 3
Memory Design
Lab 4
Xilinx Abel & Foundation HDL Design

Lab 5
Foundation State Editor

Lab 6, Lab 7
Simulation Basics
Lab 8, Lab 9
Analyzing Simulation Results

CIC
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- Outline -
Outline III
XACTstep M1 Software Flow
M1 Implementation Options
Lab 10
Timing Analyzer
Lab 11
Design Constraints
Lab 12, Lab 13
CIC
EPIC
Configuration
Hardware Debugger and XChecker Cable
Xilinx Conversion
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- Outline -
Advanced Software Design

with XACTstepTM M1
Xilinx Design Flow
FPGA/CPLD Design Flow
Design
Ideas
Detailed
Design
Functional
Simulation
Device
Programming
Timing
Simulation
Synthesis
Synthesis&&
Implementation
Implementation
FPGA
CIC
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tpd=22.1ns
fmax=47.1MHz
- swflow -
M
M11
Design Flow
Xilinx Unified Libraries
VHDL/VERILOG Models
Functional Simulation
HDL Source File

(VHDL or
Verilog HDL)
Synthesis
LogiBlox
Synthesis
Library
Synopsys
FPGA Compiler or
Design Compiler
Synopsys
VHDL System Simulator
or
3rd Party
VHDL/VERILOG Simulator
Simulation
Library
LogiCores
Optional
Netlist
(XNF or *EDIF)
Post-layout Verification
Static Timing
Verification
Constraints
File
Netlist Launcher
Static Timing Report

Synopsys
VSS Simulator
NGDBUILD
Place & Route
Implementation Tools
VHDL,
VERILOG,
*SDF
PAR (Place & Route)
Device Programming Files

*Standard
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Interface Netlist Format

Delay Format
** Standard
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Timing Simulation
Synopsys
VSS Simulator
or
3rd Party
VHDL/VERILOG Simulator
Design Entry
HDL design files
Must learn synthesizable RTL Verilog/VHDL coding
style for Synopsys
Tool: text editor
xedit, textedit, vi, joe, ...
module converter(i3,i2,i1,i0,a,b,c,d,e,f,g);
input i3, i2, i1, i0 ;
output a, b, c, d, e, f, g;
reg a,b,c,d,e,f,g;
always @(i3 or i2 or i1 or i0) begin
case({i3,i2,i1,i0})
4'b0000: {a,b,c,d,e,f,g}=7'b1111110;
4'b0001: {a,b,c,d,e,f,g}=7'b1100000;
4'b0010: {a,b,c,d,e,f,g}=7'b1011011;
4'b0011: {a,b,c,d,e,f,g}=7'b1110011;
4'b0100: {a,b,c,d,e,f,g}=7'b1100101;
4'b0101: {a,b,c,d,e,f,g}=7'b0110111;
4'b0110: {a,b,c,d,e,f,g}=7'b0111111;
4'b0111: {a,b,c,d,e,f,g}=7'b1100010;
4'b1000: {a,b,c,d,e,f,g}=7'b1111111;
4'b1001: {a,b,c,d,e,f,g}=7'b1110111;
4'b1010: {a,b,c,d,e,f,g}=7'b1101111;
4'b1011: {a,b,c,d,e,f,g}=7'b0111101;
4'b1100: {a,b,c,d,e,f,g}=7'b0011110;
4'b1101: {a,b,c,d,e,f,g}=7'b1111001;
4'b1110: {a,b,c,d,e,f,g}=7'b0011111;
4'b1111: {a,b,c,d,e,f,g}=7'b0001111;
endcase
end
endmodule
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HDL simulation
Tool: Verilog simulator
Cadence Verilog-XL
Viewlogic VCS
Tool: VHDL simulator
Synopsys
VSS
Viewlogic
Speedwave
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Logic Synthesis
RTL Verilog/VHDL -> XNF (Xilinx Netlist Format)
Tool: Synopsys software
Design Analyzer
HDL Compiler
VHDL Compiler
FPGA Compiler
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Xilinx Implementation
EDIF, XNF -> configuration bitstream & timing
netlist
Tool: Xilinx XACTstep softwar (Unix or PC version)

Xilinx Design Manager (dsgnmgr)
xgen
EPIC
CIC
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Timing Analysis
Critical path & clock rate analysis
Tool: Xilinx XACTstep Timing Analyzer
CIC
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Timing Simulation
Generate the Verilog file with timing
Tool: ngd2ver utility
Verilog simulation
Tool: Verilog simulator
Generate the VHDL file with timing

Tool: ngd2vhdl
VHDL simulation
Tool: Synopsys VSS
CIC
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Device Programming
Use configuration bitstream files to program
Xilinx devices
Tool: Xilinx Hardware Debugger

Programming hardware:
Xilinx XChecker download cable (RS-232 port)
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Design Tools
Verilog simulator
Verilog-XL or VCS
Verilog simulation model for Xilinx primitives &
macrofunctions
VHDL simulator
VSS or Speedwave
VHDL simulation model for Xilinx primitives &
macrofunctions
Verilog/VHDL synthesis
Synopsys
Xilinx-Synopsys interface (XSI)
Synthesis libraries
DesignWare libraries
Interface programs
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Design Tools
Implementation
Xilinx XACTstep
Timing Verilog netlister

ngd2ver
Timing VHDL netlister

ngd2vhdl
Our focus:
Synopsys FPGA Compiler
Xilinx XACTstep
Knowledge of Verilog-HDL design & simulation is assumed.
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Synopsys Tools We May Use

Design Analyzer
User graphical interface of Synopsys synthesis tool
HDL Compiler
Translate Verilog descriptions into Design
Compiler/FPGA Compiler
VHDL Compiler
Translate VHDL descriptions into Design
Compiler/FPGA Compiler
Design Compiler
Constraint-driven logic optimizer
FPGA Compiler
Design Compiler Family synthesis tool that targets
FPGA technologies
Optimization for LUT architectures
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Xilinx-Synopsys Synthesis Flow
Verilog/VHDL Design Design Constraints

.sdb
(V)HDL
Compiler
Xilinx Symbol Libraries

FPGA
Compiler
.db
.sldb
Design Analyzer
Xilinx Synthesis &

Technology Libraries
Optimized Netlist
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Synthesis Reports
Xilinx XACTstep Software

XACTstep features
Core implementation for all Xilinx FPGA/CPLD device families

DRC, logic optimization, mapping, timing-driven P&R
EPIC
Timing analysis
Programming file generation & device programming
LogiBLOX module generator & optimize
On-line help
Interface to third-party tools

Interface : libraries, interface programs & netlisters (not the
tool itself)
Timing Verilog/VHDL netlist file generation for timing
simulation
Installation CD-ROM contains Synopsys, Cadence, Mentor &
Viewlogic interfaces
XSI: Xilinx-Synopsys Interface
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XACTstep 5.2 / 6.0 and M1.3

Differences
XACTstep V5.2 & v6.0
XACTstep M1.3
OS
SunOS, HP Unix, Solaris*

DOS, Win 3.1, Win'95*
SunOS, HP Unix, Solaris

Win NT, Win95
GUI
Command line only on WS

Push GUI button on PC only
Command line scripts still

available
GUI identical to Windows
XACTv6.0
Netlists
Xilinx Netlist Format (XNF)
EDIF 2.0.0 is Default, XNF

accepted
Binaries
16 bit code
32 bit code (no DOS windows!)
PAR from NeoCAD

PPR
- best case ~85% CLB utilization - Typical 95% utilization on
4000X
- 100% utilization possible
- Faster compile times esp. for
4000X
XC2000, XC3x00/A,
XC3x00A***, XC5000***,
Family support
XC4000/L/A/E, XC5000, XC7300, XC4000L/E/EX/XL
XC9500**
XC7300, XC9500
Place&Route
* v5.2/6.0 tools ran on these operating systems but were not 100% tested
**XC9500 operation required modification of path variable. M1.3 integrates XC9500.
*** XC3x00A and XC5000 will be supported by M1 in the M1.4 release.
Note XC4000A is not supported by M1.
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Xilinx Customer Support

Xilinx & distributor Field Application Engineers
North American factory technical support
hotline
(800) 255-7778 (outside 408) or (408) 879-5199

e-mail: [email protected]
On-line help and documentation

Includes databook and application notes
Internet site
Home page http://www.xilinx.com
XUP http://www.xilinx.com/programs/univ.htm
SmartSearch http://www.xilinx.com/search.htm
Technical seminars
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CIC Supports
Xilinx software
PC :
WS :
XACTstep (FPGA, CPLD)

Foundation interface (Schematic, ABEL, VHDL,
Simulation)
FPGA Express
XACTstep (FPGA, CPLD)
Aliance interface (Synopsys)
Xilinx hardware
FPGA demo board, XChecker download cable
Technical support
WWW http://cic01.cic.edu.tw/software/Xilinx
[email protected]
TEL:03-5773693 ext 146
[email protected]
TEL:03-5773693 ext 148
<|
o
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Basic PLD Architecture
CPLD and FPGA

Hardware Architectures
XC9500
CPLDs
In-System
Programming Controller
JTAG
Controller
JTAG Port
programmable (ISP)
CPLDs
Function
Block 1
I/O
I/O
I/O
Global
Clocks
Global
Set/Reset
Global
TriStates
CIC
Function
Block 2
I/O
Blocks
I/O
FastCONNECT
Switch Matrix
Function
Block 3
5 ns pin-to-pin
36 to 288
macrocells
(6400 gates)
Industrys best pinlocking architecture
10,000
program/erase
cycles
1
Function
Block 4
Complete IEEE
1149.1 JTAG
capability
2 or 4
fe
5 volt in-system
- ARCH -
XC9500 - Architectural Features

Uniform, all pins fast, PAL-like architecture
FastCONNECT switch matrix provides 100%
routing with 100% utilization
Flexible function block
36 inputs with 18 outputs

Expandable to 90 product terms per macrocell
Product term and global three-state enables
Product term and global clocks
Product term and global set/reset signals
3.3V/5V I/O operation

Complete IEEE 1149.1 JTAG interface
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Complete Interconnectivity
with FastCONNECT
Global
3-State
Global
S/R
Function
Block
Function
Block
Function
Block
FastCONNECT
Function
Block
Function
Block
Function
Block
fe
Function
Block
Global
Clocks
JTAG
CIC
Function
Block
- ARCH -
XC9500 Function Block

Global
Clocks
AND
Array
Global
Tri-State
2 or 4
Macrocell 1
I/O
Macrocell 18
I/O
ProductTerm
Allocator
36
From
FastCONNECT
To
FastCONNECT
Each function block is like a 36V18 !
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- ARCH -
XC9500 Macrocell
to/from other macrocells
From
FastCONNECT
SUM-Term
Logic
36
P-Term
Allocator
XOR
D/T
to/from other macrocells
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- ARCH -
R S
P-term Clk
P-term R&S
P-term OE
CIC
Register
Global
Clocks
2 or 4
Global Global
R/S
OEs
18
XC9500 Product Family

9536
9572
95108
95144
95216
95288
Macrocells
36
72
108
144
216
288
Usable
Gates
800
1600
2400
3200
4800
6400
tPD (ns)
7.5
7.5
7.5
10
10
Registers
36
72
108
144
216
288
Max I/O
34
72
108
133
166
192
PC84
TQ100
PQ100
PQ160
PQ100
PQ160
Packages
CIC
VQ44
PC44
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PC44
PC84
TQ100
PQ100
- ARCH -
PQ160
HQ208
BG352
HQ208
BG352
Xilinx FPGA Families

HIGH SPEED
ASIC-like
ASIC-like
Architectures
Architectures
(FPGAs)
(FPGAs)
XC3100A
5V ISP
Family
HIGH DENSITY
SRAM
XC7300
OTP
XC3000A
XC4000E,EX,XL
Performance
Optimized SRAM
XC4000
XC5200
Cost/Performance
Optimized
SRAM
fe
0
620 GA
C
X
FP
M
RA
New Markets
PAL-like
PAL-like
Architectures
Architectures
(CPLDs)
(CPLDs)
CIC
HIGH DENSITY
5ns
LOW COST
- ARCH -
Xilinx FPGA Family Comparison

Family
XC3100A
Key Feature
Speed
XC4000E/EX/XL
XC5200
Speed
Low Cost
Density
Density
RAM
Speed
to 95 MHz
to 66 MHz
to 50 MHz
Density
1K-7.5K gates
3K-62K gates
2K-23K gates
I/O
64-176
80-384
84-244
Flip-flops
256-1320
360-5376
256-1936
Features
2 global clocks
4-8 global clocks
4 global clocks
Internal buses
(same)
(same)
Edge decode
Cascade
Carry
Carry
Scan
Scan
RAM
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XC4000 Architecture
CLB
Slew
Rate
Control
CLB
S witch
Matrix
CLB
Input
Buffer
Programmable
Interconnect
C1 C2 C3 C4
S/R
Control
F4
F3
F2
F1
DIN
H'
H
Func.
Gen.
F
Func.
Gen.
SD
F'
G'
EC
RD
G'
H'
S/R
Control
DIN
SD
F'
G'
H'
EC
1
H'
F'
RD
Configurable
Logic Blocks (CLBs)
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Delay
I/O Blocks (IOBs)
H1 DIN S/R EC
G
Func.
Gen.
Vcc
Output
Buffer
CLB
Q
G4
G3
G2
G1
Passive
Pull-Up,
Pull-Down
- ARCH -
Pad
Configurable Logic Block (CLB)

Combinatorial logic via lookup table
Any function(s) of available inputs
Output registered and/or combinatorial

Latches in XC5000
Inputs
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Combinatorial
Logic
Function(s)
- ARCH -
FlipFlops
Outputs
Look Up Tables
Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB
Look Up Table
4-bit address
Example:
Combinatorial Logic
A B C D
A
B
Z
C
D
Capacity is limited by number

of inputs, not complexity
Choose to use each function
generator as 4 input logic (LUT)
or as high speed sync. dual
port RAM
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0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
0
0
0
1
1
1
. . .
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
WE
G4
G3
G2
G1
G
Func.
Gen.
XC4000 Configurable Logic

Blocks
2 Four-input
C1 C2 C3 C4
function
generators (Look
Up Tables)
16x1 RAM or
Logic function
2 Registers
Each can be
configured as
Flip Flop or
Latch
Independent
clock polarity
Synchronous
and
asynchronous
Set/Reset
CIC
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H1 DIN S/R EC
S/R
Control
G4
G3
G2
G1
F4
F3
F2
F1
- ARCH -
DIN
G
Func.
Gen.
SD
F'
G'
YQ
H'
EC
RD
H
Func
.Gen.
F
Func.
Gen.
1
G'
H'
Y
S/R
Control
DIN
SD
F'
G'
XQ
H'
EC
RD
1
H'
F'
XC4000 Function Generators

Two 4-input function generators
Independent inputs (any two functions of four inputs)
One 3-input function generator

Combines four-input functions to make any five-input
function and some functions of up to nine inputs
Using write enable input turns look-up tables

into RAM
F
H
G
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I/O Block (IOB)

Periphery of identical I/O blocks
Input, output, or bidirectional

Registered, latched, or combinatorial (XC3000/XC4000)
Three-state output
Programmable output slew rate
I
O
TS
Clocks
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IOB
Pad
Bonded to
Package Pin
XC4000E I/O Block Diagram

Slew
Rate
Control
Passive
Pull-Up,
Pull-Down
Vcc
T/OE
O
Output
Buffer
OK (Output
Clock)
I1
Input
Buffer
I2
CE
IK (Input
Clock)
Delay
Elements in BLUE are not in the XC3000 family.
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Pad
XC4000EX IOB
Slew Rate
Control
Passive
Pull-Up/
Pull-Down
T
Output Mux
Flip-Flop
D
Out
Output
Buffer
CE
Output
Clock
Pad
Input
Buffer
I1
I2
Clock
Enable
Flip-Flop/
Latch
Q
CE
Input
Clock
CIC
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Delay
Fast
Capture
Latch
Delay
Q D
Latch
G
X6550
- ARCH -
Xilinx FPGA Routing

Fast Direct Interconnect - CLB to CLB
General Purpose Interconnect - Uses switch
matrix
Long Lines
CLB
Segmented across
chip
Global clocks, lowest
skew
2 Tri-states per CLB
for busses
Other routing types

in CPLDs and
XC6200
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Switch
Matrix
CLB
Switch
Matrix
CLB
CLB
XC4000EX Interconnect
Hierarchy
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CIC
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XC4000EX VersaRingTM
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Other FPGA Resources

Tri-state buffers for busses (BUFTs)
Global clock & high speed buffers
(BUFGs)
Wide Decoders (DECODEx)

Internal Oscillator (OSC4)
Global Reset to all Flip-Flops,
Latches (STARTUP)
CLB special resources

Fast Carry logic built into CLBs
Synchronous Dual Port RAM
Boundary Scan
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Whats Really In that Chip?

Programmable Interconnect Points, PIPs (White)
Switch
Matrix
Routed Wires (Blue)
Direct
Interconnect
(Green)
CLB
(Red)
Long Lines
(Purple)
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The XC4000 Series

Sampling
NOW
Available
NOW
XC4000E
Speed
3-25K Gates
60 MHz
XC4000EX
28-125K Gates
66 MHz
Conversion
During
1996
The XC4000 Series
XC4000
3-25K Gates
40 MHz
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Density
- ARCH -
XC4000E
CIC
High Performance High Density FPGA

50% Faster
100% PCI Compliant
3,000 - 25,000 Gates
Backwards Compatible to XC4000
Advanced 0.5m TLM CMOS Process
Architecture Improvements
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- ARCH -
XC4000E Architectural
Enhancements
Select-RAM
TM
Memory
Synchronous and asynchronous

Single port and dual port Select RAM memory
More Routing Resources

2 additional H function generator inputs
Additional routing connections
I/O Block Clock Enable for Improved Bus

Interface
Programmable I/O Levels

Easy design-in for TTL and CMOS chip-wide level
Soft Wake-up for Predictable Start-up Current

Outputs slowly awaken
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XC4000E New Select-RAM

Memory
Old
Data
New
XC4000
RAM
Data
Address
Address
WE
WE
XC4000E
RAM
Data 2
Address 2
Optional
Dual Port
Clock
Asynchronous
Asynchronous Single
SinglePort
Port
Synchronous
Synchronous
Timing
Timing
Critical
Critical
Simple
SimpleTiming
Timing Programmable
Programmableduring
during
device
operation
device operationororatat
start-up
start-upconfiguration
configuration
Simple
SimpletotoUse
Use 33nsnsread
readtime
time
Longer
Longer
Design
DesignTimes
Times
CIC
Programmable
Programmableonly
only
during
device
during device
operation
operation
44ns
nsread
readtime
time
fe
- ARCH -
Dual
DualPort
Port
XC4000EX
The XC4000EX Contains XC4000E Features:
Synchronous, single and dual-port Select RAM memory
Dedicated JTAG boundary scan logic
High speed carry logic
Wide Edge decoders
In Addition to:
Twice the routing resources
New high speed quad interconnect resources
High speed 3 level clocking network
VersaRing I/O added for pin assignment flexibility
Improved carry logic for faster adders, multipliers and
DSP functions
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XC4000EX Solves High-Density

Design Issues I
Easy to Route High Density Designs
Twice the routing resources as XC4000E
Innovative Buffering Allows High-Speed

Heavily Loaded Nets
Longer routes needed as designs grow

New, high performance quad lines
Low skew/Fast Chip-to-Chip Communication

High-speed, three level, clocking network
Pin Assignment Flexibility

Allowing frequent design iterations
VersaRing I/O interface
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XC4000EX Solves High-Density

Design Issues II
Higher Performance Arithmetic Functions
through Improved Carry Logic
Improved I/O Blocks Provided Faster and More

Flexible Chip-to-Chip Communication
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XC4000E Fastest 5 V FPGA

Family
4003E 4005E 4006E 4008E 4010E 4013E 4020E 4025E
Logic Cells
238
466
608
770
950
1,368
1,862
2,432
Max Logic Gates
3K
5K
6K
8K
10K
13K
20K
25K
Typ Gate Range* 2-5K
3-9K
4-12K 6-15K 7-20K 10-30K 13-40K 15-45K
(Logic + Select-RAM)
Max I/O
Packages:
100%
Footprint
Compatible
80
112
128
PC84 PC84 PC84

TQ100
PQ100 PQ100
144
160
PC84
PC84
192
224
256
TQ144 TQ144
PQ160 PQ160 PQ160 PQ160
PQ208 PQ208 PQ208 PQ208 PQ208 HQ208
HQ240 HQ240 HQ240
HQ304
PG120 PG156 PG156 PG191 PG191 PG223 PG223 PG223
fe
* 20-25% of CLBs as RAM
CIC
BG225BG225
- ARCH -
PG299
XC4000EX Family
4028EX** 4036EX** 4044EX** 4052XL 4062XL 4085XL 40125XL
Typ Logic Gates
28,000
36,000
44,000
52,000
62,000
85,000
125,000
Typ System Gates*
56,000
72,000
90,000
110,000
130,000
175,000
250,000
Avail RAM bits
32,768
41,472
51,200
61,952
73,728
100,352
157,968
Number CLBs
1,024
1,296
1,600
1,936
2,304
3,136
4,624
Flip-Flops
2,560
3,168
3,840
4,576
5,376
7,168
10,336
I/O
256
288
320
352
384
448
544
Supply Voltage
5/3
5/3
5/3
Packages:
HQ208
HQ208
HQ208
HQ208
HQ208
HQ240
HQ240
HQ240
HQ240
HQ240
HQ304
HQ304
BG352
BG352
BG352
BG352
BG352
BG432
BG432
BG432
BG560
BG560
BG560
BG560
PG411
PG411
PG475
PG475
(Logic + Select-RAM)
100% Footprint
Compatible
PG299
PG411
* 30% of CLBs as RAM
CIC
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**The 28, 36, and 44 will be available

in 5 volt (EX) and 3 Volt (XL) versions
- ARCH -
XC5000 CLB (1 of 4 Logic Cells)

CO
LC3
LC2
LC1
DO
(.LC0)
DI
F4
F3
F2
F1
D Q
CE
CLR
CIC
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CI
- ARCH -
CE CK CLR
XC5000 Function Generators

Four four-input functions
Two five-input functions
5-input AND uses only one lookup table
Cascaded sixteen-input function
CIC
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- ARCH -
XC5000 I/O Block Diagram
Slew
Rate
Control
Passive
Pull-Up,
Pull-Down
Vcc
T/OE
O
Output
Buffer
I
Delay
Input
Buffer
CIC
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- ARCH -
Pad
XC5000 Family
CIC
Part
Gates CLB Matrix CLBs Flip-Flops IOBs
5202
3000
8x8
64
256
84
5204
6000
10x12
120
480
124
5206
10000
14x14
196
784
148
5210
16000
18x18
324
1296
196
5215
23000
22x22
484
1936
244
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- ARCH -
XC3000 Configurable Logic

Block (CLB)
1 configurable
function generator
CLB inputs
5 generalpurpose (A-E)
Internal
feedback
from flip-flops
2 CLB outputs
CIC
F, G, or
registered
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- ARCH -
XC3000 Configurable Function

Generator
7 shared sources
5 general-purpose inputs (A-E)
2 storage element feedbacks (QX, QY)
Lookup table configurations

Any function of 5 inputs
2 functions of 4 inputs
M
U
X
CIC
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F
F
- ARCH -
M
U
X
XC3000 I/O Block Diagram
Slew
Rate
Control
Passive
Pull-Up
Vcc
T/OE
O
Q
Output
Buffer
OK (Output
Clock)
I
Q
IK (Input
Clock)
CIC
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- ARCH -
Input
Buffer
TTL or
CMOS
Pad
XC3000 Family
Part
Typical Gates CLB Matrix
CLBs
Flip-Flops
3120A
1300-1800
3130A
8x8
64
256
64
2000-2700
10x10
100
360
80
3142A
2500-3700
12x12
144
480
96
3164A
4000-5500
14x16
224
688
120
3190A
5000-7000
16x20
320
928
144
3195A
6500-8500
22x22
484
1320
176
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- ARCH -
IOBs
XC6200 Architecture
16x16 Tile
4x4 Block
User I/Os
Address
Data
Control
y y
y
y
y y
User I/Os
*Number of tiles varies between devices in family
CIC
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- ARCH -
User I/Os
FastMAPtm
Interface
User I/Os
Function Cell
HardWireTM
Unique no-risk 100% compatible mask-programmed cost
reduction of Xilinx FPGA
Cost-effective for volume applications
Savings of 40% to 70%
Architecture-equivalent mask-programmed version of any

FPGA
Requires virtually no customer engineering resources, test vectors, or

simulation
ALL FPGA features (e.g., Configuration, Power-On Reset, JTAG,
etc.) are fully supported
HARDWIRE
FPGA
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- ARCH -
CPLD or FPGA?
CPLD
FPGA
SRAM reconfiguration
Excellent for computer
Non-volatile
JTAG Testing
architecture, DSP,
registered designs
Wide fan-in
Fast counters, state
machines
Combinational Logic
Small student projects,
lower level courses
ASIC like design flow

Great for first year to
graduate work
More common in schools

PROM required for nonvolatile operation
CIC
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- ARCH -
Family Selection Guidelines I
XC4000
Feature
EX
XL
Shortest Pin-To-Pin
Fastest State Machine
Fastest Arithmetic Counters
Bi-directional Busses
DSP (Multiply/Accumulate)
RAM
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- ARCH -
5200
6200
9500
X
X
X
Family Selection Guidelines I

XC4000
Feature
EX
XL
5200
Tolerant of pin-locking
Footprint Compatible Families
In-System Programmable
Boundary Scan
Fast/Partial Configuration
6200
X
X
Non-Volatile/single chip (no PROM)

Low Standby Current
CIC
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X
X
- ARCH -
9500
Family Selection Guidelines III
XC4000
Feature
TTL & CMOS 5v Output
EX
XL
5200
6200
9500
T, C
T, C
T, C
T, C
T, C
3.3 V Operation
5v Output Drives 3.3 V

Hi-Rel, Mil, Mil-Temp
CIC
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Opt.
X
- ARCH -
Opt.
Basic PLD Architecture
Foundation and
TM
XACTstep Software
XACTstepTM M1 Software
ALLIANCE Series
Software Backplane
)RXQGDWLRQ Series
Libraries and Interfaces

for Leading EDA
Vendors
Core Implementation
Software - Map, Place,
Route, Bitstream
generation, and
analysis
Complete, Ready-to-Use
Includes Schematic,
Simulation, and
ABEL/VHDL Synthesis
Graphical User Interface is very similar to XACTStep v.6.0

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- Soft -
Design Tools
Standard CAE entry and verification tools
XACT software implements the design
The design is optimized for best performance and
minimal size
Graphical User Interface and Command Line Interface
Easy access to other Xilinx programs
Manages and tracks design revisions
Design
Entry
Foundation
or Alliance
Back Annotation
Simulation
Schematic,
HDL Code
XACT
Xilinx
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Design Implementation
- Soft -
Design
Verification
Static Timing Analysis,

In-Circuit Testing
Multi-Source Integration
Mixed-Level Flows
+'/
6FKHPDWLF
([LVWLQJ
'HVLJQV
and multiple EDA vendors

in the same flow
&RUHV
Allows team development

Reduces design source
EDIF
VHDL
Verilog
SDF
Knowledge
Driven
Implementation
Check Point
Verification
Design Source
Integration
Standards
Based
Enables multiple sources
translations
Design the way you are

used to
Enables rapid, accurate

iterations
Works well within existing

ASIC flows
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- Soft -
Facilitates Design Reuse
3rd Party Support & Libraries

Xilinx 3rd Party Design Entry & Simulation
Support
Synopsys, Cadence, Mentor Graphics, Aldec, Viewlogic

OrCad, Synplicity, Model Technologies, Synario, Exemplar,
ABEL and others supply libs & interfaces
Industry standard file formats:
VHDL, Verilog, and EDIF netlist formats
SDF Standard Delay files
VITAL library support
Xilinx Libraries
Optimized components for use in any Xilinx FPGA or CPLD
Wide range of functions
Comparators, Arithmetic functions, memory
DSP and PCI interfaces
Easy to use with ABEL, VHDL, Verilog, schematic entry
CIC
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- Soft -
Libraries, Macros & Attributes

Libraries are common design sets for all design entry tools
(eg. text, schematic, Foundation, Synopsys, Viewlogic, etc.)
Unified Libraries:
Boolean functions, TTL,
Flip-Flops, Adders,
RAM, small functions
LogiBlox Libraries:
Variable size blocks of
adders, registers, RAM,
ROM, etc.
Properties defined as
attributes
Library interfaces are specific to each front end
Attributes are library element properties
Online Libraries Guide has full listings and descriptions
CIC
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- Soft -
Foundation Overall Design Flow

CHECKPOINT VERIFICATION
DESIGN ENTRY
Schematic
HDL
(X-VHDL/X-ABEL)
Finite State
Machine Diagram
User-Created Stimulus
LogiBLOX
Gate-Level
Functional
Simulation
Netlist Merging
Mapping to Target
Architecture
Post-MapStatic Timing
Analysis
IMPLEMENTATION
Multi-Pass
PAR
Knowledge-Driven
Place and Route
Logic Block Delays Only

Post-Place and Route
Static Timing Analysis
User-Created Stimulus
Creation of Device
Programming Data
Interactive
Hardware
Debuggung (Optional)
PROM File
Formatting
CIC
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- Soft -
PostPlace and Route

Gate-Level
Timing Simulation
Foundation Interface Flow

LogiBLOX
GUI
HDL Editor
Finite State
Machine Editor
VHD
ABL
X-VHDL
Compiler
X-ABEL
Compiler
Symbol
Descriptor
Viewlogic
Import Utility
Schematic
Capture
EDN
EDN
Simulation
Only
EDN
Design Netlist
and Constraints
EDN UCF PCF
User-Created
Simulation
Stimulus
CIC
Gate-Level Simulation
fe
- Soft -
Netlist Merging/Mapping
SXNF
SXNF
XNF
XNF
EDIF
EDIF
UCF
UCF
NGDBUILD
NCF
NCF
NGD
NGD
M1
Design Flow
MAP
NCD
NCD
PCF
PCF
TRCE
TRCE
PAR
BITGEN
NCD
NCD
BIT
BIT
CIC
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- Soft -
Foundation Overview
Integrated Aldec front end and Xilinx implmentation
tools
Aldec Project Manager can invoke Xilinx Design Manager

and other tools
Optional VHDL synthesizer

All Windows-based
Aldec tools:
Schematic capture
Gate-level simulation
VHDL/ABEL Language Assistant
Includes Viewlogic schematic import feature

Includes on-line documentation and tutorials
Synopsys FPGA Express (VHDL, Verilog)
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- Soft -
Foundation Project Manager

Offers access to Aldec or Xilinx tools
M1 Foundation Graphical User Interface very similar to v.6.0.x
CIC
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- Soft -
Schematic Entry
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- Soft -
ABEL and VHDL Text Entry

From schematic
menu (or via HDL
Editor), select
Hierarchy -> New
Symbol Wizard to
create symbol.
Select HDL Editor &
Language Assistant
to learn by example,
then define block.
Synthesize to EDIF.
CIC
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- Soft -
State Machine Graphical Editor
Graphical editor synthesizes into ABEL or VHDL code

CIC
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- Soft -
Foundation Simulator
CIC
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- Soft -
Implementation - M1 Design
Manager
Manages
design data
Access
reports
Supports
CPLDs,
FPGAs
Flow Engine
Timing Analyzer
PROM File Formatter

Hardware Debugger
EPIC Design Editor
CIC
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- Soft -
Toolbox Programs
Flow Engine
Controls start/stop points
and custom options
Timing Analyzer
Report on net and path
delays
PROM File Formatter

Create file to program
configuration file into PROM
Hardware Debugger
Download configuration file
EPIC Design Editor

Device-level view of routing
CIC
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- Soft -
Flow Engine
View
status of
tools
Control
tool
options
Implement
design to
the
bitstream
CIC
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- Soft -

with XACTstepTM M1
Library Types
Xilinx Libraries Overview

Libraries contain descriptions of each
component with pin names, functionality,

timing, etc.
There are two libraries:

The Unified Library contains ready made components
with non-variable function and size
The LogiBLOX Library contains templates which can be
customized for function and size
Both libraries alow easy design migration

across Xilinx devices and families
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- Lib -
LogiBLOX templates and GUI

LogiBLOX is composed of two parts:
LogiBLOX Library containing templates of
VARIABLE SIZE
Templates are expanded or customized (Counters,
Adders, Registers, RAM, ROM)
Templates have many implementations (e.g.
Binary, Johnson, LFSR counters)
LogiBLOX GUI and Synthesizer to create
A design file for implementation
Symbol for schematic capture tool
HDL code for instantiation in your design
Functional simulation model
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- Lib -
Generic LogiBLOX Functions

One generic model per function type(ex:
counter) - Attributes can be specified
ex: bus width, load, clock enable, etc.
Arithmetic:
COUNTER, ADDER, SUBTRACTOR,
ACCUMULATOR, COMPARATOR
Storage:
SHIFT, DATA_REG, ROM, RAM, SYNC_RAM,
DP_RAM
Logic:
ANDBUS, ORBUS, MUXBUS, DECODE, TRISTATE,
MULITIPLEXER, SIMPLE GATES
I/O:
INPUTS, OUTPUTS, BIDIR_IO
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- Lib -
Example: LogiBLOX Counter

Template
The Counter template has a number of
options:
Example of COUNTER styles:

Binary, Johnson, LFSR, One-HOT
Up, down, or bi-directional
Fixed pre-load and/or parallel load
Asynchronous or Synchronous starting value
Clock enable
Counter range
COUNTER
D_IN
Q_OUT
LOAD
UP_DN
ASYNC_CTRL
SYNC_CTRL
CLK_EN
TERM_CNT
CLOCK
CIC
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- Lib -
Using LogiBLOX in Schematics

Invoke the Module Selector from within your design
entry tool
Configure your project directory using the LogiBLOX

Setup window
Select a base module type (ex: Counter, Memory, or

Shift-register)
Customize the module: select bus size and function (ex:

Johnson Counter)
Select OK to create a schematic symbol and a

simulation model for the selected module
Use the LogiBLOX module in the design the same as

any other component.
CIC
You can simulate in functional or timing mode
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- Lib -
LogiBLOX Combinatorial Logic

Simple Combinatorial
Logic
Bus size from 2 to 32 bits

Supports AND, Invert,
NAND, NOR, OR, XNOR,
XOR
Any of the inputs or
output can be inverted
independently
Use Decode or
MASK function
Three-State Drivers
Bus size from 2 to 32 bits

Optional pull-up resistors
Constants
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- Lib -
Allows signals to be tied

high or low

with XACTstepTM M1
Project Manager
Project Manager Overview

Manages and supervises all Foundation Series tools
involved in the design process
Integrates all Foundation tools into a unified

environment.
This environment includes such tools as
Schematic Editor
HDL Editor
State Diagram Editor
Fast gate-level Logic Simulator
External third-party programs
Project Manager is designed to work with one project at

a time.
CIC
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- FndPM -
Project Manager Performs

Functions
Automatically loads all design resources when a project
is open.
Checks if all project resources are available and up-todate.
Shows the design process flow.

Provides buttons for launching applications involved in
the design process.
Provides interface to external third-party programs.

Places all error and status messages in the message
window.
Provides automated data transfer between tools

involved in processing your designs.
Provides design status information.

CIC
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- FndPM -
Typical Design Flow

Creating the initial description of the design.
schematic
non-schematic
hardware description languages
graphical state diagrams
mix these types of description in your projects.
Functional simulation of the design

based on the netlist generated by the design entry tools
(schematic, HDL code, state diagram).
Running the Place & Route program

produce a bit stream file and timing netlist.
Timing simulation of the design

based on the post-layout timing netlist.
CIC
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- FndPM -
Foundation Project Manager

Application Icon
& Design Flow
Library &
Schematic
List
Message
CIC
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- FndPM -
File Menu I
New Project - Creates and opens new project.
CIC
Open Project - Opens an existing project.

Copy Project - Copies an existing project.
Delete Project - Deletes an existing project.
Archive - Packs and saves project and environment
files.
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- FndPM -
File Menu II
Project Info - Displays project information.
Libraries - Enables operations on project libraries.
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- FndPM -
File Menu III

Project Type - Changes project configuration.
Configuration - Changes system configuration.

Exit - Exits Project Manager
CIC
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- FndPM -
Tools Menu I
CIC
Schematic Editor - Starts Schematic Editor

State Editor - Starts State Diagram Editor
HDL Editor - Starts HDL Editor
Simulator - Starts Logic Simulator
Library Manager - Starts Library Manager
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- FndPM -
Tools Menu II
Symbol Editor - Starts Symbol Editor
LogiBLOX - Starts a facility designed to define
LogiBLOX components. (FPGA Only)
Import LogiBLOX Converts the existing

EDN module netlist
into the binary ALB
netlist and saves the
component to the
project working
library. (FPGA Only)
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- FndPM -
Tools Menu III

JEDEC to ABEL Conversion - Converts a JEDEC
file to ABEL (CPLD only)
Checkpoint Simulation - Selects the netlist for

timing simulation and launches the simulation.
CIC
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- FndPM -

with XACTstepTM M1

Basic Design
Design Entry Tip - Label Nets

Label as many nets as possible
Net names are passed to report files
Eases debugging
Names may change due to hierarchy or
optimization
An IOB is named by the net between the pad

and I/O function primitives
A CLB is named by the net on the output

Flip-flops are always outputs
CLB Q2
IOB IN1
IN1
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D Q
- FndSch -
Q2
Use Legal and Readable Names

Allowable characters
Alphanumeric: A - Z, a - z, 0 - 9
Underline _, Dash Reserved characters
Angle brackets for buses <>
Slash / for hierarchy
Dollar sign $ for reference designators
Names must contain at least one non-digit

Avoid using names that correspond to device
resources
CLB row/column locations: AA, AB, etc.

IOB pin locations: P1, P2, etc.
CIC
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- FndSch -
Component Naming
Conventions
Common component names, pin names and
functions for all families
Basic format is
<function><width><control_inputs>
CB4CLE = Counter, Binary, 4 bits, Clear, Load, Enable
FD16RE = Flip-flops, D-type, 16 bits, Reset, Enable
Control inputs are referenced by a single letter

C = asynchronous Clear, R = synchronous Reset
Listed in order of precedence
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- FndSch -
Use Hierarchy in Design
Adds structure to design

Eases debug
Users can build libraries of common functions
Allows each design portion to be entered by
most efficient method
Facilitates incremental design and

floorplanning
Supports team design
CIC
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- FndSch -
Schematic Editor Overview

Support for multiple sheet, flat and hierarchical
schematics.
Integration with Logic Simulator providing for nonschematic simulation.
Integration with non-schematic design entry tools (HDL

Editor and State Diagram Editor), providing for the use
of non-schematic macros.
Import of Viewlogic schematics.

Schematic netlist exported to XNF,
XNF EDIF and VHDL
formats.
Support for both board-level and FPGA schematics.
CIC
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- FndSch -
Schematic Editor
Select and Drag

Hierarchy Push/Pop
Symbol toolbox
Draw wires
Draw bues
Draw bus taps
Add Net or Bus name
I/O Terminal
Power Symbol
Graphics toolsbox
CIC
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- FndSch -
Starting a New Schematic

By clicking the Schematic Editor button
in the
flowchart
By choosing Schematic Editor from the Tools menu.

By clicking the Schematic Editor button in the
toolbar.
By double-clicking in the hierarchy tree the name of the

schematic document you wish to open.
CIC
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- FndSch -
Component Libraries I
Library Types
System Libraries
User Libraries
Project Libraries
System libraries - These libraries are automatically
added to the project by rule. ex: XC4000E
Project working library - It is the default storage for user
macros generated throughout the development of the
project. This library is created automatically when you
are setting up a new project.
Choosing Project Libraries

To add or remove project libraries for the current
project:
1. Choose Project Libraries from the File menu.
The Project Libraries dialog box will open.
CIC
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- FndSch -
Component Libraries II
2. To add a library to the project, select it in the
Attached Libraries box and click Add>>.
3. To remove a library from the project, select it in
the Project Libraries box and click <<Remove.
4. Click Close to complete the operation.
CIC
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- FndSch -
Placing, Deleting and Moving

Symbols I
Switch to the Symbols mode and open the SC
Symbols toolbox
choose Symbols from the Mode menu or click the

Symbol toolbox button
in the Schematic toolbar.
Placing Symbols
1. Select the desired symbol from the list in the toolbox.
2. Move the mouse pointer over the desired location on
the schematic.
3. If you need to rotate or mirror the symbol before
placement, do one of the following:
Press Ctrl + R to rotate the symbol by 90 degrees
right (clock-wise).
Press Ctrl + L to rotate the symbol by 90 degrees
left.
Press Ctrl + M to mirror the symbol.
4. Click the mouse button to place the symbol.
CIC
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- FndSch -

Symbols II
Using Library Filter
1. Click the Symbol Filter button
located in the SC
Symbol toolbox. The Library Filter dialog will open.
2. Select the desired symbol attributes. By default, all
attributes are selected. To clear all the settings, click
Clear. To restore default settings, click Default.
3. If you want to impose some restrictions on names of
displayed components, enter the name pattern in the
Symbol Name edit box. The pattern can include
asterisk
wildcards (*).
An asterisk
stands for any
string.
4. Click OK for
the changes to
take effect.
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- FndSch -

Symbols III
Deleting Symbols
To delete a symbol, select it with the mouse button and
press the Del key or choose Delete from the Edit
menu.
If you want to preserve buses and wires connected to
the symbol you are going to delete, you have to
disconnect the symbol before the deleting operation. To
disconnect a symbol, select it with the mouse and click
the Disconnect Symbol button
Moving Symbols
1. Move the mouse pointer over the symbol you wish to
move.
2. Press the mouse button, and holding it move the
symbol to a new location.
3. Release the mouse button to place the symbol at the
new location.
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Symbols IV
Replacing symbols
1. Select the symbol, and then click the Disconnect
Symbol button
in the main toolbar.
2. Delete the symbol by pressing the Del key or
choosing Delete from the Edit menu.
3. Click the Symbol toolbox button, select a new
symbols from the SC Symbols toolbox and place it in
exactly the same place as the previous symbol.
4. Click the Symbol toolbox button to return to the
Select and Drag mode.
5. Select the symbol, and then click the Connect
Symbol button in the main toolbar. The new symbol
will get connected.
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Symbols V
Placing Wire Terminals
1. Click the I/O Terminal button in the Schematic
toolbar.
2. Select the type of the terminal from the Terminal
Type list box and type its name in the Terminal Name
box.
3. Click the OK button
to close the dialog. The
mouse pointer will adopt a new shape .
4. Move the mouse pointer over the desired location
and click the mouse button to place the
terminal symbol.
5. If you want to place several terminal
symbol whose name consist of a fixed
prefix and consecutive numbers, click
the Repeat button instead of OK.
CIC
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- FndSch -

Symbols VI
Placing Power Symbols
1. Click the Power Symbol button in the Schematic
toolbar. Schematic Editor will automatically switch to
the Draw Wires mode and the PWR dialog box will
open.
2. From the PWR Signal Type list box select the
desired power new type.
3. Click OK to close the dialog. The mouse pointer will
adopt a new shape
4. Move the mouse pointer over the desired location
and click the mouse button to
place the power symbol.
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Drawing Wires I
Switch to the Draw Wires mode
Choose Draw Wires from the Mode menu or click the
Draw Wires button in the Schematic toolbar.
In this mode the mouse looks as
Draw a wire
1. To Start a wire, Click a pin or terminal or existing
wire. When you move the mouse pointer now, a
temporal wire line will be stretched between its origin
and the current location of the mouse pointer. To
anchor a corner, click the mouse button. The fixed
segment of the wire will turn blue.
2. Cancel the connection by pressing the Esc key, thus
switching back to the Drag and Select mode.
3. To complete the connection, move the mouse pointer
over another pin, terminal or wire, and then click the
mouse button.
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Drawing Wires II
Naming Wires
1. Switch to the Select and Drag mode
2. Double click the wire you want to name, the Net
Name window will open.
3. Type the desired name in the Net Name box, and
then click OK.
Renaming Wires
1. Double-click an appropriate wire. The Net Name
dialog box will open.
2. Edit the name in the Net Name box, and then click
OK. All labels attached to the net will change to the new
name.
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Drawing Wires III

Renaming Wires with Terminals
1. Double-click an appropriate wire. The I/O Terminal
dialog box will open.
2. Edit the name in the Terminal Name box, and the
click OK.
Moving Names
1. Switch to the Select and Drag mode.
2. Select it and drag to the desired location.
Moving Wires
1. Switch to the Select and Drag mode.
2. Move the mouse pointer over the wire segment you
wish to move.
3. Press the mouse button and holding it, move the wire
segment to a new location.
4. Release the mouse button to place the wire segment
at the new location.
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Using Buses I
Naming Conventions
A generic bus name consists of an identifier followed by
index bounds enclosed in square brackets:
BUS_NAME[X:Y]
X and Y are integer numbers greater or equal 0.
There can be both X>Y and X<Y. If the both index
bounds can be equal (X=Y), the bus consists of a
single discrete signal.
Data[3:0] = (Data3, Data2, Data1, Data0)
Data[0:3] = (Data0, Data1, Data2, Data3)
Data[2:2] = Data2
Bus Pins
Bus pin
Regular pin
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Using Buses II
Bus Taps
Bus Terminals
Input
Output
BiDirectional
Unspecified
Connectivity Rules
DT7=A7
DT6=A6
DT5=A5
DT4=A4
DT3=A3
DT2=A2
DT1=A1
DT0=A0
CIC
EA15=B7
EA14=B6
EA13=B5
EA12=B4
EA11=B3
EA10=B2
EA9=B1
EA8=B0
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XOUT8=S7
XOUT9=S6
XOUT10=S5
XOUT11=S4
- FndSch -
bus terminal
Using Buses III

Unnamed Buses
AOUT3=BIN7=CIN15
AOUT2=BIN6=CIN14
AOUT1=BIN5=CIN13
AOUT0=BIN4=CIN12
BIN3=CIN11
BIN2=CIN10
BIN1=CIN9
BIN0=CIN8
OUX3=D7
OUX2=D6
OUX1=D5
OUX0=D4
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Using Buses IV
Editing Bus Connections
Double-clicking a bus pin opens the Bus Pin
Connections dialog box, which allows you to enter the
exact sequence of signals connected to the bus pin.
XA7=A3
XA6=A2
XA5=A1
XA4=A0
XA3=QA
XA2=QB
XA1=QC
XA0=A7
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Using Buses V
Drawing Buses
switch to the Draw Buses mode, choose Draw Buses
from the Mode menu or click the Draw Buses button
in the Schematic toolbar.
The mouse pointer in the Draw Buses mode looks as
To connect a bus pin or bus terminal with another bus
pin or bus terminal:
1. Click the first bus pin or bus terminal.
2. Cancel the connection by pressing the Esc key,
thus switching back to the Drag and Select mode.
3. To complete the connection, move the mouse
pointer over another bus pin or bus terminal, and
then click the mouse button.
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Using Buses VI
Adding Bus Terminals
To add a bus terminal to an existing bus segment:
1. In the Drag and Drop mode, double-click the bus
segment close to its end where you wish to add a
terminal. The Add Bus Terminal /Label dialog box will
open.
2. Specify the name of the bus segment, index bounds
and the type of the terminal (I/O marker).
3. Click OK to complete the operation.
If you started drawing a bus segment, you can end it

with a bus terminal. To do so:
1. Click with the right mouse button to detach the
temporal bus line from the mouse pointer.
2. Click the I/O Terminal button in the Schematic toolbar.
The Add Bus Terminal /Label dialog box will open.
3. Specify the name of the bus segment, index bounds
and the type of the terminal (I/O marker).
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Using Buses VII

Automatic Drawing Bus Taps
This mechanism ensures that connections between the
bus and symbol pins are automatically drawn and
labeled with the names of consecutive bus members.
To automatically draw connections between a bus and
discrete pins of a symbol:
1. Click the Draw Bus Tap button
in the Schematic
toolbar, or choose the same command from the Mode
menu.
2. Click the bus to which you want to draw connections.
3. Click the symbol pin. A wire will be automatically
drawn between the pin and bus. After this operation, the
index in the name of the current bus member will be
incremented by 1.
4. Click remaining pins in the desired sequence.
5. Press the Esc key to return to the Select and Drag
mode.
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Checking Connections
SC Query /Find window that allows you to
unambiguously check connections on schematics

choose Query from the Edit menu
or click the Query Window button
Querying Connections
find out what symbols and pins are
connected by a given wire or bus net
select the net with the mouse.
find out what nets are connected to a
given component symbol
select the symbol with the mouse.
Searching for Schematics Items

Specify the type of the schematic item you want to find
Specify what schematic sheets should be searched.
Type the item name in the Search Box, and then press
the Enter key to launch the search.
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Page Setup
When you open a new sheet in Schematic Editor, it has
a default setup, including the page size, frame,
information table, etc.
To change the default page setup:

1. Choose Page Setup from the File menu. The Page
Setup dialog box will open.
2. Select the page size and orientation in the Sheet
Format field.
3. Set up the ruler and /or frame parameters.
4. Click OK to set your
preferences.
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Editing Schematic Table

A schematic sheet can contain a standard information
table with information on project, revision, vendor, etc.
To edit the table contents:

1. Choose Table Setup from
the File menu. The Edit
Standard Table dialog
box will open.
2. Enter data that you want
to be displayed in the table
3. Click OK to complete the
operation.
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Zooming Schematics
Zoom in or out a schematic
Using Scanner
Zoom in
Schematic Editor allows you to magnify

a portion of a schematic in a separate
Scanner window.
Zoom out
Open the Scanner window, View > Scanner
select the schematic region
which you want to scan.
set the desired scaling
factor for the Scanner window.
Select the desired region for
scanning directly,
View > Move Scanner
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Zoom area
Full Page
Creating Schematic Netlist

A netlist is a description of connections
between schematic components.
A netlist is generated from project schematics

and saved to a binary file with the ALB
extension.
The netlist is generated automatically when

you start functional simulation.
To create a project netlist, choose Create

Netlist from the Options menu.
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Exporting Netlists
Schematic Editor supports conversion of the
binary ALB netlist into a selected text format
To export the project netlist into a selected text

format:
1. Choose Export Netlist from the Options menu. The

Export Netlist dialog box will open.
2. From the Netlist Format list box, select the desired
format. You can choose XNF, EDIF or VHDL.
3. If you want to use a specific extension for the
exported netlist file, use the Options button.
4. Choose the source netlist ALB file. By default, the
project netlist is automatically selected.
5. Click OK to start exporting.
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Importing Netlists
Schematic Editor allows you to import an
external netlist (edif, xnf) and save it to the

project working library.
A new library object created in the process
acquires automatically generated symbol, and

behaves like a schematic primitive .
To import an external netlist:

1. Choose the Import Netlist command from the
Hierarchy menu. The Import Netlist dialog box will
open.
2. From the Netlist Format list box, select the desired
input netlist format. You can choose either XNF or
EDIF.
3. Choose the source netlist file.
4. Click OK to start importing.
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Generating Schematics from

Netlists
You can generate a schematic from an existing
netlist of type ALB or EDIF.
To generate a schematic from a netlist:

1. Choose Generate Schematic from Netlist from the
File menu. The Generating Schematic dialog box will
open.
2. Select the desired netlist type from the List files of
type list box, then the desired netlist file.
3. Click the Options button to display the Page Setup
dialog box which allows you to select the desired page
size and orientation.
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with XACTstepTM M1

Manage Large Design
Methods of Partitioning Large

Schematics
Large schematics usually cannot be fitted into
a single schematic sheet.
A large schematic must be divided into smaller

portions convenient to edit and simulate.
Several top-level sheets and no schematic macros

A single top-level sheet and schematic macros
Serveral top-level sheet and schematic macros
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Adding and Removing Top-Level

Schematic Documents I
To be a part of a project, a top-level schematic
file must be attached to the project.
To add an existing top-level schematic to a

project, use Project Manager:
1. Choose Add from the Document menu. The Add

Document dialog box will open.
2. Find and select the desired schematic file. Then click
OK to complete the operation.
To create a new project schematic document

In Schematic Editor choose New Sheet from the File
menu, or click the New Schematic button in the main
toolbar.
To create a new non-project schematic sheet

Choose Scratchpad from the File menu.
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Adding and Removing Top-Level

Schematic Documents II
To remove a top-level schematic file from a
project, use Project Manager:
1. Select the file in the hierarchy browser.

2. Choose Remove from the Document menu, or
press the Esc key. Project Manager will prompt you to
confirm the operation.
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Opening Schematic Documents

In Schematic Editor you can open the following
schematic documents:
top-level sheets
non-project sheets
macro sheets
To open a schematic document:

1. Choose the Open command from the File menu. The
Open Sheet dialog box will open.
2. Select the desired document.
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Creating Macros from Current

Sheet
You can convert a top-level schematic
document or non-project document into a

macro.
To convert the schematic sheet displayed in

the active window:
1. Choose Create Macro Symbol From Current Sheet

from the Hierarchy menu. The Create Symbol dialog
will open.
2. Enter the Symbol Name box enter the macro name.
You can edit other
parameters as desired.
3. Click OK to complete the
operation. If the sheet was
attached to the project, it will
be automatically removed.
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Using New Symbol Wizard I

The New Symbol Wizard is a tool that guides
you through the procedure to create a macro

symbol.
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Using New Symbol Wizard II
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Symbol Editor Overview I

Symbol Editor is an application designed for
creating and editing symbols. It allows you to

edit shape, pins, pin descriptions and numbers
for the component symbol.
You can start Symbol Editor in one of the

following ways:
From Project Manager:

Choose Symbol Editor from the Tools menu or
click the corresponding toolbar button .
From Schematic Editor:
Select the component symbol you wish to edit, and
then choose Symbol Editor from the Options
menu or press Ctrl+E.
From Library Manager:
On the Objects tab, double-click the name of the
component whose symbol you wish to edit.
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Symbol Editor Window II
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Symbol Properties
To specify symbol attributes select the desired
symbol in the Select mode and click on the
Properties icon
Double click the symbol
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Navigation through Project

Hierarchy
Switch to Hierarchy mode
Choose Hierarchy Push from the Hierarchy menu or
click the Hierarchy Push /Pop button in the
Schematic toolbar.
The mouse pointer adopts a different shape, shown as
To leave the Hierarchy mode

Choose again Hierarchy Push from the Hierarchy
menu, click the Hierarchy Push /Pop button in the
Schematic toolbar or simply press the Esc key.
To open a macros schematic, use
to
double-click the macro symbol.
To leave the macro schematic and go back to

the upper hierarchy level
Choose Hierarchy Pop from the Hierarchy menu, or

double click over empty space of the macro schematic.
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Importing Viewlogic Schematics

Schematic Editor supports import of flat and
hierarchical schematics from Viewlogic
designs.
To import a Viewlogic schematic:

1. Choose Import Viewlogic
Schematic from the File menu. Then
Select Viewlogic Schematics window
will open.
2. Select the desired schematic file(s)
and click the Options button. The
Options dialog box will open.
3. Select the desired options and click
OK.
4. Click OK to start the schematic
import.
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Integrity Test
The integrity test performs a comprehensive
analysis of the project netlist. It does not
create a netlist but detects all design errors
and inconsistencies.
Bus taps without labels. Such taps behave like hanging

wires.
Duplicated hidden net names.
Hanging wires ended with bubbles at both ends.
Hanging wire touching a symbol pin.
Two names with different bound indexes assigned to
the same bus.
Discrete wires connected to a bus (via bus taps) that
are not members of this bus.
Macro names identical to the project name.
To run the integrity test, choose Integrity Test

from the Options menu.
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Advanced Hardware Design Techniques
Combinational Logic Design

(Look Up Tables and
Other Resources)
16-bit Adder Examples

Many choices for implementing an adder
Speed vs. density trade-off controlled by user and PLD
features
Family
Type
CLBs
Levels
AppLINX
XC3000A
Bit-Serial
16
16
XAPP 022
XC3000A
Parallel
24
XAPP 022
XC3000A
Lookahead
30
XAPP 022
XC3000A
Conditional
41
XAPP 022
XC4000E-3
Carry
10.1ns
XAPP 018
XC5200-5
Carry
20ns
5200 DataSheet
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Arithmetic Functions
Arithmetic Macros are optimized for density
and speed
Example: Each CLB can form a two-bit full-adder
Most Arithmetic macros have been pre-placed

Require Vertical Orientation to maintain speed and
density
Known as RPM or Relationally Placed Macro
Examples:
A<3>
ADDx adders
B<3>
ADSUx adder/subtractors
A<2>
ADD4
CCx counters
B<2>
COMPMCx magnitude
A<1>
B<1>
comparators
A<0>
B<0>
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Z<3>
Z<2>
Z<1>
Z<0>
Three-State Buffers
Each CLB is associated with two Three-State
buffers (BUFT)
BUFTs are used independently of LUTs and Flip-Flops
Three-State library components:

Three-state buffers: BUFT, BUFT4, BUFT8, BUFT16
Wired AND (open Drain) : WAND1, WAND4, WAND8,
WAND16
Two input OR driving Wired AND : WOR2AND
Delay varies per family

2.9 ns in the XC4003E (-1)
5.6 ns in the XC4020E (-1)
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Use BUFT for Buses

Use to multiplex signals onto long routing
lines to use as buses
_ENABLE_A
_ENABLE_B
A3
B3
A2
B2
A1
B1
A0
B0
BUS<3>
BUS<2>
BUS<1>
BUS<0>
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BUFT
BUFTs for Multiplexers

BUFT can can be used to build large MUXes
Large MUXes composed of LUTs need multiple levels
of logic
Large MUXes composed of BUFTs have only one level
of logic
CLB resources are not used
Use of BUFTs constrains placement
Multiplexer macros use lookup tables

Example: M4_1E
Create BUFT macros from Three-State buffer

components
BUFT, BUFT4, BUFT8, BUFT16
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Wide Decoders
The Wide Decoder is a dedicated wired-AND
Useful for address decoding
IOBs or CLBs can drive the Wide Decoder

Located along the periphery of the die
All IOB drivers must be on same edge as the decoder
Four decoder lines per edge
Use DECODE macro

DECODE4/8/16/24
Must use a PULLUP primitive
DECODE8
A0
A1
A2
A3
A4
A5
A6
A7
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PULLUP
CLB Mapping Control in

Schematic
Allows user to force mapping of logic from
schematic into a single CLB
XC3000
CLBMap can specify entire CLB
XC4000/XC5000
FMap specifies a function generator in a CLB
HMap specifies an XC4000 H function generator in a
CLB
A0
FMAP
B0
C0
A2
B2
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A0
B0
A2
B2
I1
I2
I3
I4
C0
Synchronous Logic
(Flip-Flops and Latches)
Library Offerings
Types of Register Functions
Shift Registers
Left/Right, Arithmetic, Logical, Circular
Clock Dividers
Output Duty Cycle
Counters
LFSR, Binary, One_Hot, Carry Logic
Accumulators
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Naming Conventions
FD PE _1
Flip-Flop
D-Type (D), JK-Type (JK), Toggle-Type (T)
Asynchronous Preset (P), Asynchronous Clear (C)
Synchronous Set (S), Synchronous Reset (R)
Clock Enable
Inverted Clock
LDCE_1
Transparent D Latch
Asynchronous Preset (P),
Asynchronous Clear (C)
Gate Enable
Inverted Gate
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FD16 R E
Flip-Flop, D Type
Size
Synchronous Reset
Clock Enable
Counters
Libraries support a wide variety of fast and
efficient counters
Counters offer trade-offs between speed, density, and

complexity
Example: LogiBlox counter styles
Binary: predictable outputs, uses carry logic
Johnson: fastest practical counter, but uses more
flip-flops; glitch free decoding
LFSR: fast & dense, but pseudo-random outputs
One-Hot: useful for generating series of enables
Carry Chain: High speed and density
The LogiBlox synthesizer will automatically pick the
best implementation based on your design, or you can
force an implementation with the STYLE parameter
(schematic).
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16 Bit Counter Examples

The following are implemented in XC4000XL-3
Macro
CLBs
Clock
CB16CLE/D
18 - 20
23 - 24 ns
CC16CLED
19
19 ns
CC16CLE
16 ns
LogiBLOX: LFSR
7 ns
Simpler functions are faster and smaller

Carry Logic Counters are generally faster (depends on
size)
App Notes 001 and 014 describe fast PRE-scaled counters

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Global Clock Buffers

Clock Buffers are low-skew, high drive buffers
Also known as Global Buffers

Drive low-skew, high-speed long line resources
Drive all Flip-Flops and Latches in FPGA
Can also be used for high-fanout signals
There are five types of global buffers
Additional clocks and high fanout signals can

be routed on long lines
Otherwise routed on general interconnect

Slower and higher skew
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Using a Clock Generated OffChip

Connect IPAD directly to clock buffer primitive
Required for BUFGP
Place & route uses special fast input pin

Provides higher speed and uses fewer routing
resources
IPAD
BUFG
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Use Global Clock Buffers

Use clock buffers for highest fanout clocks
Drive low-skew, high-speed long line resources
Use BUFG primitive to be family-independent
Limit number of clocks to ease placement

issues
XC3000: 2
XC4000: 8
XC5000: 4
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XC3000 Clock Buffers

2 global clocks per device
1 primary (GCLK), 1 secondary (ACLK)
Connects to clock pins only

Can be driven by a special IOB or internal logic
Use GCLK first
IPAD
GCLK
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XC4000 Global Buffers

8 global buffers per device
4 primary (BUFGP), 4 secondary (BUFGS)
Main function is for clocks

Limited routing if used for non-clock pins
Primary buffers must be driven by a special

IOB
Secondary buffers can be driven by a special

IOB or internal logic and have more routing
flexibility
Use BUFGS if extra 1-2ns of delay is acceptable
D
IPAD
BUFGS
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Global Buffer Types - for XC4000EX

Name
Description
Applications
BUFGLS
Global Low
Skew Buffer
Recommended
driver for CLBs
BUFGE
Global Early
Buffer
BUFFCLK
FastCLK
Faster than
BUFGLS; fast IO
interface
Faster than
BUFGE for IOBs
Limitations
Cell type
Primarily
drives CLB
Drives only
one FPGA
quadrant
Slower than
BUFGLS for
CLBs
IOB or CLB
Primarily
CLB
BUFGLS is used by default in the XACT software if a

BUFG component is specified in the design
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XC5000 Global Buffers

4 global buffers per device
All BUFG
Main function is for clocks

Limited routing if used for non-clock pins
Can be driven by a special IOB or internal logic
IPAD
BUFG
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Generating Clock On-Chip

Internal configuration clock available after
configuration
Use OSC4 primitive

Nominal values (approximately):
8 MHz, (500 kHz, 16 kHz, 490 Hz, 15 Hz)
OSC4
F8M
F500k
F16k
F490
F15
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BUFGS
Global Reset
All flip-flops are initialized during power up
via Global Set/Reset network
You can access Global Set/Reset network

by instantiating the STARTUP primitive
Assert GSR for global set or reset

GSR is automatically connected to all CLB GR/GSR
flip-flops using dedicated routing resources
GTS
Saves general use routing resources for your
design
CLK
DO NOT CONNECT GSR to set/reset inputs
on Flip-Flops
Any signal can source the global set/reset,

but the source must be defined in the
design
Use Global Reset as much as possible
CIC
Limit the number of flip-flops with an

asynchronous reset
Extra routing resources are used
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Q1
Q2
STARTUP
Q3
Q4
DONEIN
Avoid Gated-Clock or
Asynchronous Reset
Move gating to non-clock pin to prevent glitch from
affecting logic
Binary Counter
Binary Counter
Q0
Q1
Q2
D Q
Carry
Q0
Q1
Q2
Carry-1
D Q
CE
CLB Delay
Or separate input signal changes by at least a CLB delay

(tILO) to minimize the likelihood of a glitch
Use Clock Enables instead of gating clock

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Shift Registers are Fast & Dense

The CLB can handle two bits of a shift register
Fast and dense independent of size
Fast connections between adjacent lookup tables
Qi-1
Left/Right
Q
EC
Qi+2
fe
Qi
EC
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Qi+1
Prescale Non-Loadable Counters

Counter speed is determined by the carry
delay from LSB to MSB
Non-loadable counters can use prescaling

Pre-scaling restricts load timing
Fast
Small
Counter
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TC
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CE
Large Dense Counter

with Slower Carry
Use One-Hot Encoding for State

Machines
Shift register is always fast and dense
One-hot uses one flip-flop for each count
Useful for state machine encoding
Another alternative is a Johnson Counter

Inverted output of last stage drives input of first stage
Doubles the number of states versus one-hot
D Q
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D Q
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D Q
D Q
D Q
State Machine Design Tips

Split complex states
Need to minimize number of inputs, not
number of flip-flops, in FPGAs
Use one-hot encoding for medium-size state machines

(~8-16 states)
Complex states may be improved by breaking

up into additional simpler states
State
A
State
A1
State
A2
cond1
cond1
cond1
State
B
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State
B
Use binary sequence only if

necessary
CLB can generate any sequence desired at same speed
Use Pre-Scaling on non-loadable counters to increase
speed
LSBs toggle quickly

See Application Notes
XAPP001 and XAPP014
Fast TC
Small
Counter
CE
Large Dense
Counter
with Slower
Carry
Use Gray code counters if decoding outputs
One bit changes per transition
Consider Linear Feedback
Shift Register for speed when

terminal count is all that is needed
CIC
Or when any regular sequence

is acceptable (e.g., FIFO)
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Q0
10-bit SR
Q6
Q9
Pipeline for Speed

Register-rich FPGAs encourage pipelining
Pipelining improves speed
Consider wherever latency is not an issue
Use for terminal counts, carry lookahead, etc.
How to estimate the clock period

2 x (number of combinatorial levels) x (speed grade)
XC4000XL-3: 3 levels x 2 x 3ns = 18 ns clock period
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Input / Output Design
How to specify IO blocks Schematic

User explicitly defines what resources in the
IOB are to be used
I/Os are defined with

1 pad primitive
At least 1 function primitive
1 input element, 1 output element or both
Inverters may also be pulled into IOBs
IOBs are named by net between pad and

function primitives
IOB IN1_PAD
IPAD
IN1_PAD
IN1
IBUF
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Slew Rate Control

Slew rate controls output speed
Default slow slew rate reduces noise
Use fast slew rate wherever speed is important
FAST parameter on output logic primitive
FAST
OPAD
OBUF
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Use Pull-ups/Pull-downs to
Prevent Floating
Pull-up automatically connected on unused
IOBs
Outputs of unused IOBs are automatically

disabled
A PULLUP or PULLDOWN primitive can be

specified on used IOBs
Inputs should not be left floating

Add a pull-up to design inputs that may be left floating
to reduce power and noise
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Choose TTL or CMOS

Thresholds
Default is TTL
Global selection on inputs or outputs
Change to CMOS in Configuration Template
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I/O Logic
4000E families have no boolean logic other
than inverters in the IOBs
XC4000EX adds optional output logic

Can be used as a generic two-input function generator
or MUX
One input can be driven by IOB output clock signal
Driving from FastCLK buffer provides less than 6 ns
pin-to-pin delay
Requires library components beginning with O
BUFFCLK
IPAD
F
FROM INTERNAL LOGIC
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OAND2
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OPAD
FAST
Fast Capture Latch (XC4000X)

Additional latch on input driven by outputs
clock signal
Allows capture of input by very fast clock

Followed by standard I/O storage element for
synchonization to internal logic
Very fast setup (6.8 NS for 4000EX-3), 0 ns hold
Available on 4000X, not 4000E family
Example
ILFFX or ILFLX macro includes Fast Capture Latch and
IFDX
Connect BUFGE to fast capture latch
Opposite edge of same clock via BUFGLS drives IFDX
Data
IPAD
BUFGE
D
GF
Clock
CIC
IPAD
feBUFGLS
- IO -
D Q
CE
to
internal
logic
Output MUX
Fast output signal (from output clock pin)
MUXes IOB output or clock enable pins to pad

OMUX2
D0
BUFFCLK
D1
OPAD
S0
IPAD
Effectively doubles the number of device

outputs without requiring a larger, more
expensive package
Pin-to-pin delay is less than 6 ns
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Decrease Setup time with

NODELAY
NODELAY attribute
Removes delay element to the IFD or ILD
Decreases setup time, add creates hold time
Available on IFD/ILD macros in XC5200 and XC4000E
families
IOB
External
Clock
Pad
External
Delay
Pad
Q D
Routing
Delay
Delay
Input
Buffer
XC4000X IOB - 2 Input Delay Elements

Full delay (default, no attribute added) : Zero Hold
with respect to Global Low-Skew Buffer, Global
Early Buffer
MEDDELAY : Zero Hold with respect to Global
Early Buffe
NODELAY : Short Setup, positive Hold time
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Output Three-State Control

Free inverter on output buffer control
Use OBUFE macro for active-high enable
Use OBUFT primitive for active-low enable
OBUFE
OE
OBUFT
OE
Three-state control also via a

dedicated global net
Controlled by same STARTUP primitive
All I/O disabled during configuration
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STARTUP
GTS
Global Buffers for XC4000E

Eight global buffers per FPGA
Four primary (BUFGP), Four secondary (BUFGS)
Primary buffers must be driven by a semidedicated IOB
Secondary buffers can be driven by a semi-
dedicated IOB or internal logic and have more

routing flexibility
Use BUFGS if extra 1-2ns of delay is acceptable
Use generic BUFG primitive in your design

Allows software to choose best type of buffer
Allows easy migration across families
D
IPAD
CIC
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BUFG
- IO -
Global Buffers for XC4000X

Global Low-Skew Buffers (BUFGLS) (8)
Standard clock buffers
To be used for most internal clocking, whenever a large
portion of the device must be driven
Global Early Buffers (BUFGE) (12)

A faster clock access
CLB access is limited to one-fourth of the device
BUFGLS and BUFGE share a single pad

The same IPAD symbol can drive one buffer of each
type, in parallel
FastCLK Buffer (BUFFCLK) (4)

provides the fastest way to bring a clock into the
XC4000X
Use generic BUFG primitive in your design

CIC
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- IO -
Global Low-Skew Buffers

Any BUFGLS (GCK1 - GCK8) can drive any or
all clock inputs on the device
CIC
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- IO -
Global Early Buffers

Left and right BUFGEs
can drive any or all clock

inputs in same quadrant
or edge (GCLK1 is
shown. GCK2, GCK5 and
GCK6 are similar.)
CIC
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- IO -
Top and bottom BUFGEs
can drive any or all clock

inputs in same quadrant.
(GCLK8 is shown. GCK3,
GCK4 and GCK7 are
similar.)
Memory Design
(RAM and ROM)
ROM is Equivalent to Logic

When using ROM, it is simply defining logic
functions in a look-up table format
Memory might be an easier way to define logic

Xilinx provides ROM library cells
FPGA lookup tables are essentially blocks of

RAM
Data is written during configuration

Data is read after configuration
Effectively operate as a ROM
As Gates
I1
I2
CIC
F1
A0
O = I1*I2
F2
fe
O
A1
- MEM -
As ROM
DATA(0)=0
F1
DATA(1)=0 X
F2 DATA(2)=0
DATA(3)=1
DOUT
RAM Provides 16X the Storage

of Flip-Flops
32 bits versus 2 bits of storage
Two 16x1 RAMS or One 32X1 Single Port Ram fit in
one CLB
One 16x1 Dual Port RAM fits in one CLB
CLB
D1
A0
A1
A2
A3
A4
32 bits
WE
CLB
D1
DQ
Q1
D2
2 bits
DQ
Q2
O1
CLK
32x8 shift register with RAM = 11 CLBs

Using flip-flops, takes 128 CLBs for data alone
Address decoders not included
CIC
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- MEM -
RAM Types
Synchronous RAM
(SYNC_RAM)
Synchronous Write
Operation
Synchronous DualPort (DP_RAM)
Data
Write Enable
Write Clock
Address
Data
Write Enable
Write Clock
Can read & write to

different
Write Address/
addresses
Single-Port Read Address
simultaneously
Dual-Port Read Address
CIC
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- MEM -
Output
SP
Output
DP
Output
RAM Guidelines
Less than 32 words is best
32x1 or 16x2 per RAM requires only one CLB
Delays are short, (one level of logic)
Data and output MUXes are required to expand depth
Less than 256 words recommended per RAM

Use external memory for 256 words or more
Width easily expanded

Connect the address lines to multiple blocks
Recommendation: Use less than 1/2 of max

memory resources
Maximum memory uses all logic resources of CLBs
CIC
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- MEM -
Memory Use
Most synthesis tools can synthesize ROM from
behavioral HDL code, but RAMS must be
instantiated
Use library primitives
and macros for

standard size memory
D
WE
A0
A1
A2
A3
A4
RAM/ROM16X1S to 32X8S
Use S suffix for Synchronous RAM
Use D suffix for Dual-Port RAM
Use LogiBlox to generate arbitrary

size memories
CIC
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- MEM -
O
RAM32X1S
How to Generate Memory

Use LogiBlox utility to create arbitrary size
RAM or ROM
Select type: ROM, Synchronous, Asynchronous, or

Dual Port RAM
Specify Depth: number of words must be a multiple of
16, ranging from 16 to 256 words
Specify Width: word size ranges from 1 to 64 bits
Specify initialization values with attribute file
LogiBLOX also creates RAM interface

Entity and component declaration - cut and paste into
the design (VHDL designs)
Module declaration (Verilog designs)
Symbol Graphic (schematic entry designs)
CIC
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- MEM -
Memory Generator Dialog

Specify memory type, size, name and function in the LogiBLOX GUI
Instance Name
LogiBLOX function
example
Memory Function
Data file for
initialization
CIC
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- MEM -
Memory Definition File I

Memory Definition File Header
Depth (optional)
depth memory_depth
Width (optional)
width memory_depth
Default
set the value of all
memory locations that
; The default radix is 10
are not specified in
Default 10; Defines the default ROM contents = 1010=10
the MEMFILE Data
section
Radix 16; Re-defines the default radix = 1610=16
Radix
Depth 10; Defines the depth = 1016=16
radix integer
Radix 10; Re-defines the default radix = 1016=16
Comments
Width 12; Defines the width = 1216=18
;
CIC
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- MEM -
Memory Definition File II

Memory Definition File Data Section
Data
data values
Data values may be separated by commas, white
space, or both
Addressing
address :
Example
depth 8
default 5
data 6,4,
8-word memory with the contents 6, 4, 5, 5, 2, 7, 5,

3, starting at address 0.
the contents of locations 2, 3, and 6 are defined via
the Default definition
4: 2, 7,
7: 3
CIC
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- MEM -
Memory Definition File III

ASCII Data
You can specify ASCII data values by enclosing a
string of characters in double quotes.
You can include a double quote by prefacing the
character with a backslash (\).
A MEMFILE may contain both ASCII strings and
numeric values.
For instance, the following defines the contents of
16 memory locations. Two ASCII BEL characters
(7) are defined here - one before the "R" and one
after the two "l" characters.
data 7, "Ring the bell", 7, 0
CIC
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- MEM -
Memory Definition File IV

Differences Between the LogiBLOX Memfile
and the Memgen/XBLOX Memfile
LogiBLOX imposes some restrictions on the memfiles

that were previously supported by Memgen or X-BLOX
5.2.1:
The LogiBLOX memfile does not allow a PART
declaration.
The radix of the data section is set by the RADIX
command in the data section and cannot be
changed. The radix cannot be overridden by using
notation such as 2#1101#.
The characters '#' and '_' are not allowed in the
memfile.
The depth value must be a multiple of 16. The valid
range is 16 to 256 words.
CIC
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- MEM -

with XACTstepTM M1
Xilinx Abel &

Foundation HDL Design
ABEL Design Entry
CIC
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Whats ABEL
ABEL Structure
ABEL Syntax
Designing with FPGAs
Foundation HDL Entry
- Abel -
Whats ABEL
ABEL-HDL (Advanced Boolean Equation Language)
A hardware description language optimized for, but not
limited to, PLD design.
Supports a variety of behavioral input forms, including
high-level equations, state diagrams, and true tables.
Allows designs to be entered and verified with little or
no concern for the target transfer files.
Easy to learn & debug under Foundation.
Completely integrated into Foundation.
CIC
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- Abel -
Test
End Vectors
Logic
Descriptions
Declarations Header
ABEL Structure I
CIC
Module source
Options -trace wave
Title 'Example of a Source File
Declarations
in1, in2, in3, clk PIN;
all, none, other PIN istype 'reg';
out = [all, none, other];
@MESSAGE Declarations completed
Equations
out.clk = clk;
all := in1 & in2 & in3;
none := !in1& !in2 & !in3;
other := (in1 & in2 & !in3) # (in1 & !in2 & in3)
# (in1 & !in2 & !in3) # (!in1 & in2 & in3)
# (!in1 & in2 & !in3) # (!in1 & !in2 & in3)
Test_Vectors
([in1, in2, in3, clk ] -> [all, none, other])
[1, 1, 1, .c.] -> [1, 0, 0];
[0, 1, 1, .c.] -> [0, 0, 1];
[1, 0, 1, .c.] -> [0, 0, 1];
[0, 0, 0, .c.] -> [0, 1, 0];
End source
fe
- Abel -
ABEL Structure II
Header
Module (Required): names the module and indicates if
dummy arguments are used.
Options : controls processing of the source file using
command line options.
Title : used to give a title or description for the module.
Declarations
CIC
Device Declaration (one per module)

Signal Declarations (pin and node numbers optional)
Constant Declarations
Macro Declarations
Library Declarations
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- Abel -
ABEL Structure III

Logic Description
Euqations
Truth Tables
State Diagrams
Fuses
XOR Factors
Test Vectors
Test Vectors
Trace Statement
Test Script
End
A module is lcosed with the end statement
Other Elements
Directives can be placed anywhere needed
CIC
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- Abel -
General Formats I
block format
{ set of instructions }
comment format
" comment text "
" comment text to the end of line
// comment text to the end of line
count := count.fb + 2; " count by 2
count.clk = clk; "clock equation" count.oe = !enable; // enable equation
identifier format
first character: letter, underscore (_) or tilde (~)
other characters: letters, digits, underscores (_) or tildes (~)
input pin;
_Q13 node;
~inv pin;
CIC
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- Abel -
General Formats II
number notation
binary: ^B or ^b
decimal: ^D or ^d
hex: ^H or ^h
octal: ^O or ^o
default is decimal, but it can be changed by directive
@RADIX
input = ^b010101;
DATA = ^HFA0;
Address1 = 101; " default is decimal - 'Address1' is decimal value 101
@RADIX 2;
Address2 = 101; " NOW default is binary - 'Address2' is decimal value 5
@RADIX 10; " return to default decimal
string format
' string '
` string `
` this is also correct string '
title 'Abel HDL binary adder'
CIC
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- Abel -
Operators I
arithmetic operators
- (one argument)
- (two argument)
+
twos complement (negation)

subtraction
addition
The Following operations are not used with sets (buses)
*
/
%
<<
>>
multiplication
unsigned integer division
modulus: remainder from /
shift left
shift right
assignment operators
=
:=
?=
?:=
combinational assignment (on-set)

registered assignment (on-set)
combinational assignment (dc-set)
registered assignment (dc-set)
Operators with '?' specify don't-care set conditions which enhances optimization.
NOTE: directive '@DCSET' or attribute 'DC' must be specified or the '?' equations are
ignored.
CIC
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- Abel -
Operators II
logic operators
!
&
#
$
!$
NOT: ones complement

AND
OR
XOR: exclusive OR
XNOR: exclusive NOR
relational operators
CIC
==
!=
<
<=
>
>=
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- Abel -
equal
not equal
less than
less than or equal
greater than
greater than or equal
Signal Declarations I
Pin declarations
[!]pin_id[,[!]pin_id...] PIN [pin#[,pin#]] [ISTYPE 'attr'];
pin_id - An identifier used to refer to a pin

throughout a module.
pin# - The pin number on the real device.
attr - A string that specifies pin attributes for
devices with programmable pins.
D7,D6,D5,D4,D3,D2,D1,D0 pin 2,3,4,5,6,7,8,9;
A,B,C,D
pin istype 'com';
Q7 .. Q0
Q7 .. Q0
pin 15 .. 22;
istype 'reg,invert';
Clk,OC,E,I2,I1,I0 pin;
CIC
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- Abel -
Signal Declarations II
Node declarations
[!]node_id[,[!]node_id...] NODE [node#s...] [ISTYPE 'attr'];
node_id - An identifier used for reference to a node

in a logic design.
node #s - The node number on the real device.
(This is useless for Xilinx.)
attr - A string that specifies node attributes for
devices with programmable nodes.
SClr0, SClr1
node 25,26; " counter reset
" Buried SR-regs
P0,P1,P2,P3,P4,P5,P6,P7 node istype 'reg_SR' ;
Attribute declarations
F0, A istype 'neg, reg' ;
q3,q2,q1,q0 node istype 'reg_SR';
reset pin;
reset istype 'com';
fe
Output pin 15 istype 'reg,invert,dc';
CIC
- Abel -
Attributes I
Valid attributes are:
CIC
'buffer'
'collapse'
'com'
'dc'
'invert'
'keep'
'neg'
'pos'
'retain'
'reg'
'reg_d'
'reg_g'
'reg_jk'
'reg_sr'
fe
- no inverter in target device

- collapse (remove) this signal (ABEL6)
- combinational output
- unspecified logic is don't care
- inverter in target device
- do not collapse this signal (ABEL6)
- unspecified logic is 1
- unspecified logic is 0
- do not minimize this output
- clocked memory element
- D-type flip-flop
- D-type flip-flop with gated clock
- JK-type flip-flop
- SR-type flip-flop
- Abel -
Attributes II
'reg_t'
'xor'
q3,q2,q1,q0
reset
reset
Output
QOUT
CIC
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- Abel -
- T-type flip-flop
- xor gate
NODE ISTYPE 'reg_SR';
PIN;
ISTYPE 'com';
PIN 15 ISTYPE 'reg,invert';
PIN ISTYPE 'reg,dc,keep';
Constant Declarations
Constant declarations
id [,id]... = expr [,expr]... ;
id - The id is an identifier that names a constant to
be used within a module.
expr - The expr is an expression that defines the
constant value.
X =.X.;
ADDR = [1,0,15];
G = [1,2]+[3,4];
A = B & C;
" X means 'don't-care'

" ADDR is a set with 3 elements
" set operations are legal
" operations on identifiers are valid
Set declarations
"multiple syntax of set declaration
RPM
= [RPM3,RPM2,RPM1,RPM0];
SREG
= [ Q2 , Q1 , Q0 ];
BRAKE
= [ H , L , H ];
MULOUT
= [B0..B7];
SELECT
= [S3..S2];
CIC
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- Abel -
Symbolic State Declarations

State_register declarations
statereg_id STATE_REGISTER [ISTYPE attributes];
sreg1 state_register;
State declarations
State_id [, state_id ...] STATE [state_value [,
state_value ...]];
S0, S1, S2, S3 state;
CIC
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- Abel -
Macro Declarations
Macro declarations
macro_id MACRO [ ( dummy_arg[,dummy_arg]... ) ] {block} ;
macro_id - An identifier naming the macro.

dummy_arg - A dummy argument.
block - A block.
" macro with arguments
NAND3 macro (a,b,c) { !(?a & ?b & ?c) };
" macro without arguments
Y1 macro {B # C};
" constant subexpression
Y2 = B # C;
equations
X1 = A & Y1
"RESULT: X1 = A & B # C;
X2 = A & (Y1);
"RESULT: X2 = A & (B # C);
X3 = A & Y2;
"RESULT: X3 = A & (B # C);
D = NAND3 (Clock,Hello,Busy); "RESULT: D = !(Clock & Hello & Busy);
CIC
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- Abel -
Equations
Syntax
Module comp4
Title '4-bit look-ahead comparator'
equations
Declarations
element [?] := condition
element [?] = condition
A3..A0,B3..B0
pin;
or
E3..E0
pin istype 'com';
[ WHEN condition THEN ] [ ! ]
A_EQ_B,A_NE_B,A_GT_B,A_LT_B pin istype 'com';
element=expression;
A = [A3,A2,A1,A0];
[ ELSE equation ];
B = [B3,B2,B1,B0];
E = [E3,E2,E1,E0];
Equations
E = A !$ B;
" intermediate An = Bn
A_EQ_B = E3 & E2 & E1 & E0;

" A=B
A_NE_B = !A_EQ_B;
" A!=B
A_GT_B = (A3>B3) #
" A>B
E3 & (A2>B2) #
E3 & E2 & (A1>B1) #
E3 & E2 & E1 & (A0>B0);
A_LT_B = !A_GT_B & !A_EQ_B;
" A<B
End comp4
CIC
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- Abel -
When-Then-Else
Syntax
[ WHEN condition THEN ] [ ! ] element=expression;
[ ELSE equation ];
or
[ WHEN condition THEN ] equation; [ ELSE equation ];
Examples
WHEN (Mode == S_Data) THEN
{ Out_data := S_in;
S_Valid := 1;
}
ELSE WHEN (Mode == T_Data) THEN
{ Out_data := T_in;
T_Valid := 1;
}
module Mux12T4
title `12 to 4 multiplexer Dave Pellerin
Data I/O Corp. Redmond WA.`
a0..a3
b0..b3
c0..c3
s1,s0
y0..3
pin
pin
pin
pin
pin
1..4;
5..8;
9..13;
18,19;
14..17;
H
= [1,1,1,1];
L
= [0,0,0,0];
select = .X. ;
y
= [y3..y0];
a
= [a3..a0];
b
= [b3..b0];
c
= [c3..c0];
equations
when (select == 0) then y = a;
when (select == 1) then y = b;
when (select == 2) then y = c;
when (select == 3) then y = c;
end
CIC
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- Abel -
State Diagram I
Declaration
state_id [, state_id ... ] STATE;
State_diagram
State_digram state_reg
[-> state_out]
[STATE state_exp : [equation]
[equation]
:
trans_stmt; ... ]
CIC
state_reg : an identifier or set of identifiers specifying the signals that

determine the current state of the machine.
state_out : an identifier or set of identifiers that determine the next
state of the machine.
state_exp : an expression or symbolic state name giving the current
state
quation : a valid equation that defines the state machine outputs
trans_stmt : IF-THEN-ELSE, CASE or GOTO statements, optionally
followed by WITH transition equations.
fe
- Abel -
State Diagram II
Example
Module scanner1
Title '4-Channel Digital Scanner Example
clk pin; clock
input1, input2, input3, input4 pin; control inputs
output, sync pin; output pins
state diagram declaration and assignment
scanreg state_register istype reg_D;
scan1, scan2, scan3, scan4 state;
xilinx property Initialstate scan1;
Equations
scanreg.clk = clk;
sync = scan1;
output = (scan1 * input1)
# (scan2 * input2)
# (scan3 * input3)
# (scan4 * input4);
State_diagram scanreg
State scan1: GOTO scan2;
End
CIC
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- Abel -
Sequential Statement - Case

Case - used under the State_diagram section
CASE expression : state_exp;
[ expression : state_exp; ]
[ expression : state_exp; ]
:
ENDCASE;
Examples
case a==0 : S1;
a==1 : S2;
a==2 : S3;
a==3 : S0;
endcase;
CIC
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- Abel -
Sequential Statement - Goto

Goto - used in the State_diagram section to
cause an unconditional transition to the state

indicated bye state_exp.
GOTO state_exp;
Examples
GOTO 0; goto state 0
GOTO x+y; goto the state x+y
CIC
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- Abel -
Sequential Statement - If-ThenElse

If-Then-Else - used under the state_diagram
section
IF-THEN-ELSE
IF exp Then state_exp
[ ELSE state_exp];
Chained IF-THEN-ELSE
IF exp THEN state_exp
ELSE IF exp THEN state_exp
ELSE state_exp;
Nested IF-THEN-ELSE
ELSE IF exp THEN
ELSE state_exp
ELSE state_exp;
CIC
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- Abel -
Sequential Statement - With

WITH - When used in conjunction with the IF-
THEN or CASE statement, it allows output

equations to be written in terms of transitions.
trans_stmt state_exp WITH equation
Examples
STATE S0:
IF (reset) THEN S9 WITH { ErrorFlag := 1;
ErrorAddress := address;}
Else IF (address <= ^hE100)
THEN S2
ELSE S0;
CIC
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- Abel -
Truth Table I
Syntax
TRUTH_TABLE ( in_ids -> out_ids )
inputs -> outputs ;
or
TRUTH_TABLE ( in_ids :> out_ids )
inputs :> outputs ;
or
TRUTH_TABLE ( in_ids :> reg_ids -> out_ids )
inputs :> reg_outs -> outputs ;
CIC
inputs : the inputs to the logic function

outputs : the outputs from the logic function
reg_outs : the registered (clocked) outputs
-> indicates the input to output function for combinational outputs
:> indicates the input to output function for registered outputs
fe
- Abel -
Truth Table II
Examples
TRUTH_TABLE ( [A,B] :> [C,D] -> E)
0 :> 1 -> 1;
1 :> 2 -> 0;
2 :> 3 -> 1;
3 :> 0 -> 1;
TRUTH_TABLE ( [en, A, B] -> C )
[0,.X.,.X.] -> .X.; dont care w/enab off
[1, 0, 0 ] -> 0;
[1, 0, 1 ] -> 1;
[1, 1, 0 ] -> 1;
[1, 1, 1 ] -> 0;
CIC
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- Abel -
Dot Extensions I
clock control
" .CE
" .CLK
clock-enable input to a gated-clock flip-flop

clock input
declarations
DFFCE
PIN ISTYPE 'reg_G';
Clk,ClkEn,DIn PIN;
equations
DFFCE.CLK = Clk;
DFFCE.CE = ClkEn;
DFFCE := DIn;
CIC
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- Abel -
Dot Extensions II
feedback control
" .COM
" .FB
" .PIN
" .D
" .Q
combinational feedback from the flip-flop data input, normalized to the pin value
register feedback
pin feedback
combinational feedback from the flip-flop data input
register feedback
declarations
Q1
pin istype 'reg';
Q2
pin istype 'reg_D,buffer';
CQ1,CQ2 pin istype 'com';
CLK
pin;
equations
Q1.CLK = CLK;
Q2.CLK = CLK;
" device-independent description
Q1 := !Q1.FB;
CQ1 = Q1.COM;
" device-specific description
Q2.D = !Q2.Q;
" on the left side .D specifies flip-flop input
CQ2 = Q2.D;
" on the right side .D specifies combinational feedback
CIC
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- Abel -
Dot Extensions III

Q1.OE
Q1.SET(.ASET)
CQ1
Q1.COM
Q1
D
CLK
Q1.CLK
Q
Q1.CLR(.ACLR)
Q1.FB
Q2.OE
Q1(.PIN)
Q2.SP(.AP)
CQ2
Q2.D
RESET
D
Q
Q2.CLK
Q
CLEAR
Q2.SR(.ASR)
Q2.Q
Q2(.PIN)
CIC
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- Abel -
Q2
Dot Extensions IV
register control
" .D
" .J
" .K
" .R
" .S
" .T
D input to a D flip-flop
J input to a JK flip-flop
K input to a JK flip-flop
R input to a SR flip-flop
S input to a SR flip-flop
T input to a T flip-flop
declarations
foo
PIN ISTYPE 'reg_JK ;
Clock,A,B,C
PIN;
equations
foo.clk = Clock;
foo.J = A & B;
foo.K = A $ C;
" Latch enable inputs

" .LE
latch-enable input to a latch (active LOW)
" .LH
latch-enable input to a latch (active HIGH)
" Other
" .FC
" .LD
" .PR
" .RE
CIC
flip-flop mode control

register load input
register preset (synchronous or asynchronous)
register reset (synchronous or asynchronous)
fe
- Abel -
Dot Extensions V
set/reset control
" Device-independet
" .ACLR
asynchronus register reset
" .ASET
asynchronous register reset
" .CLR
synchronous register preset
" .SET
synchronous register reset
" Device-specific
" .AP
asynchronous register preset
" .AR
asynchronous register reset
" .SP
synchronous register preset
" .SR
synchronous register reset
CIC
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- Abel -
declarations
RST,A,B
Q
pin;
pin istype 'reg';
equations
Q := A & B;
" flip-flop Q output condition
Q.ACLR = !RST;
" flip-flop Q reset condition
Dot Extensions VI
tristate control
" .OE
output enable
declarations
OUT
A,B,C,D
pin istype 'com';

pin;
equations
OUT = A $ D;
OUT.OE = C & D;
CIC
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- Abel -
" OUT tristate output buffer control
Special Constants
CIC
.C. low-high-low clock pulse - low-high-low clock pulse

.D. clock falling edge - clock falling edge (high-low transition)
.F. floating input or output - floating input or output signal
.U. clock rising edge - clock rising edge (low-high transition)
.K. high-low-high clock pulse - high-low-high clock pulse
.X. don't care condition
.Z. tristate value
fe
- Abel -
equations
Count.clk = Clk;
Count := (Count.fb + 1) & !Clear;
test_vectors
( [ Clk, Clear ] -> [Count] )
[ .C., 1 ] -> [ 0 ]; "clear the counter
[ .U., 0 ] -> [ 1 ]; "trigger the counter to next state
[ .D., 0 ] -> [ 1 ]; "transition down
Directives I
@Carry - Maximum Bit-width for Arithmetic Functions
syntax : @carry expression;
Use : For examples, for an 8-bit adder, an @CARRY
statement with an expression that results in 2 would
divide the 8-bit adder into four 2-bit adders. @CARRY 2
limits the lookahead carry by generating chain of 2-bit
adders.
@Dcset - Dont Care Set

Syntax : @dcset
Use : use dont-care conditions to help optimize
partically-specified logic functions.
@Onset - No Dont Care

Syntax : @onset
Use : disable the use of dont care input conditions for
optimization.
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- Abel -
Directives II
@Dcstate - State Output Dont Cares
Syntax : @dcstate
Use : all unspecified state diagram states and transitions
are applied to the design outputs as dont cares.This
option must be used in combination with @dcset or with
the dc attribute.
@If - If Directive
Syntax : @if expression {block}
Use : If the expression is non-zero(logical true), the block
of code is included.
Example : @if ( A > 17 ) { C = D $ F ; }
@Include - Include
Syntax : @include filespec
Use : cause the contents of the specified file to be placed
in the ABEL-HDL source file.
Example : @include \\inc\\macros.abl
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- Abel -
XILINX PROPERTIES I
You can specify the following attributes in your XABEL
source file using the ABEL "XILINX PROPERTY"
statement:
XILINX PROPERTY 'INITIALSTATE [state_reg_signal]

state_name';
(Defines the initial state of a 1-hot encoded state machine.)
XILINX PROPERTY 'SAVE node_name...';
(Preserves internal nodes; using ISTYPE 'KEEP' is preferred)
XILINX PROPERTY 'BLOCK {reg_signal | state_name}
attrib_name[=attrib_value]';
(Assigns arbitrary XACT-M1 attributes to registers in the
design.)
XILINX PROPERTY 'OPTIMIZE {AREA | SPEED | BALANCE
| OFF}';
(Selects OPTX optimization strategy for FPGA XABEL
modules.)
XILINX PROPERTY 'OPT_EFFORT {NORMAL | HIGH}';
(Selects OPTX optimization effort for FPGA XABEL modules.)
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- Abel -
XILINX PROPERTIES II
XILINX PROPERTY '{FAST | SLOW} output_pin...';
(Selects output slew rate for output pins in top-level XABEL
design.)
XILINX PROPERTY 'BUFG={CLK | OE | SR} input_pin...';
(Assigns global buffers to input pins in top-level XABEL design.)
XILINX PROPERTY 'IO reg_signal...';
(Defines registers to be implemented in the IOBs.)
XILINX PROPERTY 'INIT={R | S} reg_signal...';
(Defines initial state of registers.)
XILINX PROPERTY 'WIREAND node_name...';
(Defines logic nodes to be implemented in the CPLD
interconnect array.)
XILINX PROPERTY 'PWR_MODE={LOW | STD}
signal_name...';
(Selects macrocell power mode for nodes or outputs in CPLD
designs.)
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- Abel -
XILINX PROPERTIES III

XILINX PROPERTY 'TNM=string signal_name...';
(Tags signals with a Timing-group Name to be used in a
Timespec.)
The following ABEL attributes are automatically
forwarded to the Implementation software via the EDIF

netlist:
ISTYPE 'KEEP'
(Preserves internal nodes in both ABEL compiler and
design implementation.)
ISTYPE 'RETAIN'
(Preserves redundant logic terms in both ABEL and design
implementation.)
In addition, pin numbers specified in top-level XABEL

designs are written to the EDIF netlist as LOC constraints
for design implementation.
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- Abel -
XILINX PROPERTIES IV
Xilinx Property Example
module test
Title 'This is a test.'
XILINX PROPERTY 'OPTIMIZE OFF';
Declarations
A PIN 3;
B PIN 5;
SUM PIN 15 istype 'com';
Carry_out PIN 18 istype 'com';
t1, t2 node istype keep;
Equations
t1=A&!B;
t2=!A&B;
SUM=t1#t2;
Carry_out=A&B;
end test
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- Abel -
Hierarchy (Example)
Module ANDORINV
Title 'And - Or - Invert gate'
" ---- lower-level modules ----
Declarations
Module AND
Interface ( A,B -> Y );
AND interface ( A,B -> Y );

NOR interface ( A,B -> Y );
A1,A2 functional_block AND;
N
functional_block NOR;
I1..I4
Y
N1,N2
pin;
pin istype 'com';
node istype 'com';
Equations
A1.A = I1;
A1.B = I2;
N1 = A1.Y;
Title 'Two input NOR gate'

Declarations
A,B pin;
Y pin istype 'com';
Equations
Y = !( A # B );
End NOR
N.A = N1;
N.B = N2;
Y = N.Y;
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" -----------------------Module NOR

Interface ( A,B -> Y );
A2.A = I3;
A2.B = I4;
N2 = A2.Y;
End ANDORINV
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Title 'Two input AND gate'

Declarations
A,B pin;
Y pin istype 'com';
Equations
Y = A & B;
End AND
- Abel -
Using Hierarchy
You use hierarchy declarations in an upper-level ABELHDL source to refer to (instantiate) another ABEL-HDL
source. To instantiate an ABEL-HDL source file, you
need to do the following:
In the lower-level source: (optional)
1. Identify lower-level I/O Ports (signals) with an
Interface statement
In the top-level source:
2. Declare the lower-level source with an Interface
declaration
3. Instantiate the lower-level source with
Functional_block declarations.
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- Abel -
Designing with FPGAs I

FPGA Design Strategies
Define external and internal signals with pin and node
statements, respectively.
For state machine and truth tables, include @DCSET or
dc attributes if possible, since it usually reduces logic.
Use only dot extensions appropriate for FPGA design.
Information on using dot extensions is provided in the
specific FPGA fitter user manuals.
Use intermediate signals to create multi-level logic to
match FPGA architectures.
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- Abel -
Designing with FPGAs II

Declaring Signals
Pin Statements
Pin numbers are optional in ABEL-HDL and are not
recommended for FPGAs.
If you declare an external signal as a node instead
of a pin, the device fitter may later interpret the
signal incorrectly and delete it.
Node Statements
Signals declared as nodes are expected to have a
source and loads.
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- Abel -
Designing with FPGAs III

Using Intermediate Signals
Reduces the amount of optimization a device fitter has
to perform
Increases the chances of a fit
Simplifies the ABEL-HDL source file
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- Abel -
Foundation HDL Entry

Features of Foundation HDL Entry
Support two languages : ABEL and VHDL(need another
license)
Provide very useful instrument, Language Assistant
Syntax correctness of the code created within the HDL
Editor
Has interface to synthesis tools which generate XNF
netlist from HDL source code
How to run HDL Entry

By choosing HDL Editor from the Tools menu.
By clicking the HDL Editor button in the toolbar .
By clicking the HDL Entry button in the project flowchart
(provided that the current project type supports HDL
Editor).
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- Abel -
Create a New File

Click use HDL Design Wizard or create
empty
Use Design Wizard

Use Language Assistant
to Edit
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- Abel -
HDL Editor Window
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- Abel -
Synthesize ABEL
Configuration
Synthesis -> Configuration
Check Syntax
Synthesis -> Check Syntax
Choose Options
Synthesis -> Options
Synthesize
Synthesis -> Synthesize
ABEL General Options for Xilinx FPGA devices

Compile:
Chip - enables insertion of IBUF and OBUF pads; used for HDL type projects.
Macro - disables insertion of IBUF and OBUF pads; used for schematic type projects.
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- Abel -
ABEL Details
To know more about ABEL
Refer to DATA I/Os XILINX-ABEL manual
Foundation HDL Entry - Language Assistant
Xilinx Foundation Series On-Line Help System
To make writting ABEL code easy

Use Foundation HDL Entry Editor to edit your ABEL
files
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- Abel -

with XACTstepTM M1
Foundation State Editor
State Editor Overview
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- FndStat -
State Editor Window
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- FndStat -
Opening State Editor

To open the State Editor
click
button in the Project Manager window.
click button in the Project Managers tools bar
Tools -> State Editor... in the Projects Manager
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- FndStat -
Using HDL Design Wizard
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- FndStat -
Using HDL Design Wizard
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- FndStat -
Edit a Diagram I
To add a port to a diagram
1. Choose Input Port, Output Port or
Bidirectional Port command from the FSM menu.
2. Place the port on the current diagram.
To add a signal to a diagram

Signal allows to define an additional internal variable
and signals. Signals can be declared for the entire
diagram, but variables can only be defined for
machines.
1. Choose the Signal command from the FSM menu.
2. Place the signal icon in the desired place on a
diagram.
To add a reset to the diagram

1. Choose the Reset command from the FSM menu.
2. Place the reset icon in the desired place within
machine frames.
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- FndStat -
Edit a Diagram II
To add a state to a machine
State is a fundamental element of the machine. Each
state represents a certain condition of the machine,
including values of its ports and signals.
1. Choose the State command from the FSM menu.
2. Place the state bubble on the current diagram (within
machines frame).
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- FndStat -
Edit a Diagram III

To draw a transition between states
Transitions connect states and describe the sequence
of states. Transitions are also used for connections with
the reset and entry/exit (for hierarchical states).
1. Choose the Transition command from the FSM
menu.
2. Click over the state where the transition begins.
3. Click over the state where the transition ends.
4. Click over a diagram to end the operation.
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- FndStat -
Edit a Diagram IV
To add a condition to a transition
Condition is a Boolean HDL expression associated with
a transition. If it is true, the machine goes from one
state to another.
1. Choose the Condition command from the FSM
menu.
2. Click on the transition you wish to add condition for.
3. Enter the condition's text.
4. End conditions editing by clicking the left mouse
button.
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- FndStat -
Edit a Diagram V
To add an action to a state
Action is a set of HDL statements, which assigns new
values to ports or internal signals/variables.
1. Choose the Action command from the FSM menu. It
displays a submenu.
2. Select either Entry, State or Exit, depending on the
type of action you want to add. The mouse pointer
changes into an action line, with a black dot at the
beginning.
3. Click with the black dot end over the desired state.
4. Enter the action's text.
5. End actions editing by clicking the left mouse button.
Entry Action is executed when a machine is entering the state with which the action is
associated.
State Action is executed when a machine remains in the state with which the action is
associated.
Exit Action is executed when a machine is leaving the state with which the action is associated.
Transition Action is executed when a machine is going through the transition with which the
action is associated.
Diagram Action is executed concurrently with the machines.
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- FndStat -
Edit a Diagram VI
To choose the clock of a machine
1. Choose the Machines command from the FSM
menu.
2. Select the machine from the displayed submenu. It
displays the Machine Properties dialog box.
3. Select the desired clock from the list of clock ports.
4. Click OK.
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- FndStat -
Edit a Diagram VII

Synthesize
Synthesis -> Configuration ...
Generate a Chip
Synthesis -> Options ... > Chip
Synthesis -> Synthesize
Create a macro
Synthesis -> Options ... > Macro
Project -> Create macro
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- FndStat -

with XACTstepTM M1
Simulation Basics
Start to Simulate
From Project Manager
Press SIM Funct or SIM Timing button
From Schematic Editor

Press Simulation Toolbox or Simulator icon
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- FndSim -
Simulation From Schematic

Probe tool Stimulator tool Simulator Delete probes
Simulation toolbox
Previous event Next enevt Simulate Save Probes
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- FndSim -
Logic Simulator Window

Display Comments Measurements
On/Off
On/Off
Select Probes
Logical States
Bus On/Off
Stimulus
Delete all
waveforms
Ruler On/Off
Zoom Out (LSR)

waveforms button
I/O type
Signal or pin name
Zoom In (ESR)
waveforms button
simulator name
logical state at the
current cursor
position
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- FndSim -
The waveform window toolbar I

Ruler On/Off button - you can enable or disable the waveform window ruler.
If you don't need to see the waveforms referenced to the time scale, you should disable the
ruler to allow more room for signals.
Delete all waveforms - this button allows you to delete all waveforms and
comments.
Display Comments On/Off - this button allows you to toggle on/off the
comment display. The comments are used to document important situations on the
waveform diagram and can be both displayed at the specified screen locations and printed
with the waveform diagram.
Measurements On/Off - this button enables you to perform and display

precise timing measurements between any signal transitions, regardless of the scale.
Bus On/Off - clicking on this button is meaningful only if you have defined some
buses either in the waveform window or on the schematic. Buses are comprised of several
signals or pins and can be displayed in HEX (Condensed) mode or in Discrete mode, in which each
signal line is shown individually.
Select Probes button - this button is used to invoke the Probes Selection
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window which is used to select signals and IC pins to the waveform window.
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- FndSim -
The waveform window toolbar II

Stimulus button - this button invokes the Stimulus window that is used to
define and assign stimulators or test vectors to the desired signals. The Stimulus
window includes the Binary Counter, keyboard keys and asynchronous clocks. It also
has the Custom test vector key ("Cs" key) that is used for assigning user defined test
vector to any input or output and Formula key that allows assigning formulas to clocks
or Fn stimuli.
Logical States button - invokes the logical state selection window
that allows you to select and assign any logical state to a signal name or device pin.
Logical states can be assigned to input pins and signals, and they can also be forced
on the output pins.
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- FndSim -
Simulator I
Schematic editor button - clicking on this button switches the
screen to the ACTIVE-CAD schematic editor program. If this editor has already been
started, ACTIVE-CAD will display its window. Otherwise the schematic editor will be
started, and the schematics associated with the simulator netlist will be loaded.
Short and Long Step simulation buttons - they are
used to perform short and long simulation steps with a single click of the mouse button.
Binary counter - the status of the 16 bit binary counter is displayed in the
form of red and yellow LED lights. The red means that the bit is at a logical high or 1,
and the yellow means logical 0.
Simulation mode setup - allows you to select between TM - timing
mode with a 10 picoseconds resolution, UN - unit delay mode with propagation delays
equal to simulation precision, GL - glitch mode with propagation delays set to
simulation step and FN - functional mode with zero propagation delays.
Search button - allows you to select an item or condition to be searched for

in a timing diagram. You can choose from such items as Breakpoints, Errors, Events,
Milestones and Tags.
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- FndSim -
Simulator II
Search Forward and Backward buttons - they allow
for a quick search of timing areas that have been marked red by the simulator program.
Stop Simulation - this button stops simulation at the current simulation

cycle.
Power On button - it initializes the entire design. Power On is performed

automatically at the beginning of simulation and after each interactive connectivity
change.
Search Forward and Backward
Schematic editor
Short and Long Step
Search
Power On
Stop Simulation
Simulation mode
setup
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- FndSim -
How to Add Signals to your Sim.

Press Select Probes button to open Component
Selection
Add signals to Waveform Viewer - there are three

methods
Select a signal or press Ctrl and select multiple signals, then

press Add button
Double click a signal
Select signals and then drag them to Waveform Viewer
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- FndSim -
Creating and Applying Design

Stimulus Signals
Applications of ready made test vectors using
the virtual stimulator
This is a 16 bit software-driven binary counter that

counts at a preset clock rate.
Toggling signal lines with keyboard keys

Signals in the waveform viewer can be mapped to keys
on the keyboard so enabling real time user control
Formula
16 signals in the simulator selection tool can each be
assigned a formula.
Drawing test vector waveforms

An editor permits waveforms to be drawn in the
waveform viewer window.
Using an existing Viewlogic command file

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- FndSim -
Stimulator Selection Window

How Use Ready-Made Stimulators
Click on Add Stimulators in the Stimulators menu
Click on the selected signal name
After the selected signal name turns blue, click on the
desired stimulator
The selected stimulator name appears in the Stimulator
column, next to the signal line
Asynchronous clocks
can be defined for
special clock signals
Keyboard keys allow

you to toggle signal
logical states directly
from the keyboard
CS - Custom Signal;
indicates a manually
drawn test vector
Software-emulated
binary counter
TRUE outputs
INVERTED outputs
Formula stimulators
defined in the Formula Editor
Formula Editor and

Clock Editor
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Control buttons
- FndSim -
Mapping Signal to Stimulator

Selection
Counter, Keyboard, and Formula
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- FndSim -
Applying Formulas
Examples:
(H2L3)3 - High for 2 ns

the Low for 3 ns, repeat
3 times
H4usL1us - High for 4
us the Low for 1 us
SYMBOL
H,L
X
Z
0..9
(
ps, ns, us,

ms
[ ]
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DESCRIPTION
high and low logic level (1 and 0)
unknown ( high or low)
high impedance
numbers user for defining duration
and repetitions
parentheses for selecting subexpressions
time unit definition for duration
arguments, default is ns
brackets for defining hex bus value
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- FndSim -
Drawing Waveforms I
Waveform > Edit

Low is a strong Low logical level
High is a strong High logical level
Unkn_X is a strong Unknown logical level
High_Z is a week 3-state state that can be overridden by weak
signals
Cnf_X indicates the presence of two strong signals of different

logical values in the same node
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- FndSim -
Drawing Waveforms II
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Res_L is a weak Low logical level

Res_H is a weak High logical level
Res_X is a weak Unknown logical level
Ref_V is a special logical level signal (ECL)
High_V is a special high voltage level
SV_L is a strong power supply signal which overrides other signals
SV_H is a strong power supply signal which overrides other signals
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- FndSim -
Preferences - Simulation window

I
Options -> Preferences
B0 period or B0 frequency - selection of the
period/frequency of the bit 0 of the software-driven 16bit binary counter.
Simulation precision - Select desired value from the
Simulation Precision box. Please note that the

simulation precision is different from the simulation
step!
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- FndSim -
Preferences - Simulation window

II
Memory Range - setting the number of memory words
that will be simulated

enter in the Lower Mem Address, the number of words
in the lower memory address space that should be
simulated.
enter in the Upper Mem Address, the number of words
in the upper memory address space that should be
simulated.
Transport Delay - selecting transport delay mode for line

delays.
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- FndSim -
Preferences - General window
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- FndSim -
Preferences - Power On window

I
Forced State box allows selecting the initial state of the noninitialized internal signals of the models,
Output Waveforms box lets you choose what will be done with
the previous output waveforms
the old waveforms will be deleted during Power On (Delete)
the new waveforms will overwrite the old waveforms
(Overwrite)
old and new waveforms will be compared (Compare)
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- FndSim -
Preferences - Power On window

II
Keep Measurements option preserves the old measurements
after Power On
Keep Comments option preserves the old comments after

Power On
Execute Preset option executes the Selective Preset operation

during Power On
Global Reset option performs global reset operation during

Power On
Model Stabilization option waits till all operations scheduled for

time 0 will be completed
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- FndSim -
Preferences - Reports window
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- FndSim -
Setting Simulation Step

Options -> Simulation Step...
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- FndSim -
Start Long Simulation

Options -> Start Long Simulation...
This windows allows setting and starting long
simulations.
The Simulation Running Time box allows selection of

the simulation time.
Stop button to stop the simulation.

The Start button starts simulation process.
The Cancel button quits the Start Long Simulation
window.
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- FndSim -

with XACTstepTM M1
Simulator Macro Operations
GENERAL I
How to run macro operations
Run Script File
Files > Run Script File...
Edit Script File
Tools > Script File > Edit...
Run Script File step by step
Tools > Script File > Single Step Mode
Interactive
Window > Command
Naming conventions
Component Names - root/U1 (or U1) - Chip U1 at the
root level
Pin Names - B11/B12/U25.Y1
Signal Names - root/RESET (or RESET) - signal
RESET at the root level
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- FndSim -
GENERAL II
Logical states
Bus can expressed in Binary(\B), Octal(\O), Decimal(\D)

and Hexadecimal(\H). They may also be expressed
using their numerical bases, e.g. \2, \8, \16, \20
BUS Signal State
Z
RL
RH
RX
L
H
X
UL
UH
CX
R
V
SL
SV
SX
Description
HI_Z
RES_LOW
RES_HIGH
RES_X
LOW
HIGH
UNKN_X
UA_LOW
A_HIGH
CONF_X
REF_V
HIGH_V
SV_LOW
SV_HIGH
SV_X
Time Units - ps, ns, us, ms ,s ,m ,h

default : 0.1ns
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- FndSim -
Viewsim Compatible macros I
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Comments: |
high (h): high U2.input
watch (w): watch rst clr enable

vector (v): vector Data d0 d1 ad[0:4]
assign: assign ADBUS1 AB03\H
assign DATA data_bus.dat
low (l): low U12.output
Force Unknown: x U21.input
stepsize (step): stepsize 15ns
clock (ck): clock c 0 1 0 1 1 0 0 1
cycle (c): cycle 5
sim: sim 53ns; sim (a single short STEP)
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- FndSim -
Viewsim Compatible macros II

Macro (Command) Loop:
(assign A a.dat; assign B b.dat; sim)*12
SETUP Radix: bin, oct, dec, hex

radix dec Data_In
restart (Power-on operation)

SETUP Wfm:
wfm D0 @0=0 @1000=1 @2000=Z @3000=0
wfm A5 @0=H (1000=L 2000=H)*10
wfm Data0 events.dat
wfm DATA @0=FF\H (1000=dec by 2)*8
inc, div, mult, rl(rotate left), rr(rotate right),
sl(shift left), sr(shift right)
echo any text free of semicolon and new lines:

echo Start execution of memory test macro
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- FndSim -
Test Vectors
Test Vector File Example:
Command File Example:
| ab.dat test vector file

| test vectors for buses A i B
|
| format
| A[0:7]
| B[0:3]
10101101 | binary value
2\D | decimal value of 2;
| uses four lines B[0:3]
|
AB\H | hexadecimal value of AB
0111
|
10001111
Z
|
Assign A ab.dat | assigns the first data (10101101) from ab.dat to the A bus
Assign B ab.dat | assigns the second data (2\D) from ab.dat to the B bus
sim | simulates the assigned bus values
Assign A ab.dat (AB\H) | assigns the 3rd data from ab.dat file
Assign B ab.dat (0111) | assigns the 4th data from ab.dat file
sim
Assign A ab.dat (10001111)
Assign B ab.dat (Z)
sim
|The Assign macro automatically loads the consecutive data from
| the ab. dat file.
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Event File Example:

@0 = 0\H (hexadecimal)
@100 = 1\H
@200 = Z
@300 = A\H
- FndSim -
Example Command File

restart
vector SW sw7\sw6_p sw7\sw5_p sw7\sw4_p sw7\sw3_p sw7\sw2_p sw7\sw1_p
+sw7\sw0_p
vector ALU alu[3:0]
vector STACK stack[3:0]
radix hex SW ALU
radix bin STACK
watch clk SW exc_p ALU STACK we rst
clock clk 0 1
| Use a clock period of 100ns. Set stepsize=50ns
step 50ns
h exc_p
l gsr
assign SW 00\h
sim 1000
h gsr
assign SW 61\h
| Viewsim uses units of 0.1 ns, so this statement

| simulates for 100 ns.
sim 1000
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- FndSim -
l exc_p
cycle 2

with XACTstepTM M1
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Breakpoints
Tags
Milestones
Presets
Selective Simulation
Cross Point Probing With The Schematic
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- AnSim -
Breakpoints
A Breakpoint is a software routine that checks
for selected signal conditions in the design.
When these conditions are met, you may

perform some operations
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Stop simulation
Place a marker on the screen
Save test vectors
Load a new test vector file
Modify the existing test vectors using the Append
operation
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- AnSim -
How to Create A Breakpoint I

1) Assign probes to schematic
2) Invoke simulator
3) Select
Tools ->
Breakpoints Editor...
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- AnSim -
How to Create A Breakpoint II

4) Select the bus
5) Enter value on bus that you wish
to detect. (Must be in Hex)
6) To detect the transition to this
value, select ?Edge.
7) You have now declared the mask
that defines Condition 0.
8) Having defined a
Condition, you must
mow define the action to
be taken by the simulator
when that Condition is
met.
Click on Edit
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- AnSim -
How to Create A Breakpoint III

9) Ensure that this is the Condition you
want to edit
10) Select a blank line into which an
action is to be defined.
11) Click on Edit and then select an
Action
12) The Breakpoint Action is now defined
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- AnSim -
How to use a Breakpoint
Load the edited Breakpoint file

File -> Load Breakpoints -> filename
Run the simulation.

If any Breakpoint conditions occur, blue letter marker
will be placed onthe display.
To quickly locate Breakpoints
in a large waveform display,
ensure that this button is set
to Break
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- AnSim -
Use these buttons to jump left and

right to the next Breakpoint in that
location.
Tags
A TAG is a combination or sequence of signals
What is the difference between a TAG and a
Breakpoint
BREAKPOINTS operate whilst a simulation is running.

The are software routines that monitor the simulation
outputs looking for a particular condition. When that
condition is met, they react as instructed.
TAGS are employed whilst the simulation is stopped,
and are a quick and easy way of scrolling through the
waveform looking for a particular condition.
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- AnSim -
How to Create a TAG

1) Select Tools -> Set TAG Conditions...
This enables a second column next to
the signal names. This column shows
the state or transition that each signal
contributes to the TAG.
2) A state editor window is enabled.
3) Select a signal from the Waveform Viewer window
and click on a state in the state Editor Window.
4) To implement a transition, say 1 -> 0,
select the signal
select the High state button
select the same signal
then select the Low state button
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- AnSim -
How to Use a TAG
1) To quickly find a TAG during any stage of a simulation,

click on this button to until it shows TAG
Note that the current time of the
simulation is marked in red,
and the TAG cursor that scrolls
around the screen is in blue
2) Use these button to jump left or right between TAGd events.

The screen will jump to a blue cursor that marks the TAGd event.
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- AnSim -
Milestones
A milestone is used to store the complete
design status that exists at a selected

simulation cycle. This includes the timing at
the current simulation cycle, and all internal
registers, memories and flags etc., of all IC
models.
Milestones allow extensive design analysis.

Re-simulate a modified design from a selected
milestone
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- AnSim -
How to Create a Milestone I

Options -> Milestones...
Active Milestones
All active (saved) milestones are listed in this area.
Click Save to manually save the current design data as
a milestone.
Select a milestone and click Load to return to the
previously saved design state.
Click Delete to remove the selected milestone from the
memory.
Click Delete All to remove all milestones.
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- AnSim -
How to Create a Milestone II

Automatic Milestones.
Milestones can be saved automatically. To set
automatic milestones:
enter the period (time) between saved milestones
in the Period box,
select the maximum number of remembered
milestones in the Number field. Additional
milestones will override the previously saved ones,
forming a moving window of saved milestones.
select the On option.
Breakpoint Milestones.
Milestones can be generated by breakpoints. The
Number list box allows selecting the maximum number
of milestones that can be saved under control of
breakpoints.
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- AnSim -
Presets
The simulator allows any signal or device pin
to be preset to any logical state.
The main use is to test for some design
situation that is difficult to generate, or for a

design situation that takes a very long
simulation time to create.
e.g., the end of count sequence on a 64 bit counter
takes .. a large number of cycles!
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- AnSim -
How to define a Preset I

Select Tools -> Selective Preset
This window pops up and you
define the presets as followed
1) Click on Add in the
Selective Preset window
2) Highlight nodes in
this window
3) Click on Add
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- AnSim -
How to define a Preset II

4) Nodes transferred to here
5) Select Edit
6) Enter state for each signal.
Then select close.
7) Use Save and Load to choose between

Preset groups.
8) Use Execute to run the preset.
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- AnSim -
Selective Simulation
Running a large design for a long simulation
period can produce... long simulation times!
Why should the simulator engage in
calculating the status of nodes that are of no

interest during this particular simulation run?
Selective simulation allows the user to search
through the design netlist clicking on icons

that represent hierarchical blocks in the
design. These parts of the design are closed
down in the simulation model and their outputs
forced to Hi-Z state. Reducing the number of
active nodes in this manner results in faster
simulation times.
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- AnSim -
Invoking Selective Simulation

1) Select Waveform Viewer
Options -> Selective Simulation.
Note that in any given hierarchical level, the components

are symbolized
as chips
2) To disable a
component,
click on the chip icon,
and it will change color
from gray to white.
3) The outputs of selected

components now assume a
Hi-Z state in the simulation
model, and this is reflected
on the schematic
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disabled
active
4) click on close ...its as easy as that
- AnSim -
Cross Point Probing
The status of all probed signals will

back annotated to the schematic
window and the various logic states,
represented with different colors.
Using these buttons, one can

advance or retard the simulator
through one clock transition.
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- AnSim -

with XACTstepTM M1
XACTstep M1 Software Flow
Design Flow Overview

User Interface
Command lines
Graphical User Interface
Very similar to XACT 6.0 GUIs
Built upon the new M1 core tools
Core Tool Capabilities

Industries most robust Timing Constraint language
Check-point methodolgies
XACT Design File Compatibility
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- M1Flow -
Logical Design Files

Logical Design Files describe your design, and
are composed of logical components
Typically a netlist, generated by Schematic Capture or

Synthesis
Composed of Boolean Gates, FIFOs, RAMs
Netlist input to XACT-Step M1 is in EDIF format

XNF files are also accepted
EDIF format files are translated to (Native

Generic Design) NGD format
NGD files have varying extensions

Ex: NGD, NGM, NGA, NGO
NGD files can be translated to other formats

for simulation
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- M1Flow -
Notes on Logical Design Files

In XACT-Step M1, Logical Design Files are
NGDs
These replace the various X?F files of XACT

XFF, XTF, XG, etc
NGD Files:
Native Generic Design (NGD)
Have varying extensions
NGD, NGM, NGA, NGO, etc.
Logical design netlisting tools work with each of these
files
ngd2edif, ngd2ver, ngd2vhdl
(ngd2xnf is included with M1, but will be obsoleted in
M2)
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- M1Flow -
Physical Design Files

Physical design files are composed of
components found in a Xilinx FPGA such as

look-up tables and flip-flops
Physical design files have .ncd extension
Map creates an NCD file from an NGD file
NCD files contain varying pieces of information
Mapping, placement, and routing tools each
concatenate data to the bottom of the NCD file
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- M1Flow -
Notes on Physical Design Files

In XACT-Step M1, Physical Design Files are
NCDs
These replace the LCA files of XACT
NCD Files:
Native Circuit Design (NCD)
all physical design files have an NCD extension
NCD files contain varying degrees of information
Mapping information only
(refered to as partitioning in XACT)
Mapping, Placement and Routing information
All physical design tools will work with these files:

par, trce, epic, ngdanno, drc, ncdconv
map creates an NCD file from an NGD file
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- M1Flow -
What are the new commands?

Implementation commands:
ngdbuild <design_name>
map <design_name>
par <design_name> <routed_name>
bitgen <routed_name>
Analysis Commands:
trce <design_name>
ngdanno <design_name>
ngd2??? <design_name> (where???= EDIF, VER,
VHDL)
Compatability Commands:
lca2ncd
csttrans
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- M1Flow -
BEL and Comp Terminology

XACTstep M1 uses two new terms for FPGA resources:
Comps and Bels
A comp may refer to a CLB, IOB, TBUF, or Decoder
A BEL may refer to the contents of a comp, such as FLUT, H-LUT, FFX, FFY, RAM, or PAD
The Graphic Design Editor (EPIC), and TRCE timing

reports will refer to BELS
FFX
G_LUT
H_LUT
F_LUT
FFY
4000E CLB
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- M1Flow -
The COMP
shown here is a
CLB, which
contains BELS:
F_LUT, G_LUT,
H_LUT, FFX, and
FFY
.XNF or EDIF netlist
UCF
User Constraint File
NGDBUILD
Flatten Hierarchical Design
XACT-M1
Design Flow
.NGD
MAP
Logical to Physical translation
Groups LUTs and FFs Into CLBs
.NCD
.PCF
TRCE
Static Timing Estimates
TRCE
Static Timing Analysis
PAR
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BITGEN
Layout of Physical Design

Routes Physical Design
Generates configuration file
.NCD
.BIT
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- M1Flow -
Design Flow Programs

NGDBUILD
Merges hierarchical EDIF or XNF files into one
hierarchical file
Creates internal netlist .ngd(Native Generic Design)
files
Contains logical components: combinatorial gates,
RAMS, flip-flops, etc.
MAP
Maps logical components to physical components
found in Xilinx FPGA: look up tables, Flip-Flops, three
state buffers, etc.
Packs physical components into COMPS
Creates internal .ncd (Native Circuit Design) file
TRCE
Analyzes Timing
Use before PAR to analyze constraints
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- M1Flow -
Design Flow Programs

PAR
Places COMPS on FPGA
Routes the FPGA
TRCE
Analyzes Timing
Use after PAR to check delays
NGDANNO
Back-annotate timing delays for Simulation
BITGEN
Create file to configure FPGA
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- M1Flow -
Begin the Design Manager

In Project Manager, click XACTstep icon
Command Line : dsgnmgr.exe
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- M1Flow -
Begin the Design

Implementation
Select Design -> Implement
or click on the Right arrow
Select Part
You can select options (...see later foil)

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- M1Flow -
Report Browser
Automatically opens with the run-only Flow
Engine
Reports are shown once available

Double-click to open
Yellow sparkles indicates new (not yet read)
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- M1Flow -
Key Report Files

Place & Route Report includes resource
summary
Indicates the percentage of utilization

The number of I/O and flip-flops is specified
Reports if the design routed
Gives an overall design score
Post Layout Timing Report provides timing

summary
If timing constraints were specified, the report indicates

if they were met
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- M1Flow -

with XACTstepTM M1
M1 Implementation Options
Design Translation Flow Chart

EDIF
LogiBlox
EDIF
NCF
EDIF2NGD
EDIF2NGD
NGO
NGO
NGO
NGDBUILD
UCF
Logical DRC
Check-point
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- M1Imp -
NGD
NGDBUILD :
The Design Translation Control
Center
What NGDBUILD does
Translation of logical design (netlist) to Xilinx internal
netlist (NGD)
Merges multiple design netlist files which make up a
design into an NGD file for use by map
User constraints are also included in the NGD file
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- M1Imp -
Design Mapping Flow Chart
Optional Guide Files

Optional Constraint File
NCD
MDF
NGD
MAP
NCD
PCF
NGM
MDF
MRP
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- M1Imp -
PCF
Timing
Check-point
Functions of MAP
MAP transforms a logic design into an
equivalent physical implementation
Map re-configures your design in terms of FPGAs

logic resources.
MAP creates a physical constraint file (PCF)

which contains all of the design constraint
data applied through design translation.
MAP creates the NGM file which correlates the

logic design to its physical implementation facilitating Back-annotation.
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- M1Imp -
Main Implementation Menu

Options
Guide Option
Use a previous
implementation as
template for current
implementation
Specify constraint
file (optional)
MAP, PAR, and
configuration options
Implementation
has four sub-menus:
Optimize and Map,
Place and Route,
Timing, and
Interface
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- M1Imp -
Optimization and Map Options

Map optimizes your design before it is partitioned into
LUTs, Flip-Flops,etc. The GUI includes these options:
Trim Unconnected
Signals (default is On)

Trims all fan-out/fanin from unconnected
pins
Turn off to implement
hierarchical blocks
separately
Replicate Logic (default
is on)
Duplicates logic with
high fan-out
Increases utilization,
decreases delay
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- M1Imp -
Optimization and Map Options

Optimization Strategy (default is Off)
Minimizes logic to optimize logic for speed, area, or
both
Synthesized designs have been optimized already
Packing Strategy (default is minimum density)

Informs Map of how to pack COMPS with logic
Minimum Density - Map only puts related logic into the
same COMP
Fit Device - packs components more tightly into
COMPS
Can adversely affect timing and routability
Generate 5-I/P Functions

Reduces block levels but increases area
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- M1Imp -
Place and Route Flow Chart

Optional Guide File
NCD
NCD
PCF
PAR
Single-PAR run
Multi-PAR run
PAR
DIR
NCD
PAR
NCD
PAR
NCD
PAR
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- M1Imp -
NCD
PAR
NCD
PAR
What PAR Does

Places the COMPs within an NCD based on:
guided design requirements

location constraints (within the PCF file)
the designs structure
estimate of the routing delays for each layout
Routes the signals within an NCD based on:

guided design requirements
available slack for each signal (from Tspecs)
Performs Clean-up routing passes

to reduce design score
to reduce (all) net delays
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- M1Imp -
Place and Route Options I

Runtime (default is 4)
Trades off placement
effort verses CPU time
Router Passes (default
is Auto)
The Router will run
until no improvement is
made to meet timing
constraints.
Set Router passes to
avoid very long run
times for difficult designs
Start with 5 passes
for 4000EX/XL chips, 7
passes for 4000E chips
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- M1Imp -
Utilities -> Template Manager -> Edit

Implementation Template -> Place and
Route
Place and Route Options II

Delay Based Clean-up Passes
Use this option to further route an already routed
design.
The router makes routing decisions based on computed
delay times between sources and loads on the routed
nets, and reroutes to minimize the delays. This option is
useful if you want to manually route a portion of the
design and then automatically route the design or if you
want to run additional delay reduction passes.
Set the number of delay-based cleanup passes from 1
to 5. The default is 0.
Use Timing Constraints During Place and Route

Select this option to use timing constraints in the design
file to place and route the design within the specified
constraints.
By default, this option is on.
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- M1Imp -
Implementation Options for Fast

Runtime versus PAR Effort
Select fast placement option,

1-2 routing passes, 0 clean-up
passes, and deselect
Use Timing Constraints
Deselect these 3 checkboxes

Other hints:
- 4KX and 9500 families give fastest runtimes.
- Save this as an implementation template
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- M1Imp -
Timing Report Options

Enable the creation of the
Timing Report
Logic Level Timing
Report is created
before PAR
Has zero net delays
Used to analyze
constraints
Post Layout Timing
Report is created after
PAR
Verify that the
design meets
constraints
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- M1Imp -
Timing Report Delays

Timing reports generated on a mapped design use 0ns
delays for nets
Post-route timing reports use actual delays based on

placement and routing
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- M1Imp -
Controlling the Back Annotation

Netlist Format
Format options:
- VHDL
- Verilog
- XNF
- EDIF
EDIF formats:
- Standard (2.0.0)
- Viewlogic
- Mentor EDIF
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- M1Imp -
FPGA Multi-Pass Place & Route I

Design -> FPGA Multi-Pass Place & Route
Starting Strategy
Specify a placement initialization value with which to
begin the place and route attempts.
Each subsequent attempt is assigned an incremental
value based on the starting strategy value.
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- M1Imp -
FPGA Multi-Pass Place & Route

II
The number you choose corresponds to a cost table
index and results in different place and route strategies.
Cost tables assign weighted values to relevant factors
such as constraints specified in the input file (for
example, certain components must be in certain
locations), the length of connections, and the available
routing resources.
Choose a number from 1 to 100. The default is 1.
Iterations to Attempt
Specify the number of place and route iterations to
attempt. Choose a number from 1 to 100. The default is
1.
Iterations to Save
Specify the number of place and route iterations to
save.
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- M1Imp -
FPGA Multi-Pass Place & Route

III
Choose a number from 1 to 100. The default is 1.
This option compares every result to every other result
and leaves you with the best iteration attempts.
The best outputs are determined by a score assigned to
each output design.
The lower the score, the better the design.
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- M1Imp -
How to Start and Stop the XACT

GUI
Select Flow Engine -> Setup Advanced to
select the starting state
Select Flow Engine -> Setup -> Stop After to

set stopping point
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- M1Imp -
Create a Script from the GUI

XACT can create a script file from the GUI
session
Available from the Flow Engine or Design Manager

Select Utilities -> Command History -> Command Line
Select Utilities -> Project Notes
Copy, paste, and save text from Command History
Window
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- M1Imp -
Sample Script File

The script file below was created from the
Command History command
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- M1Imp -
The Guide Option

Allows use of a previously placed and routed
design to guide a new placement
Useful if there are few design changes
Guide is used for Map, Place, and Route

Map may take longer to execute, but PAR will be faster
CIC
Previous
Design
New Design
Place & Route
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- M1Imp -
Incremental Design Support

When using incremental design, unconnected
pins will be present
By default, Xilinx removes fan-in and/or fan-out

of unused pins
So, disable the Trim Unconnected Signals

option
Located at Setup -> Options -> Optimize and Map
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- M1Imp -
Effective use of Guide

Guide uses signal and component names to
determine edited parts of the design
Name all nets

Do not change names
Minimize changes to the design

Any new hierarchy changes all names below
Avoid any changes to synthesized logic
Synthesis users: please try to freeze the

design with set_dont_touch or like
command
Otherwise, guide option may not be useful
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- M1Imp -

with XACTstepTM M1
Timing Analyzer
Timing Analyzer
Analyze delays before and after
implementation
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- Timing -
Timing Analyzer Benefits

Combines block delays from data book with
net delays from implementation files
Quickly identifies critical paths and timing

hazards
Report shows all elements in path, each

element's delay, and cumulative delay
Can determine if slow paths are due to block delays

(design) or net delays (implementation)
IOB
I F1
CLB1
X F3
DQ
CLB2
block net block net block
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- Timing -
Element
PAD to IOB.I
IOB.I to CLB1.F1
CLB1.F1 to CLB1.X
CLB1.X to CLB2.F3
CLB2.F3 to Clock
Delay
2.2
1.1
2.7
1.2
2.1
Total
2.2 block
3.3 net
6.0 block
7.2 net
9.3 block
Basic Path Type - Clock to Setup I

A clock-to-setup (C2S) path starts at the Q
output of a flip-flop or latch and ends at an

input to another flip-flop, latch, or RAM, where
that pin has a setup requirement before a
clocking signal.
It includes
the clock-to-Q delay of a flip-flop,
the path delay from that flip-flop to the next flip-flop,
the setup requirement of the next flip-flop.
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- Timing -
Basic Path Type - Clock to Setup II
Same Clock
Rising to Falling Edge
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- Timing -
Basic Path Type - Clock to Setup III
Falling to Rising Edge
Diffent Clocks
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- Timing -
Basic Path Type - Clock to Pad

A clock-to-pad (C2P) path starts at the Q
output of a flip-flop or latch and ends at an

output of the chip.
It includes
the clock-to-Q delay of the flip-flop
the path delay from that flip-flop to the chip output.
The clock-to-pad path time is the maximum
time required for the data to leave the source

flip-flop, travel through logic and routing, and
leave the chip.
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- Timing -
Basic Path Type -
Pad to Setup
A pad-to-setup (P2S) path starts at an input of

the chip and ends at an input to a flip-flop,
latch, or RAM
The pad-to-setup path time is the maximum
time required for the data to enter the chip,

travel through logic and routing, and arrive at
the output before the clock or control signal
arrives.
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- Timing -
Basic Path Type -
Pad to Pad
A pad-to-pad (P2P) path starts at an input of

the chip and ends at an output of the chip.
The pad-to-pad path time is the maximum time

required for the data to enter the chip, travel
through logic and routing, and leave the chip.
It is not controlled or affected by any clock

signal.
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- Timing -
Basic Path Type -
Clock Input
A clock input path starts at either an input of
the chip or at the outputof a flip-flop, latch, or

RAM. It ends at any clock pin on a flip-flip
orlatch enable.
The clock input path time is the maximum time

required for the signal to arrive at the flip-flop
clock input.
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- Timing -
Basic Path Type -
Clock Skew I
Clock skew is the difference in arrival time for

clocks that are on the same clock net.
When the destination is clocked before the
source, the clock skew is called negative clock

skew.
Negative clock skew means that the clock period must
be longer than the path delay plus the amount of clock
skew between the flip-flops.
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- Timing -
Basic Path Type -
Clock Skew II
When the source is clocked first, the clock

skew is called positive clock skew.
Positive clock skew means that the clock period could

be shorter than the path delay by the minimum amount
of clock skew.
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- Timing -
Invoking Timing Analyzer

Double-click icon in Design Manager Toolbox
Toolbar buttons
Performance to TimeSpec (?TS)
Shows XACT-Performance specs and details for
each controlled path
Design Performance Summary (?MHZ)
Shows worst-case delays of each path type
Detailed Analysis (?ALL)
Shows all paths
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- Timing -
Use Filters to Specify Paths to

Report
Need to limit report file to paths of interest
Can specify by source/destination, type, or
included/excluded nets
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- Timing -
Limiting Paths by
Sources/Destinations
Can be Flip-Flops, Pads, Nets, Pins, CLBs,
Clocks, or All
Then select specfic

elements from list
Defaults to All
Select << to
delete All before
selecting specific
items
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- Timing -
Limiting Paths by Nets They

Contain
Can select paths by nets to include/exclude
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- Timing -
Control Path Tracing

Specifies Timing Analyzer path tracing.
Path Type
Asynchronous Set/Reset to output
Data to output for transparent latch
RAM data to output
RAM WE to output
TBUF tristate control to output
TBUF input to output
I/O pad to input
I/O tristate control to pad
Bidirectional tristate I/O output to input
I/O output to pad
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- Timing -
Default
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
XACT-Performance Filters
Report Paths Failing TimeSpec only lists paths
that dont meet TIMESPECs
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- Timing -
Report Options
Summary Report Only
Generates a summary report containing only the path
source and end point.
Lists one delay path per line and does not display
cumulative delays through CLBs.
Applies only to FPGAs.
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- Timing -
Report Options
Maximum Paths per Timing Constraint
Sets the limit for the number of paths reported per
timing constraint.
For FPGAs, the default is one path reported per timing
constraint.
For CPLDs, the default is unlimited.
Not specifying a value is equivalent to "no limit."
Wide Report
Creates a report formatted into 132 characters per line,
If not selected, a "normal" report (80 characters per
line) is generated.
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- Timing -
Recommended Verification
Flow
Netlist
FUNCTIONAL SIMULATION
Implement
TIMING SIMULATION
Timing Analysis
Bitgen
Prom File Formatter
Download
IN-CIRCUIT VERIFICATION
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- Timing -

with XACTstepTM M1
Design Constraints
Brief Review of Constraint Flow

LOGICAL DOMAIN
EDIF
.ucf
.ncf
User netlist
and logical
constraints
NGDBUILD
DESIGN
TRANSLATION
MAP
PHYSICAL
DOMAIN
PAR
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- UCF -
Mapped design
and physical
constraints
.pcf
.ncd
TRCE
EPIC
NGDANNO
DRC
Types of Constraints
Constraint commands define the maximum
allowable delay or placement along paths
Constraints control XACT tools during

implementation
Timing and location constraints can be
specified in schematic or user constraint (UCF)

file
Some synthesis tools create a NCF file for constraints
Location Constraints
Specify location of components on FPGA
Timing Constraints
Specify maximum allowable delay along logic paths
Allows both quick and dirty and highly detailed timing
control.
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- UCF -
Logical Location Constraints

Absolute Location constraints place a
component at a specific site on the FPGA
Example:
INST U45 LOC = CLB_R1C5;
Occupies Row 1, Column 5 in the FPGA
Relative (RLOC) location constraints specify

the relative placement of components within a
macro
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- UCF -
Absolute Location Constraints in

the Logical Domain
LOC constraint used to locate:
BUFTs, FFs, MAPs, CLBs, PADs, WANDs, decoders,
global buffers
Syntax:
single components (e.g. CLBs)
INST U45 LOC=CLB_R1C5;
ranges of components (but not IOs)
INST U46 LOC=CLB_R2C2:CLB_R4C6;
multiple sites for single component
INST U50 LOC=CLB_R1C1; CLB_R2C1;
INST /top/ddf LOC=CLB_R*C2;
Pin assignments use similar syntax:
INST QOUT<3> = P32;
NET outa = P18;
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- UCF -
Relative Location (RLOC)

Constraints
The following symbols (primitives) accept
RLOCs.
Registers, FMAP, HMAP, F5MAP, CY4, CY_MUX,

ROM, RAM, RAMS, RAMD, BUFT, WAND primitives
that do not have a DECODE attribute attached
Guidelines for Specifying Relative Locations

RLOC=RmCn [.extension]
INST xcv/U0 RLOC=R0C0;
INST xcv/U1 RLOC=R1C0;
RLOC_RANGE=Rm1Cn1:Rm2Cn2
INST xcv/U2 RLOC_RANGE=R2C0:R4C2;
Site of upper left hand corner of pre-placed macro
INST xcv RLOC_ORIGIN=CLB_R5C4;
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- UCF -
Physical Constraints
XACT translates the your contraints (from
schematic and UCF file) into a physical
constraint (PCF) file.
You may edit this file, but it is not

recommended
Edits are not annotated back to schematic or UCF file

PCF file is not user friendly
For more information on PCF files and
physical constraints, see the appendix in the

back of this chapter
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- UCF -
Path Types
Timing constraints are applied to logic paths
Logic paths typically start and stop at pads,
registers, latches, and RAM
M1 recognizes the following keywords to

define endpoints:
PADS
FFS
LATCHES
RAMS
All I/O pads

All flip-flops
All latches
All RAM elements
Keywords are also known as pre-defined

groups
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- UCF -
Global Constraint Definition

Global constraints apply to every path of a
given type in your design, and use pre-defined

groups
Syntax:
TIMESPEC NAME = FROM: ENDPOINT:TO: ENDPOINT: Value;
Rule of Thumb: Use UPPERCASE characters

for timespec commands
Example:
TIMESPEC TS_01 = FROM : FFS: TO : FFS : 30;
TS_01 will constrain all flip-flop to flip-flop paths in your
design to 30 ns
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- UCF -
Global Constraint Example

TIMESPEC command using predefined groups:
TIMESPEC TS_01 = FROM : FFS : TO : FFS : 30;
TIMESPEC TS_02 = FROM : PADS : TO : FFS : 25;
TIMESPEC TS_03 = FROM : PADS : TO : PADS :26;
TIMESPEC TS_04 = FROM : FFS : TO : PADS : 9;
TS_02
FF1
TS_04
TS_01
FF2
CLK
1 Level of Logic
2 Levels of Logic
Z<0:9>
TS_04
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TS_03
- UCF -
OUT1
OUT2
Global Constraint Example

Consider TS_04 from the previous page:
TIMESPEC TS_04 = FROM : FFS : TO : PADS : 9;
TS_04 is applied to FF2 - OUT1 and FF2 - OUT2

Is the FF2-OUT2 path constraint realistic?
Is there a similar problem for another path?
9 ns
X
FF1
CLK
FF2
1 Level of Logic
2 Levels of Logic
Z<0:9>
9 ns
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- UCF -
OUT1
OUT2
Path Specific Constraints

Most path-specific constraints use a similar
syntax as global constraints
Except that endpoints are user defined groups
Path-specific endpoints may be:
Components, pins, nets, primitives, or macros

Groups of components, pins, etc.
Subsets of pre-defined groups
Subsets of sub-groups
Period constraints are used to constrain
groups of flip-flops driven by one clock signal
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- UCF -
Group Subsets I
Subsets of pre-defined groups will pathspecific constraints:
Example:
Instance FIFORAM drives a bank of registers
TIMESPEC TS_FIFOS = FROM : RAMS(FIFORAM) : TO : FFS(MY_REG*) : 25;
MY_REG_00
FIFORAM
DATA PATH
MY_REG_01
YOUR_REG_00
YOUR_REG_01
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- UCF -
Group Subsets II
You can create subgroups based on names
with EXCEPT
Example: Create a group of Flip-Flops containing

YOUR_REG_00 and YOUR_REG_01
TIMEGRP MY_REG = FFS: EXCEPT (YOUR*);
MY_REG_00
FIFORAM
DATA PATH
MY_REG_01
YOUR_REG_00
YOUR_REG_01
All Flip-Flops in the design will be included, except for

Flip-Flops with nameYOUR
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- UCF -
Forward Tracing
Assign constraints to a net
Constraint is applied to all endpoints driven by
the net
Example:
NET DATA0 TNM = MYBUS;
TIMESPEC TS_MYBUS = FROM : FFS(CNT25) : TO : MYBUS : 30;
TS_MYBUS
MY_REG_00
DATA0
CNT25
DATA PATH
...
MY_REG_01
MY_REG_15
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- UCF -
Constraining clocks
Clock period is constrained with the FFS: TO :
FFS constraint
You can also define a clock period based on

the clock signal; for example:
PERIOD = 40: HIGH: 25 (attached to a net in

Schematic), or
NET A_CLK TS_COUNTER= PERIOD:40: HIGH:25;
(UCF file)
25ns
40ns
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- UCF -
Use of THRU Points

Allows definition of intermediate points on a
path
Example:
The TPTHRU attribute is attached to
net/instance/macro in top blob.
TIMESPEC TS_FIFOS = FROM : RAMS(FIFORAM) : THRU : ABC : TO : FFS(MY_REG*) : 25;
my_reg00
fiforam
TPTHRU=abc
my_reg01
my_reg02
my_reg03
THRU points can also be defined directly in the .ucf, e.g.:
fe
NET $3M17/ON_THE_WAY TPTHRU = ABC;
CIC
- UCF -
Use of SYNC Points

Allows definition of synchronous points that
are not FFS, RAMS, PADS or LATCHES.
Commonly used with three-state buffers.
Example:
TIMESPEC TS_1A = FROM : FFS : TO : BLUE_S : 15 ;
my_regA
D
CLK
comb _a
$3M17/BLUE
comb_b
TPSYNC = BLUE_S
RAM/
FFS/
PADS/
LATCH
SYNC points can also be defined directly in the .ucf, e.g.:

NET $3M17/BLUE TPSYNC = BLUE_S;
The constraint applies to the path from my_regA to the inputs

of the combinational logic.
How is this different from TNM?
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- UCF -
Ignoring Paths
Informs XACT to ignore a path through a net
for specific timing specifications
In the UCF file, use TIG to tell XACT to ignore a path.

In a schematic, simply attach TIG to net
Example:
Assume that TS_GENERAL and TS_FASTER would
ordinarily cover paths through net $I67/MAYBE_SLOW
A UCF constraint could be written:
NET : $I67/MAYBE_SLOW : TIG = TS_GENERAL; TS_FASTER;
Here, $I67/MAYBE_SLOW, could then be covered by

some other, more relaxed timespec.
This is sometimes referred to as a slow

exception.
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- UCF -
Creating Path-Specific Groups

Create a group of elements with the TNM
command
What elements may be grouped together?
Create groups from existing groups with the

TIMEGRP command
Assign constraints using groups with a

TIMESPEC command
Essentially the same method as used in XACT

5.2/6.0
Allows the use of existing schematics for 4KE FPGAs

and constraint files translated with CSTTRANS.
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- UCF -
Constraint Entry in UCF file

UCF is used for the TOP level logic design file
These are annotated into an NGD during NGDBUILD
Constraints must reference full hierarchical path
Example:
See previous page
Identical function to the schematic entry example
Enter TNM, TIMEGRP, and TIMESPEC commands in
the UCF file
NET CLKEN TNM=GRP1;
NET FF2GATEA TNM=ABC;
NET FF2GATEB TNM=XYZ;
TIMESPEC TS01=FROM : GRP1 : TO : PADS : 20NS;
TIMESPEC TS02=FROM : XYZ : TO : OUT2 : 6 NS;
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- UCF -
Constraint Priority I
It is legal to constrain the same paths more
than once
Known as a constraint conflict

Multiple sources constraining the same path
UCF and schematic could constrain same path
Multiple constraints on one net within one source
Resolution of conflicting constraints from

multiple sources:
Lowest Priority
- input netlist or .ncf file

- .ucf file
Highest Priority
- .pcf file (usually from MAP)
Note: this priority only applies to timespecs with identical
TSidentfiers (e.g. TS_03 =)
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- UCF -
Constraint Priority II
Within a pariticular source:
Highest Priority - Timing ignores (TIG)
- FROM:THRU:TO specs
- FROM:TO specs
- PERIOD specs
Lowest Priority - Allpaths type specs (.pcf only)
You can explicitly assign priorities

Syntax
(SOME_NORMAL_TIMESPEC) : PRIORITY : integer
Low numbers specify high priority

Example:
TIMESPEC TS01 = FROM : A : TO : B : 40 : PRIORITY : 3;
TIMESPEC TS02 = FROM : C : TO : D : 35 : PRIORITY : 2;
Note that while TS02 has higher priority than TS01, it

can never have priority over a FROM:THRU: SPEC
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- UCF -
Constraint Recommendations
Do not use the same TIMESPEC name for more
than one path. BAD Example:
TIMESPEC TS01: FROM X TO Y 20;

TIMESPEC TS01: FROM E TO F 30;
Keep constraints in one source

Either UCF file or in schematics, but not both
OVER-constraining your design is bad news!

Design Performance suffers
Critical timing paths get the best placement and
fastest routing options
As the number of critical paths increases, routability
decreases
Run times increase
Reference - Libraries Guide Chapter 13

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- UCF -
Physical Constraint Appendix

Physical Constraints and Physical Constraint
files
You will find this information helpful when
viewing a timing report or viewing your design

with EPIC.
You may edit the physical constraint (PCF) file,

but it is not recommended
Syntax is not user friendly

Changes are not annotated to schematic, HDL code, or
UCF file.
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- UCF -
Location Constraints in the

Physical Domain
Location constraints are mapped into
Physical Constraints within the PCF file
Refer to physical components - so you must
understand the physical implementation of the

design in order to edit the PCF file manually.
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- UCF -
The .pcf File - Quick Overview

Contains constraints that apply to physical
components rather than elements in the
source netlist (ANDs, ORs, etc)
All TIMESPECs refer to TIMEGRPs (except for

PERIOD constraints).
Must define TIMEGRPs before using them. (Singlepass parser).
Has global constructs (ALL CLOCKNETS, ALL
PATHS, ALL NETS) that do not exist in .ucf/.ncf

world. Can be convenient, but can also easily
lead to overly-constrained designs.
In .pcf, if multiple constraints apply to same
paths and have the same inherent priority,

the later entry in the file wins.
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- UCF -
Examples of Physical Location

Constraints
Example 1: LOCATE - physical domains
equivalent of the logical domains LOC
constraint:
COMP MY_COMP LOCATE = SITE CLB_R3C5 ;
COMP MY_COMP LOCATE = SITE CLB_R3C5, CLB_R6C1 ;
Constraints can be modified further with
SOFT attributes to allow placer leeway in

using sites that are different from those
supplied in the constraint.
COMP ABC LOCATE = SOFT SITE CLB_R2C2 ;
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- UCF -

Constraints
Example 2: COMPGRP - creates a group of
components
Analogous to the TIMEGRP mechanism
COMPGRP SIMPLE = COMP $1I47 COMP $1I48 ;
COMPGRP MY_COMPS = COMP ABC COMPGRP SIMPLE
MACRO HIS_MACRO EXCEPT COMP MY_OTHER_COMP ;
Example 3: LOCATE COMPGRP or Macro

COMPGRP MY_DATA_BUS LOCATE = SITE TBUF_R6C7.1,
TBUF_R6C7.2,TBUF_R7C7.1, TBUF_R7C7.2 ;
MACRO MYRPM LOCATE = SITE CLB_R1C2 ;
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- UCF -

Constraints
Example 4: LOCK - locks routing of nets so that
re-entrant routing will not change them.
To lock down routing of a specific net:

NET_MUX_SELECT LOCK;
To lock down routing of all currently routed

nets:
ROUTING LOCK;
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- UCF -
Timing Constraints in .pcf file

You can also enter timing constraints manually
into .pcf file
Allows creation of constraints that affect elements in the
physical (mapped) implementation.
Allows relatively fast patching of timespecs:

Remapping is not required to test changes.
Could also involve manual editing of .pcf constraints
that were created by MAP from original netlist or
.ucf/.ncf file timespecs.
NOT the recommended flow:

Syntax of .pcf file isnt very user friendly.
User must understand physical implementation of
circuit (CLBs, IOBs, TBUFs, etc)
Usage of the period constraint in XACT-Step M1 is not
recommended
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- UCF -

with XACTstepTM M1
EPIC
What EPIC does

Create physical design files (NCDs) and
Macros (NMCs)
Modify existing NCDs to apply Floorplanning-like

layout constraints
Perform graphical design analysis
Evaluate mapping through Block Editor
Highlight COMPs by design hierarchy
Evaluate path delays - TRACE is built into EPIC
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performs optional path hilighting
- EPIC -
What EPIC does

Details:
EPIC works on Physical COMPs only - no BEL based
work
PAR and Trace are fully integrated into EPIC
It can perform virtually all of the functions that XDE
supports
arguably faster once you understand how to use
the tool
Includes an EPIC scripting capability
EPIC maintains a LOG file (<design>.epl) while it is
open.
The log file is closed when EPIC is exited normally.
The log file is saved as a .rcv file whenever EPIC
exits abnormally (AKA - crashes). This RCV file
may optionally be run when EPIC is restarted.
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- EPIC -
The EPIC Flow

epic.ini
.ncd
epic.men
optional
customization files
EPIC
design.scr
.ncd
.nmc
design.epl
temp. file
NCD Tools
Trace, PAR, BITGEN
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- EPIC -
MAP
EPIC: Usage and I/O

Usage
From Design Manager : Tools -> EPIC Design Editor
From Design Manager : Tools Icon
epic <design_name> [switches]
Inputs
<design>.ncd ; EPIC in design mode (default)
<design>.nmc ; EPIC in macro mode
Outputs
<design>.ncd ; modified physical design
<design>.pcf ; modified physical constraints file.
Common command line switches

-e ; open EPIC in Edit more (alternatives are -n and r)
-m ; open EPIC in macro mode.
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- EPIC -
EPIC Window
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- EPIC -
Logic Block Editor
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- EPIC -
Using EPIC I
EPIC is built on an Object - Action
paradigm
Select an object, perform an action.
EPIC is able to observe all physical design

objects
List Window (in upper right by default) allows for

selection of any design objects:
NETs
COMPs
Macros
Constraints
EDIT Window also can be used to select these objects
Selection in either fashion is highlighted in both
windows
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- EPIC -
Using EPIC II
EPIC is able to perform most Physical design
actions
Buttons and Hot-keys are commonly used for invoking

actions
Placement, Routing (or automatic PAR)
Trace
DRC
Logic Block Editor
Object attributes:
Constraints
Objects programming
Pull-down menus are also used for invoking actions
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- EPIC -
Constraints
Constraint Generation:
Select Object
Push attr button
Push Show Constraints button
Applicable constraints for type of design object are
displayed in dialog box
Examples of Constraints:
For Nets:
Period, Maxdelay, Lock, Block
For COMPs:
Locate, Block, Offset
For Sites (non-occupied CLBs, IOBs, etc.)
prohibit
For the Design
Period, Lock Routing, Maxskew, Maxdelay NETs /
Paths, penalize ~
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- EPIC -
EPICs Command Language

Command line: type a or x to get a
command line
Highlight a hierarchy
Type: select comp COUNTER/*
Type: hilite -c cyan
Prohibit a group of sites

click on sites
Type: setattr prohibit on
Create a button
button TRACE post trace
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- EPIC -
Manual Editing
Full function editing capabilities
All devices
Placement
Manual, swapping, pin swapping, locate, Automatic
Routing
Manual, assisted, Automatic
Logic
Capability to configure logic cells
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- EPIC -
Graphical Timing Analysis

View Constraints in the list window
Select the desired constraint
Tools menu pulldown for TRACE
Many create a custom button for this function (shown
earlier)
Reporting
Controlled by typical TRACE like controls
-v, -e, limit
Result formats
Highlight the selected path
Timing report within history window
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- EPIC -
EPIC - Macro Hints

Cheating, using MAP
MAP a similar function into an NCD
Save as a Macro
Edit to add necessary Macro I/O
Cheating using Record

Open EPIC in Macro mode
Program 1 COMP in proper configuration
Issue the record -c switch
this writes a script which can be text edited to more
rapidly create an entire macro.
CIC
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- EPIC -

with XACTstepTM M1
Configuration
Bitstream Generator
Runs if Produce Configuration Data selected
(default)
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- Config -
Configuration Options
Configuration Rate
The XC4000 uses an internal configuration clock,
CCLK, when configuring in a master mode. The
configuration rate option allows you to select the rate
for this clock. The following options are available. The
default is Slow.
Slow
Select Slow to set the
configuration clock
rate to 1MHz.
Fast
Select Fast to set the
configuration clock
rate to 8 MHz.
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- Config -
Threshold Levels
Inputs : Default is TTL.
TTL (1.2 V threshold)
specify TTL-compatible inputs.
CMOS (2.5 V threshold)

specify CMOS-compatible inputs.
Outputs : Default is TTL.

TTL
specify TTL-compatible outputs.
CMOS
specify CMOS-compatible outputs.This option is only
available for XC4000E and XC4000EX devices.
Configuration Pins
TD0, M0, M1, M2, Done
Float, Pullup, Pulldown
CIC
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- Config -
Perform CRC During Configuration
This option enables Cyclic Redundancy Checking
(CRC) error checking during configuration.
If enabled, the software calculates a running CRC and
insets a unique four-bit partial check at the end of each
data frame in the configuration bitstream.
If disabled, the device performs a simple check for the
0110 pattern at the end of each frame in the
configuration data. By default, this option is on.
Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to
the binary BIT file.
The RBT file is a text file that contains ASCII 1s and 0s.
These characters represent the actual bits in the
configuration bitstream that are downloaded to the
FPGA. By default, this option is off.
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- Config -
Choose a Configuration Method

Configuration mode selected by control pins M0,
M1, M2
Configuration data can be supplied by:

Memory (e.g. PROM),
incrementing address
Decrementing address
Serial memory (XC17xxx)
Processor (parallel)
Processor and clock
Processor; byte-wide load
External master FPGA
or processor (serial)
CIC
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- Config -
Parallel Master Mode up

Parallel Master Mode down
Serial Master Mode
Peripheral Mode
Synchronous Peripheral
(XC4000/XC5000)
Express Mode
(XC4000EX/XC5000)
Slave Mode
Master Serial Mode

FPGA automatically loads itself from external
serial PROM
Requires one small chip, few connections

Xilinx offers serial PROMs from 18K to 256K
Internal CCLK clocks address counter in the

serial memory
Reset
CIC
Serial
PROM
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- Config -
CCLK
Enable
Data
FPGA
Master Parallel Mode

FPGA automatically loads itself from external
byte-wide PROM
Can use part of existing PROM
Internal CCLK clocks address counter in FPGA

Up from 0 or Down from all 1s, specified by mode
16-18 bit address for large FPGA, or large daisy chain
Data still gets serialized internally (configures

at same rate)
Address
Parallel
PROM
CIC
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- Config -
Enable
Data
FPGA
Peripheral Mode
FPGA loads under microprocessor control as a
peripheral
May not require extra connections if FPGA is

already connected to a processor
Byte of data supplied by external controller

FPGA reads data when Chip Selects and Write
asserted
FPGA Ready/!Busy signal indicates ready for next byte
Data
Write Strobe
Chip Selects
Ready/Busy
CIC
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- Config -
FPGA
Synchronous Peripheral Mode

XC4000/XC5000 only
User generates configuration clock, CCLK
Accepts byte-wide data
Data
CCLK
Ready/Busy
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- Config -
FPGA
Express Mode
XC4000EX/XC5000 only
Only mode that configures in parallel
Byte loaded on each CCLK
CCLK max = 10 MHz
Equivalent to 80 MHz in other modes
Supports daisy chain if all XC5000 Express Mode
Data
CCLK
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- Config -
FPGA
Slave Mode
Simple two-wire interface
FPGA reads one bit of data on each clock
supplied externally
Can be controlled by microprocessor or DMA

controller
Used by XChecker download cable
Data
Microprocessor
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- Config -
CCLK FPGA
Daisy Chain
Can program multiple devices with
independent configurations from one PROM
Control from lead FPGA in daisy chain

Lead FPGA can be in any configuration mode
Following FPGAs must be in slave mode
Automatically created by PROM Formatter

Address
PROM
Control
Data
BITSTREAM1
BITSTREAM2
BITSTREAM3
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DOUT
Lead
FPGA
Data
Clock
BITSTREAM1
- Config -
DIN
DOUT
Data
DIN
DOUT
Slave
FPGA
Slave
FPGA
BITSTREAM2
BITSTREAM3
PROM File Formatter

Translates bitstreams into PROM programmer
files
Supports standard ASCII HEX formats for

programmers
LCA
Intel MCS (MCS)
Motorola Exormax (EXO)
Tektronix Hex (TEK)
Bitstream
BIT
LCA
LCA
Bitstream
Bitstream
BIT
BIT
PROM Formatter
HEX
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- Config -
PROM Formatter Screen

Current revisions bitstream is loaded
automatically
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- Config -
PROM Properties
File -> PROM Properties
PROM File
Format
TEKHEX
MCS-86
EXORmacs
HEX
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Number of
Addresses
(Bytes) *
65 536
1 048 576
16 777 216
No limit
- Config -
AddressRange
Total Number
of Bits
0000:FFFF
00000:FFFFF
000000:FFFFFF
No limit
524 288
8 388 608
134 217 728
No limit
Daisy Chain Creation
CIC
Select Add Data Stream button

Find additional bitstreams using Files
Select bitstream
Select Add Bit File button
fe
- Config -
Tie Off Unused Interconnect

Tie option ties off all unused interconnect to
logic 0
Tie is highly recommended for production

Decreases power consumption by a few mA
Decreases on-chip noise
Use Critical Nets as Last Resort

Select this option to use the nets marked as critical to
complete the tiedown process if necessary. By default,
this option is off.
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- Config -
Consider Configuration Pins in

Design
M0, M1, M2 determine configuration mode
Some can be used as I/O after configuration
CCLK is configuration clock

DONE goes high at end of configuration
PROGRAM can be pulled low to re-start
configuration
LDC is Low During Configuration; could use as

PROM enable
INIT goes high after initial clearing of configuration

Goes back low if CRC error occurs
Avoid contention between configuration and logic

functions
CIC
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- Config -
Configuration Sequence
I/O disabled
HDC=High
LDC=Low
RESET (XC3000)
PROG (XC4/5000)
INIT Signal Low
Power-On
Time Delay
Clear
Configuration
Memory
Configuration
Program Mode
Low on PROGRAM
CIC
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- Config -
StartUp
Operational
Mode
Configuration Debugging
Check VCC and rise time
Check configuration pins and contention
Check for clean connections between FPGA
and source
Watch timing requirements in peripheral and

slave modes
Examine DOUT and CCLK outputs even if not

used
Try XChecker cable or different FPGA

Debug daisy chain one at a time, in sequence
order
Put latest family first
CIC
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- Config -
FPGA Demoboard Layout
CIC
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- Config -
FPGA Demoboard I
One socket for an XC3000 device
8 DIP switches to set up the XC4000 and XC3000 FPGAs
One socket for an XC4000 device

One 17XX socket for each FPGA
An XChecker/Download cable header for each FPGA
Daisy-chain configuration with the XC4000 device at the
head of the chain
16 I/O lines that connect the two FPGAs
An external relaxation oscillator for the XC3000
The XC4000 OSC4 library symbol, uses pin 19 of the
XC4003E to drive the XC3000 TCLKIN on pin 11 of the
XC3020A
The XC4000 OSC4, uses pin 13 to drive the XC3000

alternate clock buffer (BCLKIN) on pin 43
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- Config -
FPGA Demoboard II
8 DIP switches set logic input levels; switch outputs
drive both FPGAs; closing switches drive signals to
logic 1's
Program, Reset, and Spare Pushbutton switches, which

are common to both FPGAs
XC3000 displays that use eight LED bars in one row and
one 7-segment LED, shown in the "FPGA Demonstration

Board Displays" figure
XC4000 displays that use eight LED bars in one row and
two 7-segment LEDs, shown in the "FPGA
Demonstration Board Displays" figure
Space for an optional +5 V regulator for battery

operation
Space for an optional crystal oscillator

Headers for FPGA probe points
Prototype area on PC board
CIC
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- Config -
Configuring the XC4003E from

the XChecker/Download Cable
Switch
SW1
SW1
SW1
SW1
SW1
SW1
SW1
SW1
CIC
Name
INP
MPE
SPE
M0
M1
M2
MCLK
DOUT
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Position
X
X
X
X
X
X
OFF
OFF
- Config -
Switch
SW2
SW2
SW2
SW2
SW2
SW2
SW2
SW2
Name
PWR
MPE
SPE
M0
M1
M2
RST
INIT
Position
X
OFF
OFF
ON
ON
ON
X
OFF
FPGA Board General

Components
RESET Pushbutton (SW4)
When you press the RESET pushbutton it can apply an
active-Low Reset signal to the FPGAs and
configuration PROMs, depending on how the Reset
signal routing is configured.
SPARE Pushbutton (SW5)

The SPARE pushbutton applies an active-Low signal to
the XC3020A on pin 16, and to the XC4003E on pin 18.
PROG Pushbutton (SW6)

The PROG pushbutton applies an active low signal to
the DONE/PROGRAM input on the XC3020A FPGA
socket at pin 45 and to the PROGRAM input on the
XC4003A FPGA socket at pin 55.
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- Config -
LED Indicators
LED
D1
D2
D3
D4
D5
D6
D7
D8
XC3020APin
37
36
41
33
32
31
28
29
LED
D9
D10
D11
D12
D13
D14
D15
D16
XC4003EPin
61
62
65
66
57
58
59
60
XC3020A
XC4003E
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- Config -
7-Segment I/O Connections

Display
Segment
a
b
c
d
e
f
g
decimal point
XC3020A
U6
38
39
40
56
49
53
55
30
a
f
b
g
c
d
CIC
fe
decimal point
- Config -
XC4003E
U7
39
38
36
35
29
40
44
37
XC4003E
U8
49
48
47
46
45
50
51
41
Eight General-Purpose Input

Switches (SW3)
Switch
SW3
SW3
SW3
SW3
SW3
SW3
SW3
SW3
CIC
fe
XC3020A
11
13
15
17
19
21
23
24
- Config -
XC4003E
19
20
23
24
25
26
27
28

with XACTstepTM M1
Hardware Debugger and

XChecker Cable
Use XChecker Cable to

Simplify Verification
Downloading allows quick verification of
design in circuit
Bitstream downloaded via computers serial port directly

into FPGA
No PROM programming required
Design changes and verifications made quickly
Readback sends configuration data and flipflop values back out of chip
CIC
Verifies correct configuration

Allows in-circuit probing of all signals
Can occur while the FPGA is running
Uses no CLBs or routing resources
fe
- Xchk -
Readback Operation
Readback Trigger input starts readback
operation
Connect to RT on XChecker cable
Internal configuration clock (CCLK) drives

readback logic
Data is sent out serially on Readback Data pin

Connect to RD on XChecker cable
Trig and Data are on dedicated pins on XC3000

XC4000/XC5000 allow user programming of pin
locations
RT
XChecker
RD
CIC
fe
- Xchk -
Trig
FPGA
Data
Enabling Configuration
Readback
XC3000 controlled via Bitstream Generator
Default is enabled
Data and trigger connected to Mode pins
XC4/5000 controlled via schematic and

Bitstream Generator
Include Readback symbol in schematic

Connect TRIG and DATA to I/O pins
Can use MD0 and MD1
CLK
XChecker
RT
CIC
IPAD
(MD0)
fe
TRIG
IBUF
- Xchk -
DATA
READBACK
RIP
OBUF
OPAD
(MD1)
XChecker
RD
Enabling Flip-Flop Readback

XC3000
always enabled with configuration readback
XC4/5000
leave default configuration template option Capture
CLB and IOB Outputs When TRIG Goes Active
CIC
fe
- Xchk -
Available Readback Data

Data includes all storage elements in device
XC4000/XC5000 readback data includes all outputs of
CLBs and IOBs
XC4000/XC5000 data is captured when

readback is triggered
XC3000 data is captured as readback

progresses
May want to stop system clock for logic verification

Requires XChecker control of system clock
CIC
fe
- Xchk -
XChecker Cable Features

Controlled by Hardware Debugger
Download to single FPGA or daisy chain
Typically used during design and development
Design prototype system for XChecker cable
connection
Readback from single FPGA

Verification of bitstream
Logic verification
CIC
fe
- Xchk -
Cable Setup
Connect cable to computers serial port
Power up cable via targets VCC and GND
Hardware Debugger should find cable

automatically
Cable -> Communications... allows change to

port
CIC
fe
- Xchk -
Downloading a Design
Connect cable to target VCC, GND, PROG,
DONE, DIN, CCLK
Put device into slave mode

Select Download -> Download Design or the
lightning toolbar icon
Can verify configuration with Download ->
Verify Bitstream or checkmark toolbar icon

Requires configuration readback to be enabled
CIC
fe
- Xchk -
Use Synchronous Debugging

Debugging session allows readback of logic
state
Selected from Debug menu or by selecting

toolbar icon (Bug with clock)
Synchronous mode controls system clock via

CLKO
Clock stops between each readback (required in

XC3000)
Clock source is internal cable clock or external system
clock via CLKI
CIC
fe
- Xchk -
Control Panel Defines Debug

Session
Readback Control Panel
View > Control Pannel
Allows direct control of:
CIC
System clock source definition and application

Readback trigger source definition and application
Number of readbacks
Display options
fe
- Xchk -
Use XChecker or System as

Clock Source
Can use one of four clock speeds in cable, or
route system clock into cable for user control
CIC
fe
- Xchk -
Specify When Readback is

to be Triggered
Can trigger on external event
Specify number of clocks between multiple
readbacks
CIC
fe
- Xchk -
Choose Signals to Display

Can define groups first with Groups... button
Can select flip-flops in XC3000, RAM bits in
XC4000, and combinatorial outputs in
XC4000/XC5000
Filter for
desired
signals
CIC
fe
- Xchk -
Activating Readback
Select Read button in Control Panel
Waveform opens automatically
Note waveform reflects several steady state conditions,
not timing
CIC
fe
- Xchk -

with XACTstepTM M1
Xilinx Conversion
Converting Foundation Projects

The first time you open a project of type XACT
step6, a dialog box will appear
Convert
The Project Manager will automatically change the
project type to XACT step M1.
Enable XACT step6

The Projects Manager will not convert this project, nor
will it automatically convert any other XACT step6
projects.
CIC
fe
- Conver -
After Converting a Project

The library names have changed slightly
XC4000EU -> XC4000E
The XBLOXU library is removed

A new library called SIMPRIMS is added
CIC
fe
- Conver -
Migrating ABEL Designs

Recompiling all ABEL macros is recommended
M1 uses EDIF netlist interface instead of XNF.
Recompiling will create an EDIF file to replace the XNF
IF your design contains ABEL, you must add

the XABELSIM library to your project.
This library is used to perform functional simulation of

ABEL modules.
CIC
fe
- Conver -
Migrating X-BLOX/MEMGEN
Designs I
Option 1: Convert X-BLOX/MEMGEN modules
to LogiBLOX
1. Convert the project type to XACTstep M1.

Attach the XBLOXU library and addit to the project.
2. Select Tools -> Library Manager
3. Select Library -> attach
4. Browse to the location of the BLOXU library. Select
the XBLOXU library and click OK.
5. Close the Library Manager.
6. Select File -> Project Libraries.
7. Select the XBLOXU library and click Add.
8. Close the Project Libraries dialog.
You will be able to see the XBLOX modules and use them
as a reference when creating the LogiBLOX
equivalents.
CIC
fe
- Conver -
Designs II
9. Replace each functional X-BLOX and MEMGEN
module in your design with equivalent LogiBLOX
module.
Non-logical X-BLOX modules such as BUS_DEF,
BUS_Ifxx, CAST, ELEMENT, and SLICE should be
removed.
10. Add bounds to all your buses
Option 2: Run your optimized X-BLOX design

through M1
1. Dont convert the project type of XACTstep M1

2. Attach the version 6.x libraries needed for the project
XBLOXU and XC4000EU or XC5200U
3. Follow the 6.x design flow through the optimize
stage, where the .XTF file is created
4. Rename design.xtf to design.xnf.
CIC
fe
- Conver -
Designs III
5. Open the M1 Design Manager and create a new
project. Select design.xnf as the source file.
6. Use the M1 tools to translate, optimize, place and
route this design.
You can perform functional simulation by using the
normal 6.x flow.
Timing Simulation
1. In the M1 Flow Engine Options, edit the
Implementation Template
2. Click on the interface tab. Under Simulation Data
Options, select XNF format.
3. Run the FLOW Engine to produce the simulation
netlist
tims_sim.xnf
CIC
fe
- Conver -
Designs IV
4. In the Foundation Project Manager, select Tools ->
Simulator. When the simulator comes up, select File > Load Netlist. Select files of type *.XN*, and choose
time_sim.xnf
5. Make sure the simulation mode is set to TM.
CIC
fe
- Conver -
Translation of 5.X designs to

M1.X with LCA2NCD
LCA2NCD Usage
lca2ncd [-w] [-p] <infile> [<output>]
Input file for LCA2NCD
Logic Cell Array from 5.X (.lca)
Output files created by LCA2NCD
Mapped physical design implementation (.ncd)
File to aid future guided mapping (.mdf)
-w : Overwrite. Allow overwrite of an existing output file.
-p : Placement only, i.e. dont preserve routing.
CIC
fe
- Conver -
Translation of 5.X constraints to

M1.X with CSTTRANS
Convert existing constraint files into an M1.X
usable file.
CSTTRANS Usage
csttrans <infile>[.cst] [-o <output>]
Input file for CSTTRANS
5.X constraint file (.cst)
Output files created by CSTTRANS
User constraints file (.ucf)
CIC
fe
- Conver -
Xilinx Foundation Lab

Fibonacci Generator
CIC
fe
- Lab -
Lab 1 - New a Project

File > New Project
CIC
fe
- Lab -
@y5
Lab 2 - myor8 I
4!1@4=
Click Schematic Editor Icon

File > New Sheet (MYFIB1.SCH)
@y
CIC
fe
- Lab -
Lab 2 - myor8 II
File > Save as ... (myor8)
=yPMU[
CIC
fe
- Lab -
File > Page Setup ...
Lab 2 - myor8 III
3Symbol
CIC
Hierarchy > Create Macro Symbol From Current Sheet
fe
G!No
- Lab -
Lab 3 - DB4_LED, DB4_CR3,

DB4_CR4 I
Lab23Macro Symbol1, 2DB4_LED1=Y
File > Open > Browse > MYFIB1.SCH

save as DB4_LED
@yYp2=
new+!schematic 3+!SCH file, myfib1.sch,

G5
p.s.
new
schematic
myfib2.sch, myfib3.sch...,
CIC
fe
- Lab -

DB4_CR4 II
4DB4_LED3DB4_CR3
CIC
File > Open > Browse > MYFIB1.SCH

File > Open > DB4_LED
DB4_LED
,
Edit > Copy
MYFIB1,
Edit > Paste,
LED[7:0]
bus
,
OBUF OPAD
bus - DSP[6:0],
bus taps DSP[6:0] OBUFs
46U2
1=dG fG
26U
fG
Gs
6Uv
2
@1 V
E1
4
2
V
%OPAD1LOCG
Symbol
uB, %LOC1G
4DB4_CR33DB4_CR4
fe
- Lab -

DB4_CR4 III
DB4_CR3
DB4_CR4
CIC
fe
- Lab -
Lab 4 - ROM16x7
CIC
4LogiBLOX1ROM3.DBt1=
UProject ManagermrLogiBLOX
r
Tools > LogiBLOX...
@y5]G OK
fe
rom16x7.mem
depth 16
width 7
radix 2
data
1000000,
1111001,
0100100,
0110000,
0011001,
0010010,
0000010,
1011000,
0000000,
0010000,
0001000,
0000011,
1000110,
0100001,
0000110,
0001110
- Lab -
Lab 5 - DEC7SEGA I
7
ABEL3.DBt1=
)Project Manager, G HDL Entry
Icon
1ABEL=
G
Use HDL Design Wizard

Language
ABEL
Name
DEC7SEGA
Port
Output ,
Advance ...,
Combinatorial
CIC
`G
`5
`y
fe
- Lab -
Lab 5 - DEC7SEGA II
2=y
{sConfiguration
Synthesis > Configuration
7
Synthesis > Check Syntax
Title 'DEC7SEGA'
Declarations
CODE3 PIN;
CODE2 PIN;
CODE1 PIN;
CODE0 PIN;
DSP6..DSP0 PIN istype 'com';
DSP = [DSP6..DSP0];
CODE = [CODE3..CODE0];
Truth_table ( [ CODE] -> [ DSP0 .. DSP6 ] )
// Segments : a b c d e f g
[ 0 ] -> [ 0, 0, 0, 0, 0, 0, 1 ];
[ 1 ] -> [ 1, 0, 0, 1, 1, 1, 1 ];
[ 2 ] -> [ 0, 0, 1, 0, 0, 1, 0 ];
[ 3 ] -> [ 0, 0, 0, 0, 1, 1, 0 ];
[ 4 ] -> [ 1, 0, 0, 1, 1, 0, 0 ];
[ 5 ] -> [ 0, 1, 0, 0, 1, 0, 0 ];
[ 6 ] -> [ 0, 1, 0, 0, 0, 0, 0 ];
[ 7 ] -> [ 0, 0, 0, 1, 1, 0, 1 ];
[ 8 ] -> [ 0, 0, 0, 0, 0, 0, 0 ];
[ 9 ] -> [ 0, 0, 0, 0, 1, 0, 0 ];
[ 10 ] -> [ 0, 0, 0, 1, 0, 0, 0 ];
[ 11 ] -> [ 1, 1, 0, 0, 0, 0, 0 ];
[ 12 ] -> [ 0, 1, 1, 0, 0, 0, 1 ];
[ 13 ] -> [ 1, 0, 0, 0, 0, 1, 0 ];
[ 14 ] -> [ 0, 1, 1, 0, 0, 0, 0 ];
[ 15 ] -> [ 0, 1, 1, 1, 0, 0, 0 ];
end DEC7SEGA
CIC
fe
- Lab -
Lab 5 - DEC7SEGA III
{s}G
Synthesis > Options
}, 3Symbol
CIC
fe
- Lab -
Project > Create Macro
Lab 5 - DEC7SEGA IV
4Symbol Editor%DEC7SEGA1symbol
CIC
Project ManagermG Tools > Symbol Editor

]Symbol EditorrG File > open (DEC7SEGA)
fe
- Lab -
Lab 5 - DEC7SEGA V
CIC
2!%@yf
DSP0, DSP1,...DSP6 - cGPIN, f
Del
46U%symbolU[
5bus - DSP[6:0] - Symbol > Add Pin...
fe
- Lab -
Lab 6 - scount8 I
4State Editory 8 bits counter - scount8

)Project Manager, G State Editor Icon
EState Machine1.
G
Use HDL Design Wizard

Language
ABEL
Name
scount8
Port
Output ,
Advance ...,
Registered
CIC
`G
`5
`y
fe
- Lab -
Lab 6 - scount8 II
The number of machines
G one
@yyState Diagram
3ABEL code !
CIC
Synthesis > HDL Code

Generation
fe
- Lab -
Lab 6 - scount8 III

combinational
CIC
fe
- Lab -
Lab 6 - scount8 IV
{s}G
Synthesis > Options
}, 3Symbol
CIC
fe
- Lab -
Project > Create Macro
Lab 7 -
EMulti Sheet1Top
Schematic I
E#+MTop Schematic
File > Open > Browse (MYFIB1.SCH)
, File > Save
MYFIB1.SCH
Project
Project
Document > Add... > MYFIB1.SCH
Manager
@=yY=
7
"!5
mG
m!
E#2MTop Schematic
File > New (MYFIB2.SCH)
, File > Save
MYFIB2.SCH
Project
Project
Document > Add... > MYFIB2.SCH
Manager
@yY=
7
"!5
mG
CIC
fe
- Lab -
m!
Lab 7 -
EMulti Sheet1Top
Schematic II
CIC
fe
MYFIB1.SCH
- Lab -
Lab 7 -
EMulti Sheet1Top
Schematic III
MYFIB2.SCH
CIC
fe
- Lab -
Lab 8 - Simulate MYFIB I
Schematic CapturemGsimulation toolbox SC Probes
GSC ProbesB1Probe tools, f46UG

1Net NameBus Name
CIC
GENABLE, CLK, RESET, FIB, PREV, NEXT, FIBCC,

DSPA, DSPB, FIBCC_N
GSC ProbesB1Simulator Logic Simulator
fe
- Lab -
D,
Lab 8 - Simulate MYFIB II
Stimulator Selection, Vinputs netslu1A5
4Stimulator^S
CIC
G GSignal > Add StimulatorStimulator

Selection
4Stimulator Selection{ENABLE1aq (7v
vq
s+ahighlow), CLK1aB1, RESET1aCS
CS74Cs, GWaveform > Edit Test
Vector State Selectionf4!@, @py
StepdBS+[Dt
LongdBSo1+Dt
Options > Simulation Step... LongStep1to
fe
- Lab -
Lab 8 - Simulate MYFIB III
CIC
fe
- Lab -
Lab 9 - Simulation from Macros
4MacroBatch^S
@Command file
Tools > Script File > Edit... (test.cmd)
Command file
Macro cp1
Signal > Delete Signals > All

File > Run Script File...
(test.cmd)
CIC
fe
- Lab -
restart
vector FIB FIB[7:0]
vector PREV PREV[7:0]
vector NEXT NEXT[7:0]
vector FIBCC FIBCC[7:0]
vector FIBCC_N FIBCC_N[7:0]
vector DSPA DSPA[6:0]
vector DSPB DSPB[6:0]
radix hex FIB PREV NEXT FIBCC
radix bin DSPA DSPB FIBCC_N
watch clk enable reset PREV FIB NEXT
watch FIBCC FIBCC_N DSPA DSPB
clock clk 0 1
step 20ns
l ENABLE
l RESET
c2
h RESET
c2
sim
h ENABLE
c4
l RESET
c2
h RESET
c1
l enable
c2
h ENABLE
c 256
Lab 10 - XACT Step

Implementation I
m1 XACT, ^5 XACT Step

Part "!%
Click Project Manager

Design > Implementation
Options...
CIC
2 Produce Logic Level Timing Report, Produce Post

Layout Timing Report G, !I Optional Targets 1G
7G7
GOK
GRun
fe
- Lab -
Lab 10 - XACT Step

Implementation II
Y Implement pG Reports
Map Report
Section: Design Summary

-----------------------Number of warnings: _____
Number of errors:
_____
Number of CLBs:
_____ out of 100
Flops/latches: _____
4 input LUTs:
_____
3 input LUTs:
_____
Number of bonded IOBs:
_____ out of 61
Number of RPM macros:
_____
Logic Level Timing Report
Design statistics:
Minimum period: ________ns (Maximum frequency: ________MHz)
Maximum net delay: ________ns
CIC
fe
- Lab -
Lab 10 - XACT Step

Implementation III
Place & Route Report
IO
___/80 ___% used

___/61 ___% bonded
LOGIC ___/100 ___% used
IOB
___/80
___% used
CLB
___/100 ___% used
The Average Connection Delay for this design is: _______ ns
The Average Connection Delay on critical nets is: _______ ns
The Average Clock Skew for this design is:
_______ ns
The Maximum Pin Delay is:
_______ ns
The Average Connection Delay on the 10 Worst Nets is: ______ ns
Post Layout Timing Report
Design statistics:
Minimum period: _______ns (Maximum frequency: ______MHz)
Maximum net delay: _______ns
CIC
fe
- Lab -
Lab 11 - Timing Analysis I
ETiming Analyzer
r myfib.ncdr
Design Manager mG7 Timing analyzer

Tools > Timing Analyzer
File > Open Design >

c:\active\projects\myfib\xproject\v1_0\rev1\myfib.lca
Analyze > Timing Constraints

Analyze > Design Performance
4 Filter Gs1 path
CIC
Path Filters > Path Analysis Filters > Select Sources...

Path Filters > Path analysis Filters > Select Destinations...
Analyze > All Paths
Source Destination
C@BG
fe
- Lab -
Lab 11 - Timing Analysis II
CIC
fe
- Lab -
Lab 12 - XACT Performance I
^5 Schematic, MYFIB1.SCH m5 TIMESPEC

1 TNM
XACT Step, Timing Analyzer 1, "
!$}
c&rDesign ManagerfUProject Manager^5Design

Manager Implementation
Implementation m Optional Targets 1 Produce Timing
Simulation Data G, @! Lab. Timing
Simulation
CIC
fe
- Lab -
Lab 12 - XACT Performance II
CIC
fe
- Lab -
Lab 13 - Timing Simulation
Project Manager m1 SIM Timing

Function Simulation 1 Macro S
CIC
Tools > Script File > Edit... (test.cmd)

step 20ns
step 40ns,
File > Run Script File...(test2.cmd)
Timing Analyzer
,
Macro,
clk period
Macro
Signal > Delete Signals > All
test2.cmd
1 % step 1,
[1

cp1
fe
- Lab -

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Xilinx

Chip Implementation Center

Introduction to Programmable Logic Device

Foundation Schematic Design

Combinational Logic Design

Xilinx Abel & Foundation HDL Design

Foundation State Editor

Analyzing Simulation Results

Advanced Software Design

Xilinx Design Flow

FPGA/CPLD Design Flow

HDL Source File

Static Timing Report

Place & Route

PAR (Place & Route)

Device Programming Files

Interface Netlist Format

Tool: Xilinx XACTstep softwar (Unix or PC version)

Generate the VHDL file with timing

Tool: Xilinx Hardware Debugger

Timing Verilog netlister

Timing VHDL netlister

Synopsys Tools We May Use

Xilinx-Synopsys Synthesis Flow

Verilog/VHDL Design Design Constraints

Xilinx Symbol Libraries

Xilinx Synthesis &

Xilinx XACTstep Software

Core implementation for all Xilinx FPGA/CPLD device families

Interface to third-party tools

XACTstep 5.2 / 6.0 and M1.3

SunOS, HP Unix, Solaris*

SunOS, HP Unix, Solaris

Command line only on WS

Command line scripts still

Xilinx Netlist Format (XNF)

EDIF 2.0.0 is Default, XNF

32 bit code (no DOS windows!)

PAR from NeoCAD

Xilinx Customer Support

(800) 255-7778 (outside 408) or (408) 879-5199

On-line help and documentation

XACTstep (FPGA, CPLD)

Basic PLD Architecture

CPLD and FPGA

Industrys best pinlocking architecture

XC9500 - Architectural Features

Flexible function block

36 inputs with 18 outputs

3.3V/5V I/O operation

XC9500 Function Block

Each function block is like a 36V18 !

to/from other macrocells

XC9500 Product Family

Xilinx FPGA Families

Xilinx FPGA Family Comparison

4-8 global clocks

I/O Blocks (IOBs)

Configurable Logic Block (CLB)