FPGA Design Flow
FPGA Design Flow
called synthesizer.
For an HDL code that is correctly written and simulated, synthesis shouldn't
be any problem. However, synthesis can reveal some problems and
potential errors that can't be found using behavioral simulation, so, an
FPGA engineer should pay attention to warnings produced by the synthesizer.
6) Implementation. A synthesizer-generated netlist is mapped onto particular device's internal structure. The main
phase of the implementation
stage
is place and route or layout, which allocates FPGA resources (such as logic cells
and connection wires). Then these configuration data are written to a special file by a program called bitstream
generator.
7) Timing analysis. During the timing analysis special software checks whether the implemented design satisfies
timing constraints (such as clock frequency) specified by the user.