4601 Fe

LTM4601/LTM4601-1
12A µModule Regulators

with PLL, Output Tracking
and Margining
Features Description
n Complete Switch Mode Power Supply The LTM®4601 is a complete 12A step-down switch mode
n Wide Input Voltage Range: 4.5V to 20V DC/DC power supply with onboard switching controller,
n 12A DC Typical, 14A Peak Output Current MOSFETs, inductor and all support components. The
n 0.6V to 5V Output Voltage µModule® regulator is housed in small surface mount
n Output Voltage Tracking and Margining 15mm × 15mm × 2.82mm LGA and 15mm × 15mm ×
n Parallel Multiple µModule Regulators for Current 3.42mm BGA packages. Operating over an input voltage
Sharing range of 4.5V to 20V, the LTM4601 supports an output
n Differential Remote Sensing for Precision voltage range of 0.6V to 5V as well as output voltage
Regulation (LTM4601 Only) tracking and margining. The high efficiency design deliv-
n PLL Frequency Synchronization ers 12A continuous current (14A peak). Only bulk input
n ±1.5% Regulation and output capacitors are needed to complete the design.
n Current Foldback Protection (Disabled at Start-Up)
The low profile and light weight package easily mounts
n SnPb or RoHS Compliant Finish
in unused space on the back side of PC boards for high
n UltraFast™ Transient Response
density point of load regulation. The µModule regulator
n Current Mode Control
can be synchronized with an external clock for reducing
n Up to 95% Efficiency at 5VIN, 3.3VOUT
undesirable frequency harmonics and allows PolyPhase®
n Programmable Soft-Start
operation for high load currents.
n Output Overvoltage Protection
n Small Footprint, Low Profile A high switching frequency and adaptive on-time current
(15mm × 15mm × 2.82mm) Surface Mount LGA and mode architecture deliver a very fast transient response
(15mm × 15mm × 3.42mm) BGA Packages to line and load changes without sacrificing stability. An
onboard differential remote sense amplifier can be used
to accurately regulate an output voltage independent of
Applications load current. The onboard remote sense amplifier is not
n Telecom and Networking Equipment available in the LTM4601-1.
n Servers L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registered
n Industrial Equipment trademarks and UltraFast and LTpowerCAD are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
n Point of Load Regulation including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210.
Typical Application Efficiency and Power Loss

vs Load Current
1.5V/12A Power Supply with 4.5V to 20V Input 95 4.0
EFFICIENCY 5VIN
CLOCK SYNC 90
VIN 3.5
TRACK/SS CONTROL
4.5V TO 20V
85
VIN PLLIN TRACK/SS VOUT 12VIN 3.0
PGOOD VOUT 1.5V 80
POWER LOSS (W)
EFFICIENCY (%)
100pF 12A
VFB 75 2.5
ON/OFF RUN MARG0 12VIN
MARGIN
70 2.0
COMP MARG1 CONTROL COUT 5VIN
CIN LTM4601
INTVCC VOUT_LCL 65
1.5
DRVCC DIFFVOUT
60
MPGM VOSNS+ POWER LOSS 1.0
R1 VOSNS– 55
392k SGND PGND fSET RSET 50 0.5
40.2k 0 2 4 6 8 10 12 14
5% MARGIN
4601 TA01a LOAD CURRENT (A)
4601 TA01b
4601fe
For more information www.linear.com/LTM4601 1

LTM4601/LTM4601-1
Absolute Maximum Ratings
(Note 1)
INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V with VIN.............................................................. –0.3V to 20V
DIFFVOUT )..................................................... –0.3V to 6V VOSNS+, VOSNS –...........................–0.3V to INTVCC + 0.3V
PLLIN, TRACK/SS, MPGM, MARG0, MARG1, Operating Temperature Range (Note 2)....–40°C to 85°C
PGOOD, fSET...............................–0.3V to INTVCC + 0.3V Junction Temperature............................................ 125°C
RUN (Note 5)................................................ –0.3V to 5V Storage Temperature Range................... –55°C to 125°C
VFB, COMP................................................. –0.3V to 2.7V Reflow (Peak Body) Temperature........................... 245°C
Pin Configuration
TOP VIEW TOP VIEW
TRACK/SS
TRACK/SS
INTVCC
INTVCC
MPGM
MPGM
COMP
PLLIN
COMP
PLLIN
RUN
RUN
VIN fSET VIN fSET
MARG0 MARG0
MARG1 MARG1
DRVCC DRVCC
VFB VFB
PGND PGND
PGOOD PGOOD
SGND SGND
VOSNS+/NC2* VOSNS+/NC2*
DIFFVOUT/NC3* DIFFVOUT/NC3*
VOUT VOUT
VOUT_LCL VOUT_LCL
VOSNS–/NC1* VOSNS–/NC1*
LGA PACKAGE BGA PACKAGE

118-LEAD (15mm × 15mm × 2.82mm) 118-LEAD (15mm × 15mm × 3.42mm)
TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W, TJMAX = 125°C, θJA = 15.5°C/W, θJC = 6.5°C/W,
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 1.7g WEIGHT = 1.9g
*LTM4601-1 ONLY *LTM4601-1 ONLY
Order Information
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE MSL TEMPERATURE RANGE
DEVICE FINISH CODE TYPE RATING (Note 2)
LTM4601EV#PBF Au (RoHS) LTM4601V e4 LGA 3 –40°C to 85°C
LTM4601IV#PBF Au (RoHS) LTM4601V e4 LGA 3 –40°C to 85°C
LTM4601EV-1#PBF Au (RoHS) LTM4601V-1 e4 LGA 3 –40°C to 85°C
LTM4601IV-1#PBF Au (RoHS) LTM4601V-1 e4 LGA 3 –40°C to 85°C
LTM4601EY#PBF SAC305 (RoHS) LTM4601Y e1 BGA 3 –40°C to 85°C
LTM4601IY#PBF SAC305 (RoHS) LTM4601Y e1 BGA 3 –40°C to 85°C
LTM4601EY-1#PBF SAC305 (RoHS) LTM4601Y-1 e1 BGA 3 –40°C to 85°C
LTM4601IY-1#PBF SAC305 (RoHS) LTM4601Y-1 e1 BGA 3 –40°C to 85°C
LTM4601IY SnPb (63/37) LTM4601Y e0 BGA 3 –40°C to 85°C
LTM4601IY-1 SnPb (63/37) LTM4601Y-1 e0 BGA 3 –40°C to 85°C
4601fe
2 For more information www.linear.com/LTM4601

LTM4601/LTM4601-1
Order Information
Consult Marketing for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and Manufacturing
ranges. *Device temperature grade is indicated by a label on the shipping Procedures:
container. Pad or ball finish code is per IPC/JEDEC J-STD-609. www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking: • LGA and BGA Package and Tray Drawings:
www.linear.com/leadfree www.linear.com/packaging
Electrical Characteristics The l denotes the specifications which apply over the –40°C to 85°C
temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V, per typical application (front page) configuration.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN(DC) Input DC Voltage l 4.5 20 V
VOUT(DC) Output Voltage CIN = 10µF ×3, COUT = 200µF, RSET = 40.2k
VIN = 5V, VOUT = 1.5V, IOUT = 0A l 1.478 1.5 1.522 V
VIN = 12V, VOUT = 1.5V, IOUT = 0A l 1.478 1.5 1.522 V
Input Specifications
VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 4 V
IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A. VOUT = 1.5V
VIN = 5V 0.6 A
VIN = 12V 0.7 A
IQ(VIN,NOLOAD) Input Supply Bias Current VIN = 12V, No Switching 3.8 mA
VIN = 12V, VOUT = 1.5V, Switching Continuous 38 mA
VIN = 5V, No Switching 2.5 mA
VIN = 5V, VOUT = 1.5V, Switching Continuous 42 mA
Shutdown, RUN = 0, VIN = 12V 22 µA
IS(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 12A 1.81 A
VIN = 12V, VOUT = 3.3V, IOUT = 12A 3.63 A
VIN = 5V, VOUT = 1.5V, IOUT = 12A 4.29 A
INTVCC VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V
Output Specifications
IOUTDC Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 6) 0 12 A
ΔVOUT(LINE) Line Regulation Accuracy VOUT = 1.5V, IOUT = 0A, VIN from 4.5V to 20V l 0.3 %
VOUT
ΔVOUT(LOAD) Load Regulation Accuracy VOUT = 1.5V, 0A to 12A (Note 6)
VOUT VIN = 12V, with Remote Sense Amplifier l 0.25 %
VIN = 12V (LTM4601-1) l 1 %
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2× 100µF X5R Ceramic
VIN = 12V, VOUT = 1.5V 20 mVP-P
VIN = 5V, VOUT = 1.5V 18 mVP-P
fS Output Ripple Voltage Frequency IOUT = 5A, VIN = 12V, VOUT = 1.5V 850 kHz
ΔVOUT(START) Turn-On Overshoot COUT = 200µF, VOUT = 1.5V, IOUT = 0A,
TRACK/SS = 10nF
VIN = 12V 20 mV
VIN = 5V 20 mV
tSTART Turn-On Time COUT = 200µF, VOUT = 1.5V, TRACK/SS = Open,
IOUT = 1A Resistive Load
VIN = 12V 0.5 ms
VIN = 5V 0.5 ms
4601fe

LTM4601/LTM4601-1
Electrical Characteristics The l denotes the specifications which apply over the –40°C to 85°C
temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V, per typical application (front page) configuration.
ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load,
COUT = 2 × 22µF Ceramic, 470µF 4V Sanyo
POSCAP
VIN = 12V 35 mV
VIN = 5V 35 mV
tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load
VIN = 12V 25 µs
IOUTPK Output Current Limit COUT = 200µF Ceramic
VIN = 12V, VOUT = 1.5V 17 A
VIN = 5V, VOUT = 1.5V 17 A
Remote Sense Amp (Note 3) (LTM4601 Only, Not Supported in the LTM4601-1)
VOSNS+, VOSNS– Common Mode Input Voltage Range VIN = 12V, RUN > 2V 0 INTVCC – 1 V
CM Range
DIFFVOUT Range Output Voltage Range VIN = 12V, DIFFVOUT Load = 100k 0 INTVCC – 1 V
VOS Input Offset Voltage Magnitude 1.25 mV
AV Differential Gain 1 V/V
GBP Gain Bandwidth Product 3 MHz
SR Slew Rate 2 V/µs
RIN Input Resistance VOSNS+ to GND 20 kW
CMRR Common Mode Rejection Mode 100 dB
Control Stage
VFB Error Amplifier Input Voltage IOUT = 0A, VOUT = 1.5V l 0.594 0.6 0.606 V
Accuracy
VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V
ITRACK/SS Soft-Start Charging Current VTRACK/SS = 0V –1.0 –1.5 –2.0 µA
tON(MIN) Minimum On Time (Note 4) 50 100 ns
tOFF(MIN) Minimum Off Time (Note 4) 250 400 ns
RPLLIN PLLIN Input Resistance 50 kΩ
IDRVCC Current into DRVCC Pin VOUT = 1.5V, IOUT = 1A, DRVCC = 5V 18 25 mA
RFBHI Resistor Between VOUT_LCL and VFB 60.098 60.4 60.702 kΩ
VMPGM Margin Reference Voltage 1.18 V
VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V
PGOOD Output
ΔVFBH PGOOD Upper Threshold VFB Rising 7 10 13 %
ΔVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 %
ΔVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings correlation with statistical process controls. The LTM4601I/LTM4601I-1
may cause permanent damage to the device. Exposure to any Absolute are guaranteed over the –40°C to 85°C operating temperature range.
Maximum Rating condition for extended periods may affect device Note 3: Remote sense amplifier recommended for ≤3.3V output.
reliability and lifetime. Note 4: 100% tested at wafer level only.
Note 2: The LTM4601 is tested under pulsed load conditions such that Note 5: Limit current into RUN pin to less than 1mA.
TJ ≈ TA. The LTM4601E/LTM4601E-1 are guaranteed to meet performance
Note 6: See output current derating curves for different VIN, VOUT and TA.
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
4601fe

LTM4601/LTM4601-1
Typical Performance Characteristics (See Figure 18 for all curves)
Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current
with 5VIN with 12VIN with 20VIN
100 100 100
95 95
95
90
90 90
85
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
85 85
80
80 75 80
75 70 75
0.6VOUT
0.6VOUT 65 1.2VOUT 1.2VOUT
70 1.2VOUT 1.5VOUT 70 1.5VOUT
1.5VOUT 60 2.5VOUT 2.5VOUT
65 2.5VOUT 3.3VOUT 65 3.3VOUT
55
3.3VOUT 5VOUT 5.0VOUT
60 50 60
0 5 10 15 0 5 10 15 0 5 10 15
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4601 G01 4601 G02 4601 G03
1.2V Transient Response 1.5V Transient Response 1.8V Transient Response
VOUT VOUT VOUT

50mV/DIV 50mV/DIV 50mV/DIV
0A TO 6A 0A TO 6A 0A TO 6A
LOAD STEP LOAD STEP LOAD STEP
20µs/DIV 4601 G04 20µs/DIV 4601 G05

20µs/DIV 4601 G06
1.2V AT 6A/µs LOAD STEP 1.5V AT 6A/µs LOAD STEP 1.8V AT 6A/µs LOAD STEP
COUT = 3 • 22µF 6.3V CERAMICS COUT = 3 • 22µF 6.3V CERAMICS COUT = 3 • 22µF 6.3V CERAMICS
470µF 4V SANYO POSCAP 470µF 4V SANYO POSCAP 470µF 4V SANYO POSCAP
C3 = 100pF C3 = 100pF C3 = 100pF
2.5V Transient Response 3.3V Transient Response
VOUT VOUT
50mV/DIV 50mV/DIV
0A TO 6A 0A TO 6A
LOAD STEP LOAD STEP
20µs/DIV 4601 G07 20µs/DIV 4601 G08
2.5V AT 6A/µs LOAD STEP 3.3V AT 6A/µs LOAD STEP

COUT = 3 • 22µF 6.3V CERAMICS COUT = 3 • 22µF 6.3V CERAMICS
470µF 4V SANYO POSCAP 470µF 4V SANYO POSCAP
C3 = 100pF C3 = 100pF
4601fe

LTM4601/LTM4601-1
Typical Performance Characteristics (See Figure 18 for all curves)
Start-Up, IOUT = 12A
Start-Up, IOUT = 0A (Resistive Load)
VOUT VOUT
0.5V/DIV 0.5V/DIV
IIN
IIN 1A/DIV
0.5A/DIV
5ms/DIV 4601 G09 2ms/DIV 4601 G10
VIN = 12V VIN = 12V

VOUT = 1.5V VOUT = 1.5V
COUT = 470µF, 3 × 22µF COUT = 470µF, 3 × 22µF
SOFT-START = 10nF SOFT-START = 10nF
VIN to VOUT Step-Down Ratio Track, IOUT = 12A

5.5
3.3V OUTPUT WITH
5.0 130k FROM VOUT TRACK/SS
4.5 TO ION 0.5V/DIV
5V OUTPUT WITH VFB
4.0 0.5V/DIV
OUTPUT VOLTAGE (V)
100k RESISTOR
3.5 ADDED FROM fSET VOUT
3.0 TO GND 1V/DIV
5V OUTPUT WITH
2.5
NO RESISTOR ADDED
2.0 FROM fSET TO GND 2ms/DIV 4601 G12
1.5 2.5V OUTPUT VIN = 12V

1.8V OUTPUT VOUT = 1.5V
1.0 COUT = 470µF, 3 × 22µF
0.5 1.5V OUTPUT SOFT-START = 10nF
1.2V OUTPUT
0
0 2 4 6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
4601 G11
Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 12A
VOUT VOUT
0.5V/DIV 0.5V/DIV
IIN IIN
1A/DIV 1A/DIV
50µs/DIV 4601 G13

50µs/DIV 4601 G14
VIN = 12V VIN = 12V

VOUT = 1.5V VOUT = 1.5V
COUT = 470µF, 3 × 22µF COUT = 470µF, 3 × 22µF
SOFT-START = 10nF SOFT-START = 10nF
4601fe

LTM4601/LTM4601-1
Pin Functions (See Package Description for Pin Assignment)
VIN (Bank 1): Power Input Pins. Apply input voltage be- TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
tween these pins and PGND pins. Recommend placing Start Pin. When the module is configured as a master
input decoupling capacitance directly between VIN pins output, then a soft-start capacitor is placed from this pin
and PGND pins. to ground to control the master ramp rate. A soft-start
VOUT (Bank 3): Power Output Pins. Apply output load capacitor can also be used for soft-start turn-on of a stand
between these pins and PGND pins. Recommend placing alone regulator. Slave operation is performed by putting
output decoupling capacitance directly between these pins a resistor divider from the master output to the ground,
and PGND pins. See Figure 15. and connecting the center point of the divider to this pin.
See the Applications Information section.
PGND (Bank 2): Power ground pins for both input and
output returns. MPGM (Pin A12): Programmable Margining Input. A re-
sistor from this pin to ground sets a current that is equal
VOSNS– (Pin M12): (–) Input to the Remote Sense Ampli- to 1.18V/R. This current multiplied by 10kΩ will equal a
fier. This pin connects to the ground remote sense point. value in millivolts that is a percentage of the 0.6V refer-
The remote sense amplifier is used for VOUT ≤3.3V. Tie to ence voltage. See the Applications Information section.
INTVCC if not used. To parallel LTM4601s, each requires an individual MPGM
NC1 (Pin M12): No internal connection on the LTM4601-1. resistor. Do not tie MPGM pins together.
VOSNS+ (Pin J12): (+) Input to the Remote Sense Ampli- fSET (Pin B12): Frequency Set Internally to 850kHz. An
fier. This pin connects to the output remote sense point. external resistor can be placed from this pin to ground
The remote sense amplifier is used for VOUT ≤3.3V. Tie to to increase frequency. See the Applications Information
ground if not used. section for frequency adjustment.
NC2 (Pin J12): No internal connection on the LTM4601-1. VFB (Pin F12): The Negative Input of the Error Amplifier.
Internally, this pin is connected to VOUT_LCL pin with a
DIFFVOUT (Pin K12): Output of the Remote Sense Ampli- 60.4k precision resistor. Different output voltages can be
fier. This pin connects to the VOUT_LCL pin. Leave floating
programmed with an additional resistor between VFB and
if not used. SGND pins. See the Applications Information section.
NC3 (Pin K12): No internal connection on the LTM4601-1. MARG0 (Pin C12): This pin is the LSB logic input for the
DRVCC (Pin E12): This pin normally connects to INTVCC margining function. Together with the MARG1 pin it will
for powering the internal MOSFET drivers. This pin can be determine if margin high, margin low or no margin state
biased up to 6V from an external supply with about 50mA is applied. The pin has an internal pull-down resistor of
capability, or an external circuit as shown in Figure 16. 50k. See the Applications Information section.
This improves efficiency at the higher input voltages by
MARG1 (Pin D12): This pin is the MSB logic input for the
reducing power dissipation in the module.
margining function. Together with the MARG0 pin it will
INTVCC (Pin A7): This pin is for additional decoupling of determine if margin high, margin low or no margin state
the 5V internal regulator. is applied. The pin has an internal pull-down resistor of
PLLIN (Pin A8): External Clock Synchronization Input 50k. See the Applications Information section.
to the Phase Detector. This pin is internally terminated
to SGND with a 50k resistor. Apply a clock with a high
level above 2V and below INTVCC. See the Applications
Information section.
4601fe

LTM4601/LTM4601-1
Pin Functions (See Package Description for Pin Assignment)
SGND (Pin H12): Signal Ground. This pin connects to RUN (Pin A10): Run Control Pin. A voltage above 1.9V
PGND at output capacitor point. See Figure 15. will turn on the module, and when below 1V, will turn
COMP (Pin A11): Current Control Threshold and Error off the module. A programmable UVLO function can be
Amplifier Compensation Point. The current comparator accomplished by connecting to a resistor divider from
threshold increases with this control voltage. The voltage VIN to ground. See Figure 1. This pin has a 5.1V Zener to
ranges from 0V to 2.4V with 0.7V corresponding to zero ground. Maximum pin voltage is 5V. Limit current into the
sense voltage (zero current). RUN pin to less than 1mA.
PGOOD (Pin G12): Output Voltage Power Good Indicator. VOUT_LCL (Pin L12): VOUT connects directly to this pin
Open-drain logic output that is pulled to ground when the to bypass the remote sense amplifier, or DIFFVOUT con-
output voltage is not within ±10% of the regulation point, nects to this pin when the remote sense amplifier is used.
after a 25µs power bad mask timer expires. VOUT_LCL can be connected to VOUT on the LTM4601-1,
VOUT is internally connected to VOUT_LCL with 50Ω in the
LTM4601-1.
4601fe

LTM4601/LTM4601-1
Simplified Block Diagram
VIN VOUT_LCL
VOUT
>1.9V = ON 1M
R1 <1V = OFF (50Ω, LTM4601-1)
UVLO MAX = 5V RUN VIN
FUNCTION PGOOD 5.1V
+ 4.5V TO 20V
R2 1.5µF CIN
COMP ZENER
60.4k
INTERNAL
COMP
Q1
POWER CONTROL
SGND
0.47µH VOUT
MARG1 1.5V
12A
MARG0 22µF
VFB
50k 50k
fSET
+
RSET Q2 COUT
40.2k
39.2k 2.2k PGND
MPGM
INTVCC
TRACK/SS 10k
CSS PLLIN 10k VOSNS–

– NOT INCLUDED
IN THE LTM4601-1
4.7µF 50k 10k VOSNS+
+ VOSNS– = NC1
INTVCC VOSNS+ = NC2
10k DIFFVOUT = NC3
DRVCC
DIFFVOUT
4601 F01
= SGND
= PGND
Figure 1. Simplified LTM4601/LTM4601-1 Block Diagram
Decoupling Requirements TA = 25°C, VIN = 12V. Use Figure 1 configuration.

CIN External Input Capacitor Requirement (VIN = IOUT = 12A, 3× 10µF Ceramics 20 30 µF
4.5V to 20V, VOUT = 1.5V)
COUT External Output Capacitor Requirement (VIN IOUT = 12A 100 200 µF
= 4.5V to 20V, VOUT = 1.5V)
4601fe

LTM4601/LTM4601-1
Operation
Power Module Description Pulling the RUN pin below 1V forces the controller into its
The LTM4601 is a standalone nonisolated switching mode shutdown state, turning off both Q1 and Q2. At low load
DC/DC power supply. It can deliver up to 12A of DC output current, the module works in continuous current mode by
current with some external input and output capacitors. default to achieve minimum output ripple voltage.
This module provides a precisely regulated output voltage When DRVCC pin is connected to INTVCC an integrated
programmable via one external resistor from 0.6VDC to 5V linear regulator powers the internal gate drivers. If a
5.0VDC over a 4.5V to 20V wide input voltage. The typical 5V external bias supply is applied on the DRVCC pin, then
application schematic is shown in Figure 18. an efficiency improvement will occur due to the reduced
power loss in the internal linear regulator. This is especially
The LTM4601 has an integrated constant on-time current
true at the high end of the input voltage range.
mode regulator, ultralow RDS(ON) FETs with fast switch-
ing speed and integrated Schottky diodes. The typical The LTM4601 has a very accurate differential remote
switching frequency is 850kHz at full load. With current sense amplifier with very low offset. This provides for
mode control and internal feedback loop compensation, very accurate output voltage sensing at the load. The
the LTM4601 module has sufficient stability margins and MPGM pin, MARG0 pin and MARG1 pin are used to sup-
good transient performance under a wide range of operat- port voltage margining, where the percentage of margin
ing conditions and with a wide range of output capacitors, is programmed by the MPGM pin, and the MARG0 and
even all ceramic output capacitors. MARG1 select margining.
Current mode control provides cycle-by-cycle fast current The PLLIN pin provides frequency synchronization of the
limit. Besides, foldback current limiting is provided in an device to an external clock. The TRACK/SS pin is used
overcurrent condition while VFB drops. Internal overvolt- for power supply tracking and soft-start programming.
age and undervoltage comparators pull the open-drain
PGOOD output low if the output feedback voltage exits a
±10% window around the regulation point. Furthermore,
in an overvoltage condition, internal top FET Q1 is turned
off and bottom FET Q2 is turned on and held on until the
overvoltage condition clears.
4601fe

LTM4601/LTM4601-1
Applications Information
The typical LTM4601 application circuit is shown in Fig- The MPGM pin programs a current that when multiplied
ure 18. External component selection is primarily deter- by an internal 10k resistor sets up the 0.6V reference ±
mined by the maximum load current and output voltage. offset for margining. A 1.18V reference divided by the
Refer to Table 2 for specific external capacitor requirements RPGM resistor on the MPGM pin programs the current.
for a particular application. Calculate VOUT(MARGIN):
VIN to VOUT Step-Down Ratios %VOUT

VOUT(MARGIN) = • VOUT
100
There are restrictions in the maximum VIN to VOUT step
down ratio that can be achieved for a given input voltage. where %VOUT is the percentage of VOUT you want to
These constraints are shown in the Typical Performance margin, and VOUT(MARGIN) is the margin quantity in volts:
Characteristics curves labeled VIN to VOUT Step-Down
VOUT 1.18V
Ratio. Note that additional thermal derating may apply. See RPGM = • •10k
the Thermal Considerations and Output Current Derating 0.6V VOUT(MARGIN)
section of this data sheet.
where RPGM is the resistor value to place on the MPGM
Output Voltage Programming and Margining pin to ground.
The PWM controller has an internal 0.6V reference voltage. The margining voltage, VOUT(MARGIN), will be added or
As shown in the Block Diagram, a 1M and a 60.4k 0.5% subtracted from the nominal output voltage as determined
internal feedback resistor connects VOUT and VFB pins by the state of the MARG0 and MARG1 pins. See the truth
together. The VOUT_LCL pin is connected between the 1M table below:
and the 60.4k resistor. The 1M resistor is used to protect MARG1 MARG0 MODE
against an output overvoltage condition if the VOUT_LCL LOW LOW NO MARGIN
pin is not connected to the output, or if the remote sense LOW HIGH MARGIN UP
amplifier output is not connected to VOUT_LCL. In these HIGH LOW MARGIN DOWN
cases, the output voltage will default to 0.6V. Adding a HIGH HIGH NO MARGIN
resistor RSET from the VFB pin to SGND pin programs
the output voltage: Input Capacitors
60.4k +RSET LTM4601 module should be connected to a low AC imped-
VOUT = 0.6V •
RSET ance DC source. Input capacitors are required to be placed
adjacent to the module. In Figure 18, the 10µF ceramic input
Table 1. RSET Standard 1% Resistor Values vs VOUT capacitors are selected for their ability to handle the large
RSET RMS current into the converter. An input bulk capacitor
Open 60.4 40.2 30.1 25.5 19.1 13.3 8.25
(kΩ) of 100µF is optional. This 100µF capacitor is only needed
VOUT
0.6 1.2 1.5 1.8 2 2.5 3.3 5 if the input source impedance is compromised by long
(V)
inductive leads or traces.
4601fe

LTM4601/LTM4601-1
Applications information
For a buck converter, the switching duty-cycle can be Pick the corresponding duty cycle and the number of phases
estimated as: to arrive at the correct ripple current value. For example,
VOUT the 2-phase parallel LTM4601 design provides 24A at 2.5V
D= output from a 12V input. The duty cycle is DC = 2.5V/12V
VIN = 0.21. The 2-phase curve has a ratio of ~0.25 for a duty
Without considering the inductor ripple current, the RMS cycle of 0.21. This 0.25 ratio of RMS ripple current to a
current of the input capacitor can be estimated as: DC load current of 24A equals ~6A of input RMS ripple
current for the external input capacitors.
IOUT(MAX)
ICIN(RMS) = • D • (1–D) Output Capacitors
η%
The LTM4601 is designed for low output ripple voltage.
In the above equation, η% is the estimated efficiency of The bulk output capacitors defined as COUT are chosen
the power module. CIN can be a switcher-rated electrolytic with low enough effective series resistance (ESR) to meet
aluminum capacitor, OS-CON capacitor or high value ce- the output voltage ripple and transient requirements. COUT
ramic capacitor. Note the capacitor ripple current ratings can be a low ESR tantalum capacitor, a low ESR polymer
are often based on temperature and hours of life. This capacitor or a ceramic capacitor. The typical capacitance is
makes it advisable to properly derate the input capacitor, 200µF if all ceramic output capacitors are used. Additional
or choose a capacitor rated at a higher temperature than output filtering may be required by the system designer
required. Always contact the capacitor manufacturer for if further reduction of output ripple or dynamic transient
derating requirements. spikes is required. Table 2 shows a matrix of different
In Figure 18, the 10µF ceramic capacitors are together output voltages and output capacitors to minimize the
used as a high frequency input decoupling capacitor. In a voltage droop and overshoot during a 5A/µs transient.
typical 12A output application, three very low ESR, X5R or The table optimizes total equivalent ESR and total bulk
X7R, 10µF ceramic capacitors are recommended. These capacitance to maximize transient performance.
decoupling capacitors should be placed directly adjacent
0.6
to the module input pins in the PCB layout to minimize
the trace inductance and high frequency AC noise. Each 0.5
RMS INPUT RIPPLE CURRENT
10µF ceramic is typically good for 2A to 3A of RMS ripple 1-PHASE

2-PHASE
DC LOAD CURRENT
0.4
current. Refer to your ceramics capacitor catalog for the 3-PHASE
4-PHASE
RMS current ratings. 0.3 6-PHASE
12-PHASE
Multiphase operation with multiple LTM4601 devices in 0.2
parallel will lower the effective input RMS ripple current
due to the interleaving operation of the regulators. Appli- 0.1
cation Note 77 provides a detailed explanation. Refer to

0
Figure 2 for the input capacitor ripple current reduction as 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY CYCLE (VOUT/VIN)
a function of the number of phases. The figure provides 4601 F02
a ratio of RMS ripple current to DC load current as func-

Figure 2. Normalized Input RMS Ripple Current
tion of duty cycle and the number of paralleled phases. vs Duty Cycle for One to Six Modules (Phases)
4601fe

LTM4601/LTM4601-1
Multiphase operation with multiple LTM4601 devices in at low duty cycle and high output voltage can be reduced
parallel will lower the effective output ripple current due to by adding an external resistor from fSET to ground which
the interleaving operation of the regulators. For example, increases the frequency. If the duty cycle is DC = 2.5V/12V
each LTM4601’s inductor current in a 12V to 2.5V multi- = 0.21, the inductor ripple current for 2.5V output at 21%
phase design can be read from the Inductor Ripple Current duty cycle is ~6A in Figure 3.
vs Duty Cycle graph (Figure 3). The large ripple current
Figure 4 provides a ratio of peak-to-peak output ripple cur-
12 rent to the inductor current as a function of duty cycle and
2.5V OUTPUT the number of paralleled phases. Pick the corresponding
10 5V OUTPUT
duty cycle and the number of phases to arrive at the correct
1.8V OUTPUT
8 1.5V OUTPUT
output ripple current ratio value. If a 2-phase operation is
1.2V OUTPUT chosen at a duty cycle of 21%, then 0.6 is the ratio. This
IL (A)
6 3.3V OUTPUT WITH 0.6 ratio of output ripple current to inductor ripple of 6A
130k ADDED FROM
4
VOUT TO fSET equals 3.6A of effective output ripple current. Refer to
5V OUTPUT WITH
100k ADDED FROM
Application Note 77 for a detailed explanation of output
2 fSET TO GND ripple current reduction as a function of paralleled phases.
0 The output ripple voltage has two components that are
0 0.2 0.4 0.6 0.8
DUTY CYCLE (VOUT/VIN)
related to the amount of bulk capacitance and effective
4601 F03 series resistance (ESR) of the output bulk capacitance.
Figure 3. Inductor Ripple Current vs Duty Cycle
1.00
0.95 1-PHASE
2-PHASE
0.90
3-PHASE
0.85 4-PHASE
6-PHASE
0.80
PEAK-TO-PEAK OUTPUT RIPPLE CURRENT
0.75
0.70
0.65
0.60
DIr
0.55
0.50
0.45
0.40
0.35
0.30
RATIO =
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VO/VIN)
4601 F04
Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI, Dlr = Each Phase’s Inductor Current
4601fe

LTM4601/LTM4601-1
Therefore, the output ripple voltage can be calculated with Output Voltage Tracking
the known effective output ripple current. The equation:
Output voltage tracking can be programmed externally
ΔVOUT(P-P) ≈ (ΔIL/(8 • f • m • COUT) + ESR • ΔIL), where f
using the TRACK/SS pin. The output can be tracked up and
is frequency and m is the number of parallel phases. This
down with another regulator. The master regulator’s output
calculation process can be easily accomplished by using
is divided down with an external resistor divider that is the
LTpowerCAD™.
same as the slave regulator’s feedback divider. Figure 5
Fault Conditions: Current Limit and Overcurrent shows an example of coincident tracking. Ratiometric
Foldback modes of tracking can be achieved by selecting different
resistor values to change the output tracking ratio. The
LTM4601 has a current mode controller, which inher- master output must be greater than the slave output for
ently limits the cycle-by-cycle inductor current not only in the tracking to work. Figure 6 shows the coincident output
steady-state operation, but also in response to transients. tracking characteristics.
To further limit current in the event of an overload condi- MASTER
OUTPUT
tion, the LTM4601 provides foldback current limiting. If the R2
output voltage falls by more than 50%, then the maximum TRACK CONTROL 60.4k
VIN
output current is progressively lowered to about one sixth R1
of its full current limit value. 100k
40.2k
VIN PLLIN TRACK/SS
PGOOD VOUT SLAVE OUTPUT
Soft-Start and Tracking MPGM VFB COUT
RUN MARG0
The TRACK/SS pin provides a means to either soft-start COMP MARG1
LTM4601
the regulator or track it to a different power supply. A CIN
INTVCC VOUT_LCL
capacitor on this pin will program the ramp rate of the DRVCC DIFFVOUT
VOSNS+
output voltage. A 1.5µA current source will charge up the VOSNS–
external soft-start capacitor to 80% of the 0.6V internal SGND PGND fSET
RSET
voltage reference plus or minus any margin delta. This will 40.2k
4601 F05
control the ramp of the internal reference and the output

voltage. The total soft-start time can be calculated as:
Figure 5. Coincident Tracking Schematic
(
t SOFTSTART = 0.8 • 0.6V ± VOUT(MARGIN) ) C
• SS
1.5µA
When the RUN pin falls below 1.5V, then the TRACK/SS MASTER OUTPUT
pin is reset to allow for proper soft-start control when the

regulator is enabled again. Current foldback and forced SLAVE OUTPUT
continuous mode are disabled during the soft-start pro- OUTPUT
VOLTAGE
cess. The soft-start function can also be used to control
the output ramp up time, so that another regulator can
be easily tracked to it.
4601 F06
TIME
Figure 6. Coincident Output Tracking Characteristics
4601fe

LTM4601/LTM4601-1
Run Enable INTVCC and DRVCC Connection
The RUN pin is used to enable the power module. The An internal low dropout regulator produces an internal
pin has an internal 5.1V Zener to ground. The pin can be 5V supply that powers the control circuitry and DRVCC
driven with a logic input not to exceed 5V. for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4601
The RUN pin can also be used as an undervoltage lock out
can be directly powered by VIN. The gate driver current
(UVLO) function by connecting a resistor divider from the
through the LDO is about 20mA. The internal LDO power
input supply to the RUN pin:
dissipation can be calculated as:
R1+R2 PLDO_LOSS = 20mA • (VIN – 5V)
VUVLO = •1.5V
R2
The LTM4601 also provides the external gate driver volt-
See Figure 1, Simplified Block Diagram. age pin DRVCC. If there is a 5V rail in the system, it is
recommended to connect DRVCC pin to the external 5V
Power Good rail. This is especially true for higher input voltages. Do
The PGOOD pin is an open-drain pin that can be used to not apply more than 6V to the DRVCC pin. A 5V output can
monitor valid output voltage regulation. This pin monitors be used to power the DRVCC pin with an external circuit
a ±10% window around the regulation point and tracks as shown in Figure 16.
with margining.
Parallel Operation of the Module
COMP Pin The LTM4601 device is an inherently current mode con-
This pin is the external compensation pin. The module trolled device. Parallel modules will have very good current
has already been internally compensated for most output sharing. This will balance the thermals on the design. The
voltages. Table 2 is provided for most application require- voltage feedback equation changes with the variable N as
ments. LTpowerCAD is available for other control loop modules are paralleled:
optimization. 60.4k
+RSET
PLLIN VOUT = 0.6V N
RSET
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase N is the number of paralleled modules.
detector. This allows the internal top MOSFET turn-on Figure 19 shows an LTM4601 and an LTM4601-1 used in a
to be locked to the rising edge of an external clock. The parallel design. The 2nd LTM4601 device does not require
frequency range is ±30% around the operating frequency the remote sense amplifier, therefore, the LTM4601-1 device
of 850kHz. A pulse detection circuit is used to detect a is used. An LTM4601 device can be used without the diff
clock on the PLLIN pin to turn on the phase-locked loop. amp. VOSNS+ can be tied to ground and the VOSNS– can be
The pulse width of the clock has to be at least 400ns and tied to INTVCC. DIFFVOUT can float. When using multiple
at least 2V in amplitude. The PLLIN pin must be driven LTM4601-1 devices in parallel with an LTM4601, limit the
from a low impedance source such as a logic gate located number to five for a total of six modules in parallel.
close to the pin. During the start-up of the regulator, the
phase-locked loop function is disabled.
4601fe

LTM4601/LTM4601-1
Thermal Considerations and Output Current Derating or below for the derating curves. The maximum case
The power loss curves in Figures 7 and 8 can be used temperature of 100°C is to allow for a rise of about 13°C
in coordination with the load current derating curves in to 25°C inside the µModule with a thermal resistance θJC
from junction to case between 6°C/W to 9°C/W. This will
Figures 9 to 14 for calculating an approximate θJA for the
module with various heat sinking methods. Thermal models maintain the maximum junction temperature inside the
are derived from several temperature measurements at µModule regulator below 125°C.
the bench and thermal modeling analysis. Thermal Ap- Safety Considerations
plication Note 103 provides a detailed explanation of the The LTM4601 modules do not provide isolation from
analysis for the thermal models and the derating curves. VIN to VOUT. There is no internal fuse. If required, a
Tables 3 and 4 provide a summary of the equivalent θJA slow blow fuse with a rating twice the maximum input
for the noted conditions. These equivalent θJA parameters
current needs to be provided to protect each unit from
are correlated to the measured values, and are improved
catastrophic failure.
with air flow. The case temperature is maintained at 100°C
5.0 6
4.5
5
4.0
3.5
4
POWER LOSS (W)
POWER LOSS (W)
20VIN
3.0 12VIN
20VIN
2.5 3
2.0 12VIN
2
1.5
5VIN
1.0
1
0.5
0 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12
LOAD CURRENT (A) LOAD CURRENT (A)
4601 F07 4601 F08
Figure 7. 1.5V Power Loss Figure 8. 3.3V Power Loss
12 12
10 10
MAXIMUM LOAD CURRENT (A)
8 8
6 6
4 4
2 5VIN, 1.5VOUT 0LFM 2 5VIN, 1.5VOUT 0LFM

5VIN, 1.5VOUT 200LFM 5VIN, 1.5VOUT 200LFM
0 0
50 60 70 80 90 100 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4600 F09 4601 F10
Figure 9. No Heat Sink 5VIN Figure 10. BGA Heat Sink 5VIN
4601fe

LTM4601/LTM4601-1
12 12
10 10

8 8
6 6
4 4
2 5VIN, 1.5VOUT 0LFM 2 5VIN, 1.5VOUT 0LFM

0 0
50 60 70 80 90 100 50 60 70 80 90 100
4601 F11 4601 F12
Figure 11. No Heat Sink 12VIN Figure 12. BGA Heat Sink 12VIN
12 12
10 10
8 8
6 6
4 4
2 0LFM 2 0LFM
200LFM 200LFM
400LFM 400LFM
0 0
40 60 80 100 40 60 80 100
4601 F13 4601 F14
Figure 13. 12VIN, 3.3VOUT, No Heat Sink Figure 14. 12VIN, 3.3VOUT, BGA Heat Sink
4601fe

LTM4601/LTM4601-1
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18), 0A to 6A Load Step
TYPICAL MEASURED VALUES
COUT1 VENDORS PART NUMBER COUT2 VENDORS PART NUMBER
TDK C4532X5R0J107MZ (100µF, 6.3V) SANYO POS CAP 6TPE330MIL (330µF, 6.3V)
TAIYO YUDEN JMK432BJ107MU-T ( 100µF, 6.3V) SANYO POS CAP 2R5TPE470M9 (470µF, 2.5V)
TAIYO YUDEN JMK316BJ226ML-T501 ( 22µF, 6.3V) SANYO POS CAP 4TPE470MCL (470µF, 4V)
VOUT CIN CIN COUT1 COUT2 VIN DROOP PEAK TO RECOVERY LOAD STEP RSET
(V) (CERAMIC) (BULK) (CERAMIC) (BULK) CCOMP C3 (V) (mV) PEAK (mV) TIME (µs) (A/µs) (kΩ)
1.2 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 47pF 5 70 140 30 6 60.4
1.2 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 5 35 70 20 6 60.4
1.2 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 40 93 30 6 60.4
2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 5 57 116 30 6 19.1
2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 12 51 102 30 6 19.1
5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 15 188 375 25 6 8.25
5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 20 159 320 25 6 8.25
4601fe

LTM4601/LTM4601-1
Table 3. 1.5V Output at 12A
DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (°C/W) LGA qJA (°C/W) BGA
Figures 9, 11 5, 12 Figure 7 0 None 15.2 15.7
Figures 9, 11 5, 12 Figure 7 200 None 14 14.5
Figures 9, 11 5, 12 Figure 7 400 None 12 12.5
Figures 10, 12 5, 12 Figure 7 0 BGA Heat Sink 13.9 14.4
Table 4. 3.3V Output at 12A

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK qJA (°C/W) LGA qJA (°C/W) BGA
Figure 13 12 Figure 8 0 None 15.2 15.7
Figure 14 12 Figure 8 0 BGA Heat Sink 13.9 14.4
Heat Sink Manufacturer

Aavid Thermalloy Part No: 375424B00034G Phone: 603-224-9988
4601fe

LTM4601/LTM4601-1
Layout Checklist/Example
The high integration of LTM4601 makes the PCB board • Use a separated SGND copper area for components
layout very simple and easy. However, to optimize its electri- connected to signal pins. Connect the SGND to PGND
cal and thermal performance, some layout considerations underneath the unit.
are still necessary.
Figure 15 gives a good example of the recommended layout.
• Use large PCB copper areas for high current path, in-
cluding VIN, PGND and VOUT. It helps to minimize the Frequency Adjustment
PCB conduction loss and thermal stress. The LTM4601 is designed to typically operate at 850kHz
• Place high frequency ceramic input and output capaci- across most input conditions. The fSET pin is normally
tors next to the VIN, PGND and VOUT pins to minimize left open. The switching frequency has been optimized
high frequency noise. for maintaining constant output ripple noise over most
operating ranges. The 850kHz switching frequency and
• Place a dedicated power ground layer underneath the
the 400ns minimum off time can limit operation at higher
unit. Refer frequency synchronization source to power
duty cycles like 5V to 3.3V, and produce excessive induc-
ground. tor ripple currents for lower duty cycle applications like
• To minimize the via conduction loss and reduce module 20V to 5V. The 5VOUT and 3.3VOUT drop out curves are
thermal stress, use multiple vias for interconnection modified by adding an external resistor on the fSET pin to
between top layer and other power layers. allow for lower input voltage operation, or higher input
voltage operation.
• Do not put vias directly on pads unless they are capped.
VIN
CIN CIN
GND
SIGNAL
GND
COUT COUT
VOUT
4601 F15
Figure 15. Recommended Layout (LGA and BGA PCB Layouts Are Identical
with the Exception of Circle Pads for BGA, See Package Description.)
4601fe

LTM4601/LTM4601-1
Example for 5V Output Example for 3.3V Output
LTM4601 minimum on-time = 100ns LTM4601 minimum on-time = 100ns
tON = ((VOUT • 10pF)/IfSET), for VOUT > 4.8V use 4.8V. tON = ((VOUT • 10pF)/IfSET)
LTM4601 minimum off-time = 400ns LTM4601 minimum off-time = 400ns
tOFF = t – tON, where t = 1/Frequency tOFF = t – tON, where t = 1/Frequency
Duty Cycle = tON/t or VOUT/VIN Duty Cycle (DC) = tON/t or VOUT/VIN
Equations for setting frequency: Equations for setting frequency:
IfSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 170µA, IfSET = (VIN /(3 • RfSET)), for 20V operation, IfSET = 170µA,
tON = ((4.8 • 10pF)/IfSET), tON = 282ns, where the internal tON = ((3.3 • 10pf)/IfSET), tON = 195ns, where the internal
RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20 RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/
• 282ns)) ~ 886kHz. The inductor ripple current begins (20 • 195ns)) ~ 846kHz. The minimum on-time and mini-
to get high at the higher input voltages due to a larger mum off-time are within specification at 195ns and 980ns.
voltage across the inductor. This is noted in the Inductor The 4.5V minimum input for converting 3.3V output will
Ripple Current vs Duty Cycle graph (Figure 3) where IL ≈ not meet the minimum off-time specification of 400ns.
10A at 25% duty cycle. The inductor ripple current can be tON = 868ns, Frequency = 850kHz, tOFF = 315ns.
lowered at the higher input voltages by adding an external
resistor from fSET to ground to increase the switching Solution
frequency. An 8A ripple current is chosen, and the total Lower the switching frequency at lower input voltages to
peak current is equal to 1/2 of the 8A ripple current plus allow for higher duty cycles, and meet the 400ns minimum
the output current. The 5V output current is limited to 8A, off-time at 4.5V input voltage. The off-time should be about
so the total peak current is less than 12A. This is below the 500ns, which includes a 100ns guard band. The duty cycle
14A peak specified value. A 100k resistor is placed from for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/tOFF or
fSET to ground, and the parallel combination of 100k and (1 – 0.73)/500ns = 540kHz. The switching frequency
39.2k equates to 28k. The IfSET calculation with 28k and needs to be lowered to 540kHz at 4.5V input. tON = DC/
20V input voltage equals 238µA. This equates to a tON of frequency, or 1.35µs. The fSET pin voltage is 1/3 of VIN, and
200ns. This will increase the switching frequency from the IfSET current equates to 38µA with the internal 39.2k.
~886kHz to ~1.25MHz for the 20V to 5V conversion. The The IfSET current needs to be 24µA for 540kHz opera-
minimum on-time is above 100ns at 20V input. Since tion. A resistor can be placed from VOUT to fSET to lower
the switching frequency is approximately constant over the effective IfSET current out of the fSET pin to 24µA.
input and output conditions, then the lower input voltage The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore
range is limited to 10V for the 1.25MHz operation due to 130k will source 14µA into the fSET node and lower the
the 400ns minimum off-time. Equation: tON = (VOUT/VIN) IfSET current to 24µA. This enables the 540kHz operation
• (1/Frequency) equates to a 400ns on-time, and a 400ns and the 4.5V to 20V input operation for down converting to
off-time. The VIN to VOUT Step-Down Ratio curve reflects 3.3V output. The frequency will scale from 540kHz to 1.1
an operating range of 10V to 20V for 1.25MHz operation MHz over this input range. This provides for an effective
with a 100k resistor to ground, and an 8V to 16V operation output current of 8A over the input range.
for fSET floating. These modifications are made to provide
wider input voltage ranges for the 5V output designs while
limiting the inductor ripple current, and maintaining the
400ns minimum off-time.
4601fe

LTM4601/LTM4601-1
VOUT
TRACK/SS CONTROL
VIN
10V TO 20V REVIEW TEMPERATURE
R2 R4
100k 100k VIN PLLIN TRACK/SS DERATING CURVE VOUT
PGOOD VOUT 5V
C3 100pF + COUT1 8A
MPGM VFB 100µF
RUN MARG0 6.3V REFER TO
SANYO POSCAP TABLE 2
COMP MARG1
LTM4601-1
INTVCC VOUT_LCL
5% MARGIN
DRVCC NC3
R1 NC1
392k
CIN 1% NC2
10µF SGND PGND fSET
25V
×2 RfSET RSET
100k 8.25k
MARGIN CONTROL
IMPROVE
EFFICIENCY SOT-323
FOR ≥12V INPUT
DUAL
CMSSH-3C3 4601 F16
Figure 16. 5V at 8A Design Without Differential Amplifier
VOUT
VIN TRACK/SS CONTROL
4.5V TO 16V
R2 R4 REVIEW TEMPERATURE
PGOOD VOUT 3.3V
C3 100pF 10A
PGOOD MPGM VFB
RUN MARG0 COUT1
+ 100µF
COMP MARG1
LTM4601 6.3V
INTVCC VOUT_LCL
SANYO POSCAP
DRVCC DIFFVOUT
CIN
10µF R1 VOSNS+
25V 392k VOSNS–
×3 SGND PGND fSET RfSET
130k RSET
13.3k
5% MARGIN MARGIN CONTROL 4601 F17
Figure 17. 3.3V at 10A Design
4601fe

LTM4601/LTM4601-1
CLOCK SYNC
VOUT C5
VIN 0.01µF
4.5V TO 20V
R2 R4 REVIEW TEMPERATURE
PGOOD VOUT 1.5V
C3 100pF 12A
PGOOD MPGM VFB COUT1 + COUT2
100µF 470µF
RUN MARG0 MARGIN
ON/OFF 6.3V 6.3V
COMP MARG1 CONTROL
LTM4601
INTVCC VOUT_LCL
DRVCC DIFFVOUT
CIN + R1 VOSNS+
BULK
OPT CIN
392k VOSNS– REFER TO
10µF SGND PGND fSET TABLE 2 FOR
RSET
25V DIFFERENT
40.2k
×3 CER OUTPUT
VOLTAGE
4601 F18
5% MARGIN
Figure 18. Typical 4.5V to 20V, 1.5V at 12A Design
60.4k + R
SET
VOUT N
VOUT = 0.6V
CLOCK SYNC RSET
VIN 0° PHASE TRACK/SS CONTROL N = NUMBER OF PHASES
4.5V TO 20V
R2 R4
100k 100k VIN PLLIN TRACK/SS VOUT
PGOOD VOUT 1.5V
C6 220pF 24A
MPGM VFB C3
22µF
RUN MARG0
6.3V
COMP MARG1 +
LTM4601 C4
INTVCC VOUT_LCL 470µF
+ C5*
DRVCC DIFFVOUT 6.3V
C1 100µF
0.1µF 25V VOSNS+
LTC6908-1 REFER TO
C2 VOSNS–
1 6 TABLE 2
118k V+ OUT1 10µF R1 SGND PGND fSET
1% 392k RSET 100pF
2 5 25V
GND OUT2 20k
×2
3 4
SET MOD
5% MARGIN
2-PHASE MARGIN CONTROL
OSCILLATOR
CLOCK SYNC
180° PHASE
4.5V TO 20V TRACK/SS CONTROL
C7
0.033µF
VIN PLLIN TRACK/SS

PGOOD PGOOD VOUT
C3 + C4
MPGM VFB 22µF 470µF
C8 RUN MARG0 6.3V 6.3V
10µF
25V COMP MARG1
LTM4601-1 REFER TO
×2 INTVCC VOUT_LCL
TABLE 2
DRVCC NC3
NC2
392k NC1
SGND PGND fSET
4601 F19
*C5 OPTIONAL TO REDUCE ANY LC RINGING.

NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION
Figure 19. 2-Phase Parallel, 1.5V at 24A Design

4601fe

24
4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Coincident Tracking
8V TO 16V
–48V INTERMEDIATE R17 C26

INPUT BUS 59k 0.1µF
LTC6902
V+ SET
4-PHASE DIV MOD
OSCILLATOR PH GND
CLOCK SYNC 1
OUT1 OUT4
OUT2 OUT3 3.3V R23
CLOCK SYNC 2 60.4k
3.3V 3.3V
TRACK/SS
8V TO 16V 8V TO 16V R24
CONTROL
Typical Applications
19.1k
C7 R10 R11
R6 R7 0.15µF
LTM4601/LTM4601-1
100k 100k VIN PLLIN TRACK/SS 100k 100k VIN PLLIN TRACK/SS
3.3V AT 10A 2.5V AT 12A
PGOOD VOUT PGOOD VOUT
C12 100pF C18 100pF
PGOOD MPGM VFB C9 + C10 PGOOD MPGM VFB C16 + C15
22µF 470µF 22µF 470µF
RUN MARG0 MARGIN RUN MARG0 MARGIN
ON/OFF 6.3V 6.3V ON/OFF 6.3V 6.3V
COMP MARG1 CONTROL COMP MARG1 CONTROL
LTM4601 LTM4601
C11 INTVCC VOUT_LCL REFER TO INTVCC VOUT_LCL REFER TO
+ 100µF DRVCC DIFFVOUT TABLE 2 DRVCC DIFFVOUT TABLE 2
C14
35V R27 VOSNS+ 10µF R9 VOSNS+
OPT 392k VOSNS– 25V 392k VOSNS–
C8
10µF fSET ×3 fSET
SGND PGND R8 SGND PGND R18
25V 13.3k 19.1k
×3
5% MARGIN 5% MARGIN
R25
CLOCK SYNC 3 CLOCK SYNC 4 60.4k
3.3V
3.3V R21 3.3V
60.4k R26
8V TO 16V 8V TO 16V
3.3V 40.2k
R19
R15 R16
For more information www.linear.com/LTM4601

R2 R3 30.1k
100k 100k VIN PLLIN TRACK/SS 100k 100k VIN PLLIN TRACK/SS
1.8V AT 12A 1.5V AT 12A
PGOOD VOUT PGOOD VOUT
C8 100pF C24 100pF
PGOOD MPGM VFB C3 + C4 PGOOD MPGM VFB C16 + C15
22µF 470µF 22µF 470µF
RUN MARG0 MARGIN RUN MARG0 MARGIN
ON/OFF 6.3V 6.3V ON/OFF 6.3V 6.3V
COMP MARG1 CONTROL COMP MARG1 CONTROL
LTM4601 LTM4601
INTVCC VOUT_LCL REFER TO INTVCC VOUT_LCL REFER TO
DRVCC DIFFVOUT TABLE 2 DRVCC DIFFVOUT TABLE 2
C2 C14
10µF R1 VOSNS+ 10µF R14 VOSNS+
25V 392k VOSNS– 25V 392k VOSNS–
×3 fSET ×3 fSET
SGND PGND R12 SGND PGND R13
30.1k 40.2k
4601 TA02
5% MARGIN 5% MARGIN
4601fe
LGA Package
118-Lead (15mm × 15mm × 2.82mm)
(Reference LTC DWG # 05-08-1801 Rev B) DETAIL A SEE NOTES
7
A M L K J H G F E D C B A
aaa Z
12
b 11
10
8
MOLD
CAP SUBSTRATE
7
F
D
6
H1
H2
5
Package Description
Z
PIN “A1” 4
bbb Z
CORNER DETAIL B
4 3
2
0.630 ±0.025 SQ. 118x e
1
eee S X Y
X
SEE NOTES b e C(0.30)
E Y PAD 1
DETAIL B 3 G
PACKAGE TOP VIEW PACKAGE SIDE VIEW
aaa Z
PACKAGE BOTTOM VIEW
NOTES:
DETAIL A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
0.0000
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
3 LAND DESIGNATION PER JESD MO-222, SPP-010
6.9850 4 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
DIMENSIONS
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
0.630 ±0.025 Ø 118x 5.7150 SYMBOL MIN NOM MAX NOTES THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR

A 2.72 2.82 2.92 MARKED FEATURE
4.4450
b 0.60 0.63 0.66 5. PRIMARY DATUM -Z- IS SEATING PLANE
3.1750 D 15.00
6. THE TOTAL NUMBER OF PADS: 118
1.9050
E 15.00
e 1.27 7 PACKAGE ROW AND COLUMN LABELING MAY VARY
0.6350
! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
F 13.97 LAYOUT CAREFULLY
0.0000
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
0.6350 G 13.97
H1 0.27 0.32 0.37
1.9050
H2 2.45 2.50 2.55
3.1750 aaa 0.15
bbb 0.10
4.4450
eee 0.05
5.7150 TOTAL NUMBER OF LGA PADS: 118 LTMXXXXXX
µModule
6.9850
COMPONENT
PIN “A1”
SUGGESTED PCB LAYOUT

TOP VIEW TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION LGA 118 1212 REV B
25
4601fe
LTM4601/LTM4601-1
26
BGA Package
118-Lead (15mm × 15mm × 3.42mm)
(Reference LTC DWG # 05-08-1903 Rev B)
Z DETAIL A SEE NOTES
A
7
A2 M L K J H G F E D C B A
aaa Z
12
A1 b 11
ccc Z 10
8
MOLD b1
CAP 7
F
D
SUBSTRATE 6
0.27 – 0.37
Package Description
2.45 – 2.55 5
LTM4601/LTM4601-1
4
PIN “A1” DETAIL B
// bbb Z
CORNER 3
4
2
e
Øb (118 PLACES)
1
ddd M Z X Y
X eee M Z
SEE NOTES b e PIN 1
E Y
DETAIL B 3 G
PACKAGE TOP VIEW PACKAGE SIDE VIEW
aaa Z
PACKAGE BOTTOM VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A 2. ALL DIMENSIONS ARE IN MILLIMETERS
0.0000
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
3 BALL DESIGNATION PER JESD MS-028 AND JEP95
6.9850 DIMENSIONS 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
SYMBOL MIN NOM MAX NOTES BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
0.630 ±0.025 Ø 118x 5.7150 THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

A 3.22 3.42 3.62
MARKED FEATURE
4.4450 A1 0.50 0.60 0.70
A2 2.72 2.82 2.92 5. PRIMARY DATUM -Z- IS SEATING PLANE
3.1750
b 0.60 0.75 0.90 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
1.9050 b1 0.60 0.63 0.66
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
D 15.0 ! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.6350
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
0.0000 E 15.0 LAYOUT CAREFULLY

0.6350 e 1.27
F 13.97
1.9050
G 13.97
3.1750 aaa 0.15
4.4450
bbb 0.10
ccc 0.20
5.7150 LTMXXXXXX
ddd 0.30
µModule
6.9850 eee 0.15
COMPONENT
TOTAL NUMBER OF BALLS: 118 PIN “A1”
SUGGESTED PCB LAYOUT

TOP VIEW TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION BGA 118 1112 REV B
4601fe
LTM4601/LTM4601-1
Package Description
Table 5. Pin Assignment (Arranged by Pin Number)
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VIN B1 VIN C1 VIN D1 PGND E1 PGND F1 PGND
A7 INTVCC B7 – C7 – D7 – E7 PGND F7 PGND
A8 PLLIN B8 – C8 – D8 – E8 – F8 PGND
A9 TRACK/SS B9 – C9 – D9 – E9 – F9 PGND
A10 RUN B10 – C10 – D10 – E10 – F10 –
A11 COMP B11 – C11 – D11 – E11 – F11 –
A12 MPGM B12 fSET C12 MARG0 D12 MARG1 E12 DRVCC F12 VFB
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 PGND H1 PGND J1 VOUT K1 VOUT L1 VOUT M1 VOUT
G10 – H10 – J10 VOUT K10 VOUT L10 VOUT M10 VOUT
G11 – H11 – J11 – K11 VOUT L11 VOUT M11 VOUT
G12 PGOOD H12 SGND J12 VOSNS+/NC2* K12 DIFFVOUT/NC2* L12 VOUT_LCL M12 VOSNS–/NC1*
*LTM4601-1 Only
4601fe

LTM4601/LTM4601-1
Package Description
Table 6. Pin Assignment (Arranged by Pin Function)
PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME
A1 VIN D1 PGND J1 VOUT A7 INTVCC B7 -
A2 VIN D2 PGND J2 VOUT A8 PLLIN B8 -
A3 VIN D3 PGND J3 VOUT A9 TRACK/SS B9 -
A4 VIN D4 PGND J4 VOUT A10 RUN B10 -
A5 VIN D5 PGND J5 VOUT A11 COMP B11 -
A6 VIN D6 PGND J6 VOUT A12 MPGM C7 -
B1 VIN E1 PGND J7 VOUT B12 fSET C8 -
B2 VIN E2 PGND J8 VOUT C9 -
J9 VOUT C12 MARG0
B3 VIN E3 PGND C10 -
B4 VIN E4 PGND J10 VOUT D12 MARG1 C11 -
B5 VIN E5 PGND K1 VOUT E12 DRVCC D7 -
B6 VIN E6 PGND K2 VOUT D8 -
E7 PGND K3 VOUT F12 VFB
C1 VIN D9 -
C2 VIN F1 PGND K4 VOUT G12 PGOOD D10 -
C3 VIN F2 PGND K5 VOUT D11 -
K6 VOUT H12 SGND
C4 VIN F3 PGND E8 -
C5 VIN F4 PGND K7 VOUT J12 VOSNS+/NC2*
K8 VOUT E9 -
C6 VIN F5 PGND K12 DIFFVOUT/NC3* E10 -
F6 PGND K9 VOUT
K10 VOUT L12 VOUT_LCL E11 -
F7 PGND
F8 PGND K11 VOUT F10 -
M12 VOSNS–/NC1*
F9 PGND L1 VOUT F11 -
*LTM4601-1 Only
G1 PGND L2 VOUT G10 -
G2 PGND L3 VOUT G11 -
G3 PGND L4 VOUT
L5 VOUT H10 -
G4 PGND H11 -
G5 PGND L6 VOUT
G6 PGND L7 VOUT J11 -
G7 PGND L8 VOUT
G8 PGND L9 VOUT
G9 PGND L10 VOUT
L11 VOUT
H1 PGND
H2 PGND M1 VOUT
H3 PGND M2 VOUT
H4 PGND M3 VOUT
H5 PGND M4 VOUT
H6 PGND M5 VOUT
H7 PGND M6 VOUT
H8 PGND M7 VOUT
H9 PGND M8 VOUT
M9 VOUT
M10 VOUT
M11 VOUT
4601fe

LTM4601/LTM4601-1
Revision History (Revision history begins at Rev B)
REV DATE DESCRIPTION PAGE NUMBER

B 01/10 Added Note 5 2, 4
C 03/12 Revised entire data sheet to include the BGA package. 1 to 30
D 02/14 Added SnPb BGA option 1, 2
E 04/14 Added LTM4601-1 BGA package diagram and package information 2
4601fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of its information www.linear.com/LTM4601
circuits as described herein will not infringe on existing patent rights. 29
LTM4601/LTM4601-1
Package Photo
15mm 2.82mm 15mm 3.42mm
15mm 15mm
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PART NUMBER DESCRIPTION COMMENTS
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Amplifier, 15mm × 15mm × 4.32mm LGA
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15mm × 15mm × 3.42mm BGA
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®
This product contains technology licensed from Silicon Semiconductor Corporation. 4601fe
30 Linear Technology Corporation LT 0414 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM4601  LINEAR TECHNOLOGY CORPORATION 2007

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LTM4601/LTM4601-1

12A µModule Regulators

Typical Application Efficiency and Power Loss

For more information www.linear.com/LTM4601 1

VIN fSET VIN fSET

LGA PACKAGE BGA PACKAGE

2 For more information www.linear.com/LTM4601

For more information www.linear.com/LTM4601 3

4 For more information www.linear.com/LTM4601

1.2V Transient Response 1.5V Transient Response 1.8V Transient Response

VOUT VOUT VOUT

20µs/DIV 4601 G04 20µs/DIV 4601 G05

2.5V Transient Response 3.3V Transient Response

20µs/DIV 4601 G07 20µs/DIV 4601 G08

2.5V AT 6A/µs LOAD STEP 3.3V AT 6A/µs LOAD STEP

For more information www.linear.com/LTM4601 5

5ms/DIV 4601 G09 2ms/DIV 4601 G10

VIN = 12V VIN = 12V

VIN to VOUT Step-Down Ratio Track, IOUT = 12A

1.5 2.5V OUTPUT VIN = 12V

Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 12A

50µs/DIV 4601 G13

VIN = 12V VIN = 12V

6 For more information www.linear.com/LTM4601

For more information www.linear.com/LTM4601 7

8 For more information www.linear.com/LTM4601

CSS PLLIN 10k VOSNS–

Figure 1. Simplified LTM4601/LTM4601-1 Block Diagram

Decoupling Requirements TA = 25°C, VIN = 12V. Use Figure 1 configuration.

For more information www.linear.com/LTM4601 9

10 For more information www.linear.com/LTM4601

VIN to VOUT Step-Down Ratios %VOUT

For more information www.linear.com/LTM4601 11

10µF ceramic is typically good for 2A to 3A of RMS ripple 1-PHASE

cation Note 77 provides a detailed explanation. Refer to

a ratio of RMS ripple current to DC load current as func-

12 For more information www.linear.com/LTM4601

For more information www.linear.com/LTM4601 13

control the ramp of the internal reference and the output

pin is reset to allow for proper soft-start control when the

Figure 6. Coincident Output Tracking Characteristics

14 For more information www.linear.com/LTM4601

For more information www.linear.com/LTM4601 15

Figure 7. 1.5V Power Loss Figure 8. 3.3V Power Loss

2 5VIN, 1.5VOUT 0LFM 2 5VIN, 1.5VOUT 0LFM

16 For more information www.linear.com/LTM4601

MAXIMUM LOAD CURRENT (A)

2 5VIN, 1.5VOUT 0LFM 2 5VIN, 1.5VOUT 0LFM

MAXIMUM LOAD CURRENT (A)

For more information www.linear.com/LTM4601 17

18 For more information www.linear.com/LTM4601

Table 4. 3.3V Output at 12A

Heat Sink Manufacturer

For more information www.linear.com/LTM4601 19

20 For more information www.linear.com/LTM4601

For more information www.linear.com/LTM4601 21

Figure 16. 5V at 8A Design Without Differential Amplifier

5% MARGIN MARGIN CONTROL 4601 F17

Figure 17. 3.3V at 10A Design