LTC3418

8A, 4MHz, Monolithic

Synchronous Step-Down
Regulator
Features Description
n High Efficiency: Up to 95% The LTC®3418 is a high efficiency, monolithic synchronous
n 8A Output Current step-down DC/DC converter utilizing a constant frequency,
n 2.25V to 5.5V Input Voltage Range current mode architecture. It operates from an input voltage
n Low RDS(ON) Internal Switch: 35mΩ range of 2.25V to 5.5V and provides a regulated output
n Tracking Input to Provide Easy Supply Sequencing voltage from 0.8V to 5V while delivering up to 8A of output
n Programmable Frequency: 300kHz to 4MHz current. The internal synchronous power switch increases
n 0.8V ±1% Reference Allows Low Output Voltage efficiency and eliminates the need for an external Schottky
n Quiescent Current: 380µA diode. Switching frequency is set by an external resistor
n Selectable Forced Continuous/Burst Mode® Operation or can be synchronized to an external clock. OPTI-LOOP®
with Adjustable Burst Clamp compensation allows the transient response to be optimized
n Synchronizable Switching Frequency over a wide range of loads and output capacitors.
n Low Dropout Operation: 100% Duty Cycle
The LTC3418 can be configured for either Burst Mode
n Power Good Output Voltage Monitor
operation or forced continuous operation. Forced con-
n Overtemperature Protected
tinuous operation reduces noise and RF interference
n 38-Lead Low Profile (0.75mm) Thermally Enhanced
while Burst Mode operation provides high efficiency by
QFN (5mm × 7mm) Package
reducing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
Applications the output voltage ripple to be adjusted according to the
requirements of the application. A tracking input in the
n Microprocessor, DSP and Memory Supplies LTC3418 allows for proper sequencing with respect to
n Distributed 2.5V, 3.3V and 5V Power Systems another power supply.
n Automotive Applications
n Point of Load Regulation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
n Notebook Computers Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.

Typical Application
2.5V/8A Step-Down Regulator Efficiency and Power Loss vs Load Current
100 100000
VIN
CIN
2.8V TO 5.5V 90
47µF EFFICIENCY
SVIN TRACK PVIN ×4 10000
0.2µH VOUT 80
POWER LOSS (mW)

RT SW 2.5V
EFFICIENCY (%)

2.2M COUT 8A 70 1000

30.1k LTC3418
100µF
PGOOD ×2 60
RUN/SS PGND POWER LOSS
50 100
1000pF ITH SGND
4.99k SYNC/MODE VFB 40
10
820pF 332Ω 4.32k 30 VIN = 3.3V
3418 TA01a
VOUT = 2.5V
20 1
1.69k 0.01 0.1 1 10
LOAD CURRENT (A)
3418 TA01b
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LTC3418
Absolute Maximum Ratings Pin Configuration
(Note 1)
Input Supply Voltage.................................... –0.3V to 6V TOP VIEW

TRACK
ITH, RUN/SS, VFB Voltages.......................... –0.3V to VIN

PGND
PGND
PGND

PGND
PGND
PGND
SYNC/MODE Voltages................................. –0.3V to VIN 38 37 36 35 34 33 32
TRACK Voltage........................................... –0.3V to VIN SW 1 31 SW
SW Voltage................................... –0.3V to (VIN + 0.3V) SW 2 30 SW

Operating Temperature Range PVIN 3 29 PVIN

PVIN 4 28 PVIN
(Note 2)................................................–40°C to 85°C
PGOOD 5 27 SYNC/MODE
Junction Temperature (Note 5).............................. 125°C RT 6 26 ITH
Storage Temperature Range.................. –65°C to 125°C RUN/SS 7
39
25 VFB
SGND 8 24 SVIN
PVIN 9 23 PVIN
PVIN 10 22 PVIN
SW 11 21 SW
SW 12 20 SW
13 14 15 16 17 18 19

PGND
PGND
PGND
VREF
PGND
PGND
PGND
UHF PACKAGE
38-LEAD (7mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 1°C/W
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

order information http://www.linear.com/product/LTC3418#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3418EUHF#PBF LTC3418EUHF#TRPBF 3418 38-Lead (7mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

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 LTC3418
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range 2.25 5.5 V
VFB Regulated Feedback Voltage 0°C ≤ TA ≤ 85°C 0.792 0.800 0.808 V
(Note 3) l 0.784 0.800 0.816 V
IFB Feedback Input Current 100 200 nA
∆VFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 3) 0.04 0.2 %/V
VLOADREG Output Voltage Load Regulation Measured in Servo Loop, VITH = 0.36V l 0.02 0.2 %
Measured in Servo Loop, VITH = 0.84V l –0.02 –0.2 %
VTRACK Tracking Voltage Offset VTRACK = 0.4V 15 mV
Tracking Voltage Range 0 0.8 V
ITRACK TRACK Input Current 100 200 nA
∆VPGOOD Power Good Range ±7.5 ±9 %
RPGOOD Power Good Resistance 100 150 Ω
IQ Input DC Bias Current (Note 4)
Active Current VFB = 0.7V, VITH = 1V 380 450 µA
Shutdown VRUN = 0V 0.03 1.5 µA
fOSC Switching Frequency ROSC = 69.8kΩ 0.88 1 1.12 MHz
Switching Frequency Range (Note 6) 0.3 4 MHz
fSYNC SYNC Capture Range (Note 6) 0.3 4 MHz
RPFET RDS(ON) of P-Channel FET ISW = 600mA 35 50 mΩ
RNFET RDS(ON) of N-Channel FET ISW = – 600mA 25 35 mΩ
ILIMIT Peak Current Limit 12 17 A
VUVLO Undervoltage Lockout Threshold 1.75 2 2.25 V
VREF Reference Output 1.219 1.250 1.281 V
ILSW SW Leakage Current VRUN = 0V, VIN = 5.5V 0.1 1 µA
VRUN RUN Threshold 0.5 0.65 0.8 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: The LTC3418 is tested in a feedback loop that adjusts V FB to
may cause permanent damage to the device. Exposure to any Absolute achieve a specified error amplifier output voltage (ITH).
Maximum Rating condition for extended periods may affect device Note 4: Dynamic supply current is higher due to the internal gate charge
reliability and lifetime. being delivered at the switching frequency.
Note 2: The LTC3418 is guaranteed to meet performance specifications Note 5: TJ is calculated from the ambient temperature TA and power
from 0°C to 85°C. Specifications over the –40°C to 85°C operating dissipation PD as follows:
temperature range are assured by design, characterization and LTC3418: TJ = TA + (PD)(34°C/W)
correlation with statistical process controls.
Note 6: This parameter is guaranteed by design and characterization.

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 LTC3418
Typical Performance Characteristics TA = 25°C unless otherwise noted.

Internal Reference Voltage Switch On-Resistance

vs Temperature vs Input Voltage On-Resistance vs Temperature
0.8000 45 50
VIN = 3.3V VIN = 3.3V
40 45
0.7995
40
35
REFERENCE VOLTAGE (V)

0.7990 PFET PFET

ON-RESISTANCE (mΩ)
ON-RESISTANCE (mΩ)
35
30
0.7985 NFET NFET
30
25
0.7980 25
20
20
0.7975
15
15
0.7970 10 10
0.7965 5 5
0.7960 0 0
–40 –20 0 20 40 60 80 100 120 2.25 2.75 3.25 3.75 4.25 4.75 5.25 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C)
3418 G01 3418 G02 3418 G03

Quiescent Current
Switch Leakage vs Input Voltage vs Input Voltage Frequency vs ROSC
5.0 500 4500
VIN = 3.3V
4.5 450 4000
4.0 400 3500
QUIESCENT CURRENT (µA)
LEAKAGE CURRENT (nA)

3.5 350
3000
3.0 300 FREQUENCY (kHz)
2500
2.5 250
2000
2.0 200
NFET 1500
1.5 150
100 1000
1.0
PFET
0.5 50 500

0 0 0
2.25 2.75 3.25 3.75 4.25 4.75 5.25 2.5 3 3.5 4 4.5 5 5.5 10 50 90 130 170 210 250
INPUT VOLTAGE (V) INPUT VOLTAGE (V) ROSC (kΩ)
3418 G04 3418 G05 3418 G06

Efficiency and Power Loss

Frequency vs Temperature Frequency vs Input Voltage vs Load Current
1100 1100 100 100000
VIN = 3.3V
1080 1080 90
EFFICIENCY
1060 1060 10000
80
1040 1040
POWER LOSS (mW)
FREQUENCY (kHz)

FREQUENCY (kHz)

EFFICIENCY (%)

70 1000
1020 1020
1000 1000 60
POWER LOSS
980 980 50 100

960 960
40
940 940 10
30 VIN = 3.3V
920 920
VOUT = 2.5V
900 900 20 1
–40 –20 0 20 40 60 80 100 120 2.25 2.75 3.25 3.75 4.25 4.75 5.25 0.01 0.1 1 10
TEMPERATURE (°C) INPUT VOLTAGE (V) LOAD CURRENT (A)
3418 G09
3418 G07 3418 G08

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 LTC3418
Typical Performance Characteristics TA = 25°C unless otherwise noted.

Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current

100 100 100
Burst Mode OPERATION 3.3V
90 90 90
3.3V
80 80 80 5V
5V
70 70 70
FORCED CONTINUOUS
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 60 60
50 50 50
40 40 40
30 30 30
20 20 20
10 VIN = 3.3V 10 FORCED CONTINUOUS 10 Burst Mode OPERATION
VOUT = 2.5V VOUT = 2.5V VOUT = 2.5V
0 0 0
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
3418 G10 3418 G11 3418 G12

Peak Inductor Current

vs Burst Clamp Voltage Load Regulation Load Step Transient
12 0
VIN = 3.3V
VOUT = 1.8V
OUTPUT
10 –0.05 f = 1MHz
PEAK INDUCTOR CURRENT (A)

VOLTAGE
100mV/DIV
8 –0.10
ΔVOUT/VOUT (%)

6 –0.15 INDUCTOR
CURRENT
4 –0.20 5A/DIV

5V
2 –0.25 VIN = 3.3V 20µs/DIV
3418 G15
3.3V
VOUT = 2.5V
0 –0.30 LOAD STEP: 800mA TO 8A
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 1 2 3 4 5 6 7 8
VBCLAMP (V) LOAD CURRENT (A)
3418 G13 3418 G14

Load Step Transient Burst Mode Operation Start-Up Transient

OUTPUT OUTPUT
VOLTAGE VOLTAGE
100mV/DIV OUTPUT
100mV/DIV VOLTAGE
500mV/DIV

INDUCTOR
CURRENT INDUCTOR
5A/DIV CURRENT INDUCTOR
1A/DIV CURRENT
2A/DIV
3418 G18
VIN = 3.3V 40µs/DIV
3418 G16
VIN = 3.3V 20µs/DIV
3418 G17
VIN = 3.3V 1ms/DIV
VOUT = 2.5V VOUT = 2.5V VOUT = 2.5V
LOAD STEP: 3A TO 8A LOAD: 200mA LOAD: 8A

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LTC3418
Pin Functions
SW (Pins 1, 2, 11, 12, 20, 21, 30, 31): Switch Node Con- VREF (Pin 16): Reference Output. Decouple this pin with
nection to Inductor. This pin connects to the drains of the a 2.2µF capacitor.
internal main and synchronous power MOSFET switches.
SVIN (Pin 24): Signal Input Supply. Decouple this pin to
PVIN (Pins 3, 4, 9, 10, 22, 23, 28, 29): Power Input SGND with a capacitor.
Supply. Decouple these pins to PGND with capacitors on
VFB (Pin 25): Feedback Pin. Receives the feedback volt-
all four corners of the package.
age from a resistive divider connected across the output.
PGOOD (Pin 5): Power Good Output. Open-drain logic
ITH (Pin 26): Error Amplifier Compensation Point. The
output that is pulled to ground when the output voltage
current comparator threshold increases with this control
is not within ±7.5% of regulation point.
voltage. Nominal voltage range for this pin is from 0.2V
RT (Pin 6): Oscillator Resistor Input. Connecting a resis- to 1.4V with 0.4V corresponding to the zero-sense voltage
tor to ground from this pin sets the switching frequency. (zero current).
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing SYNC/MODE (Pin 27): Mode Select and External Clock
this pin below 0.5V shuts down the LTC3418. In shutdown Synchronization Input. To select Forced Continuous, tie
all functions are disabled drawing <1.5µA of supply cur- to SVIN. Connecting this pin to a voltage between 0V and
rent. A capacitor to ground from this pin sets the ramp 1V selects Burst Mode operation with the burst clamp set
time to full output current. to the pin voltage.
SGND (Pin 8): Signal Ground. All small-signal components TRACK (Pin 35): Voltage Tracking Input. Feedback volt-
and compensation components should connect to this age will regulate to the voltage on this pin during start-up
ground, which in turn connects to PGND at one point. power sequencing.
PGND (Pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37, Exposed Pad (Pin 39): The Exposed Pad is PGND and must
38): Power Ground. Connect this pin closely to the (–) be soldered to the PCB ground for electrical connection
terminal of CIN and COUT. and rated thermal performance.

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 LTC3418
Block Diagram
24 8 26 PVIN
SVIN SGND ITH
3 29
VREF
16 VOLTAGE 4 28
REFERENCE
SLOPE PMOS CURRENT 9 23
TRACK COMPENSATION COMPARATOR
35
RECOVERY 10 22
ERROR
AMPLIFIER BCLAMP
+ BURST +
COMPARATOR
–
VFB
25 – –
+ +
SYNC/MODE
SLOPE
0.74V + OSCILLATOR
COMPENSATION SW
1 2

– 11 12

– 20 21

30 31
+
LOGIC
+
NMOS
0.86V – CURRENT
COMPARATOR

RUN/SS –
7 RUN
PGND
13 32
PGOOD
+
5 CURRENT 14 33
REVERSE
COMPARATOR 15 34

17 36

18 37
RT SYNC/MODE
6 27 19 38
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LTC3418
OPERATION
Main Control Loop Burst Mode Operation
The LTC3418 is a monolithic, constant frequency, current Connecting the SYNC/MODE pin to a voltage in the range
mode step-down DC/DC converter. During normal opera- of 0V to 1V enables Burst Mode operation. In Burst Mode
tion, the internal top power switch (P-channel MOSFET) is operation, the internal power MOSFETs operate intermit-
turned on at the beginning of each clock cycle. Current in tently at light loads. This increases efficiency by minimiz-
the inductor increases until the current comparator trips ing switching losses. During Burst Mode operation, the
and turns off the top power MOSFET. The peak inductor minimum peak inductor current is externally set by the
current at which the current comparator shuts off the top voltage on the SYNC/MODE pin and the voltage on the ITH
power switch is controlled by the voltage on the ITH pin. pin is monitored by the burst comparator to determine
The error amplifier adjusts the voltage on the ITH pin by when sleep mode is enabled and disabled. When the
comparing the feedback signal from a resistor divider on average inductor current is greater than the load current,
the VFB pin with an internal 0.8V reference. When the load the voltage on the ITH pin drops. As the ITH voltage falls
current increases, it causes a reduction in the feedback below 350mV, the burst comparator trips and enables
voltage relative to the reference. The error amplifier raises sleep mode. During sleep mode, the top power MOSFET
the ITH voltage until the average inductor current matches is held off while the load current is solely supplied by the
the new load current. When the top power MOSFET shuts output capacitor. When the output voltage drops, the top
off, the synchronous power switch (N-channel MOSFET) and bottom power MOSFETs begin switching to bring the
turns on until either the bottom current limit is reached or output back into regulation. This process repeats at a rate
the beginning of the next clock cycle. The bottom current that is dependent on the load demand.
limit is set at –8A for force continuous mode and 0A for
Pulse skipping operation can be implemented by connect-
Burst Mode operation. ing the SYNC/MODE pin to ground. This forces the burst
The operating frequency is externally set by an external clamp level to be at 0V. As the load current decreases, the
resistor connected between the RT pin and ground. The peak inductor current will be determined by the voltage
practical switching frequency can range from 300kHz to on the ITH pin until the ITH voltage drops below 400mV. At
4MHz. this point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
Overvoltage and undervoltage comparators will pull the
demand is less than the average of the minimum on-time
PGOOD output low if the output voltage comes out of
inductor current, switching cycles will be skipped to keep
regulation by ±7.5%. In an overvoltage condition, the top
the output voltage in regulation.
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears Frequency Synchronization
or the bottom MOSFET’s current limit is reached.
The internal oscillator of the LTC3418 can by synchronized
Forced Continuous to an external clock connected to the SYNC/MODE pin.
The frequency of the external clock can be in the range
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation. of 300kHz to 4MHz.
At light loads, forced continuous mode operation is less For this application, the oscillator timing resistor should
efficient than Burst Mode operation, but may be desirable in be chosen to correspond to a frequency that is 25% lower
some applications where it is necessary to keep switching than the synchronization frequency. During synchroniza-
harmonics out of a signal band. The output voltage ripple tion, the burst clamp is set to 0V, and each switching cycle
is minimized in this mode. begins at the falling edge of the clock signal.

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 LTC3418
Operation
Dropout Operation Short-Circuit Protection
When the input supply voltage decreases toward the output When the output is shorted to ground, the inductor cur-
voltage, the duty cycle increases toward the maximum rent decays very slowly during a single switching cycle.
on-time. Further reduction of the supply voltage forces To prevent current runaway from occurring, a secondary
the main switch to remain on for more than one cycle current limit is imposed on the inductor current. If the
eventually reaching 100% duty cycle. The output voltage inductor valley current increases larger than 15A, the top
will then be determined by the input voltage minus the power MOSFET will be held off and switching cycles will
voltage drop across the internal P-channel MOSFET and be skipped until the inductor current is reduced.
the inductor.
Voltage Tracking
Low Supply Operation Some microprocessors and DSP chips need two power
The LTC3418 is designed to operate down to an input sup- supplies with different voltage levels. These systems often
ply voltage of 2.25V. One important consideration at low require voltage sequencing between the core power sup-
input supply voltages is that the RDS(ON) of the P‑channel ply and the I/O power supply. Without proper sequencing,
and N-channel power switches increases. The user should latch-up failure or excessive current draw may occur that
calculate the power dissipation when the LTC3418 is used could result in damage to the processor’s I/O ports or the
at 100% duty cycle with low input voltages to ensure that I/O ports of a supporting system device such as memory,
thermal limits are not exceeded. an FPGA or a data converter. To ensure that the I/O loads
are not driven until the core voltage is properly biased,
Slope Compensation and Inductor Peak Current tracking of the core supply and the I/O supply voltage is
Slope compensation provides stability in constant fre- necessary.
quency architectures by preventing subharmonic oscilla- Voltage tracking is enabled by applying a ramp voltage
tions at duty cycles greater than 50%. It is accomplished to the TRACK pin. When the voltage on the TRACK pin
internally by adding a compensating ramp to the inductor is below 0.8V, the feedback voltage will regulate to this
current signal. Normally, the maximum inductor peak tracking voltage. When the tracking voltage exceeds 0.8V,
current is reduced when slope compensation is added. control over the feedback voltage is gradually released.
In the LTC3418, however, slope compensation recovery Full release of tracking control over the feedback voltage
is implemented to keep the maximum inductor peak cur- is achieved when the tracking voltage exceeds 1.05V.
rent constant throughout the range of duty cycles. This
keeps the maximum output current relatively constant Voltage Reference Output
regardless of duty cycle.
The LTC3418 provides a 1.25V reference voltage that is
capable of sourcing up to 5mA of output current. This
reference voltage is generated from a linear regulator and
is intended for applications requiring a low noise reference
voltage. To ensure that the output is stable, the reference
voltage pin should be decoupled with a minimum of 2.2µF.

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LTC3418
APPLICATIONS INFORMATION
The basic LTC3418 application circuit is shown on the Having a lower ripple current reduces the core losses in
front page of this data sheet. External component selection the inductor, the ESR losses in the output capacitors and
is determined by the maximum load current and begins the output voltage ripple. Highest efficiency operation is
with the selection of the operating frequency and inductor achieved at low frequency with small ripple current. This,
value followed by CIN and COUT. however, requires a large inductor.

Operating Frequency A reasonable starting point for selecting the ripple current
is ∆IL = 0.4(IMAX). The largest ripple current occurs at the
Selection of the operating frequency is a trade-off between highest VIN. To guarantee that the ripple current stays
efficiency and component size. High frequency operation below a specified maximum, the inductor value should
allows the use of smaller inductor and capacitor values. be chosen according to the following equation:
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger  V  V 
L =  OUT  1– OUT 
inductance values and/or capacitance to maintain low  fΔIL(MAX)   VIN(MAX) 
output ripple voltage.
The operating frequency of the LTC3418 is determined The inductor value will also have an effect on Burst Mode
by an external resistor that is connected between the RT operation. The transition from low current operation be-
pin and ground. The value of the resistor sets the ramp gins when the peak inductor current falls below a level
current that is used to charge and discharge an internal set by the burst clamp. Lower inductor values result in
timing capacitor within the oscillator and can be calculated higher ripple current which causes this to occur at lower
by using the following equation: load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
7.3 • 1010 ⎡ ⎤ lower inductance values will cause the burst frequency
R OSC = ⎣Ω⎦ – 2.5kΩ to increase.
f
Although frequencies as high as 4MHz are possible, the Inductor Core Selection
minimum on-time of the LTC3418 imposes a minimum Once the value for L is known, the type of inductor must
limit on the operating duty cycle. The minimum on-time be selected. Actual core loss is independent of core size
is typically 80ns. Therefore, the minimum duty cycle is for a fixed inductor value, but it is very dependent on the
equal to: inductance selected. As the inductance increases, core
100 • 80ns • f(Hz) losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
Inductor Selection will increase.
For a given input and output voltage, the inductor value Ferrite designs have very low core losses and are pre-
and operating frequency determine the ripple current. The ferred at high switching frequencies, so design goals can
ripple current ∆IL increases with higher VIN or VOUT and concentrate on copper loss and preventing saturation.
decreases with higher inductance: Ferrite core material saturates “hard,” which means that
 V  V  inductance collapses abruptly when the peak design current
ΔIL =  OUT  1– OUT  is exceeded. This results in an abrupt increase in inductor
 fL   VIN  ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

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 LTC3418
APPLICATIONS INFORMATION
Different core materials and shapes will change the size/ RMS current handling requirements. Dry tantalum, special
current and price/current relationship of an inductor. Toroid polymer, aluminum electrolytic and ceramic capacitors are
or shielded pot cores in ferrite or permalloy materials are all available in surface mount packages. Special polymer
small and don’t radiate much energy, but generally cost capacitors offer very low ESR but have lower capacitance
more than powdered iron core inductors with similar density than other types. Tantalum capacitors have the
characteristics. The choice of which style inductor to use highest capacitance density but it is important to only
mainly depends on the price vs size requirements and any use types that have been surge tested for use in switching
radiated field/EMI requirements. New designs for surface power supplies. Aluminum electrolytic capacitors have
mount inductors are available from Coiltronics, Coilcraft, significantly higher ESR, but can be used in cost-sensitive
Toko and Sumida. applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
CIN and COUT Selection tors have excellent low ESR characteristics but can have
The input capacitance, CIN, is needed to filter the trapezoidal a high voltage coefficient and audible piezoelectric effects.
wave current at the source of the top MOSFET. To prevent The high Q of ceramic capacitors with trace inductance
large voltage transients from occurring, a low ESR input can also lead to significant ringing.
capacitor sized for the maximum RMS current should be
Using Ceramic Input and Output Capacitors
used. The maximum RMS current is given by:
Higher values, lower cost ceramic capacitors are now
VOUT VIN becoming available in smaller case sizes. Their high ripple
I RMS =I OUT(MAX) –1
VIN VOUT current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
This formula has a maximum at VIN = 2VOUT, where IRMS = be taken when these capacitors are used at the input and
IOUT/2. This simple worst-case condition is commonly used output. When a ceramic capacitor is used at the input and
for design because even significant deviations do not offer the power is supplied by a wall adapter through long wires,
much relief. Note that ripple current ratings from capacitor a load step at the output can induce ringing at the input,
manufacturers are often based on only 2000 hours of life VIN. At best, this ringing can couple to the output and be
which makes it advisable to further derate the capacitor, mistaken as loop instability. At worst, a sudden inrush
or choose a capacitor rated at a higher temperature than of current through the long wires can potentially cause
required. Several capacitors may also be paralleled to meet a voltage spike at VIN large enough to damage the part.
size or height requirements in the design.
When choosing the input and output ceramic capacitors,
The selection of COUT is determined by the effective series choose the X5R or X7R dielectric formulations. These
resistance (ESR) that is required to minimize voltage ripple dielectrics have the best temperature and voltage char-
and load step transients as well as the amount of bulk acteristics of all the ceramics for a given value and size.
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing Output Voltage Programming
the load transient response as described in a later section.
The output voltage is set by an external resistive divider
The output ripple, ∆VOUT, is determined by:
according to the following equation:
 1 
ΔVOUT ≤ ΔIL ESR+   R2 
 8fCOUT  VOUT = 0.8 1+ 
 R1 
The output ripple is highest at maximum input voltage The resistive divider allows pin VFB to sense a fraction of
since ∆IL increases with input voltage. Multiple capacitors the output voltage as shown in Figure 1.
placed in parallel may be needed to meet the ESR and
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LTC3418
APPLICATIONS INFORMATION
VOUT pin to ground. This sets IBURST to 0A. In this condition, the
peak inductor current is limited by the minimum on-time
R2
of the current comparator; and the lowest output voltage
VFB
ripple is achieved while still operating discontinuously.
LTC3418 R1
During very light output loads, pulse skipping allows only
SGND
a few switching cycles to be skipped while maintaining
the output voltage in regulation.
3418 F01

Figure 1. Setting the Output Voltage

Voltage Tracking
Burst Clamp Programming The LTC3418 allows the user to program how its output
If the voltage on the SYNC/MODE pin is less than VIN by voltage ramps during start-up by means of the TRACK
1V, Burst Mode operation is enabled. During Burst Mode pin. Through this pin, the output voltage can be set up to
operation, the voltage on the SYNC/MODE pin determines either track coincidentally or ratiometrically follow another
the burst clamp level, which sets the minimum peak in- output voltage as shown in Figure 2. If the voltage on the
ductor current, IBURST, for each switching cycle. A graph TRACK pin is less than 0.8V, voltage tracking is enabled.
showing the relationship between the minimum peak During voltage tracking, the output voltage regulates to
inductor current and the voltage on the SYNC/MODE pin the tracking voltage through a resistor divider network.
can be found in the Typical Performance Characteristics
section. In the graph, VBURST is the voltage on the SYNC/
MODE pin. IBURST can only be programmed in the range VOUT2
of 0A to 10A. For values of VBURST less than 0.4V, IBURST
OUTPUT VOLTAGE

is set at 0A. As the output load current drops, the peak

inductor currents decrease to keep the output voltage in
regulation. When the output load current demands a peak VOUT1

inductor current that is less than IBURST, the burst clamp will
force the peak inductor current to remain equal to IBURST
regardless of further reductions in the load current. Since
the average inductor current is greater than the output load TIME 3418 F02a

current, the voltage on the ITH pin will decrease. When

the ITH voltage drops to 350mV, sleep mode is enabled Figure 2a. Coincident Tracking
in which both power MOSFETs are shut off and switching
action is discontinued to minimize power consumption.
All circuitry is turned back on and the power MOSFETs
VOUT2
begin switching again when the output voltage drops out
of regulation. The value for IBURST is determined by the
OUTPUT VOLTAGE

desired amount of output voltage ripple. As the value of

IBURST increases, the sleep period between pulses and the VOUT1
output voltage ripple increase. The burst clamp voltage,
VBURST, can be set by a resistor divider from the VFB pin
to the SGND pin as shown in the Typical Application on
the front page of this data sheet.
TIME 3418 F02a

Pulse skipping, which is a compromise between low output

voltage ripple and efficiency during low load current opera- Figure 2b. Ratiometric Sequencing
tion, can be implemented by connecting the SYNC/MODE
3418fc

12 For more information www.linear.com/LTC3418

 LTC3418
APPLICATIONS INFORMATION
The output voltage during tracking can be calculated with top MOSFET turn-on is locked to the falling edge of the
the following equation: external frequency source. The synchronization frequency
 R2  range is 300kHz to 4MHz. Synchronization only occurs
VOUT = VTRACK 1+ ,VTRACK < 0.8V if the external frequency is greater than the frequency
 R1  set by the external resistor. Because slope compensation
is generated by the oscillator’s RC circuit, the external
To implement the coincident tracking in Figure 2a, con-
frequency should be set 25% higher than the frequency
nect an extra resistor divider to the output of VOUT2 and
set by the external resistor to ensure that adequate slope
connect its midpoint to the TRACK pin of the LTC3418
compensation is present.
as shown in Figure 3. The ratio of this divider should be
selected the same as that of VOUT1’s resistor divider. To Soft-Start
implement the ratiometric sequencing in Figure 2b, the extra
resistor divider’s ratio should be set so that the TRACK pin The RUN/SS pin provides a means to shut down the
voltage exceeds 1.05V by the end of the start-up period. LTC3418 as well as a timer for soft-start. Pulling the RUN/
The LTC3418 utilizes a method in which the TRACK pin’s SS pin below 0.5V places the LTC3418 in a low quiescent
control over the output voltage is gradually released as current shutdown state (IQ < 1.5µA).
the TRACK pin voltage approaches 0.8V. With this tech- The LTC3418 contains a soft-start clamp that can be set
nique, some overdrive will be required on the TRACK pin externally with a resistor and capacitor on the RUN/SS
to ensure that the tracking function is completely disabled pin as shown in Typical Application on the front page of
at the end of the start-up period. this data sheet. The soft-start duration can be calculated
For coincident tracking, the following condition should by using the following formula:
be satisfied to ensure that tracking is disabled at the end VIN ⎡
tSS =R SS • CSS • In ⎣Seconds ⎤⎦
of start-up. VIN – 1.8V
VOUT2 ≥ 1.32 VOUT1 When the voltage on the RUN/SS pin is raised above 2V,
For ratiometric tracking, the following equation can be the full current range becomes available on ITH.
used to calculate the resistor values:
Efficiency Considerations
V 
R4 =R3  OUT2 – 1 The efficiency of a switching regulator is equal to the output
 VTRACK  power divided by the input power times 100%. It is often
VTRACK ≥1.05V useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
VOUT2
(MASTER)
R4 R2 Efficiency = 100% – (L1 + L2 + L3 + ...)
TRACK
PIN
VFB(MASTER)
PIN
where L1, L2, etc. are the individual losses as a percent-
R3 R1 age of input power.
3418 F03 Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
Figure 3
losses: VIN quiescent current and I2R losses.
Frequency Synchronization The VIN quiescent current loss dominates the efficiency loss
The LTC3418’s internal oscillator can be synchronized at very low load currents whereas the I2R loss dominates
to an external clock signal. During synchronization, the the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
3418fc

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LTC3418
APPLICATIONS INFORMATION
currents can be misleading since the actual power lost is both power switches will be turned off and the SW node
of no consequence. will become high impedance.
1. The VIN quiescent current is due to two components: the To avoid the LTC3418 from exceeding the maximum junc-
DC bias current as given in the Electrical Characteristics tion temperature, the user will need to do some thermal
and the internal main switch and synchronous switch analysis. The goal of the thermal analysis is to determine
gate charge currents. The gate charge current results whether the power dissipated exceeds the maximum
from switching the gate capacitance of the internal power junction temperature of the part. The temperature rise is
MOSFET switches. Each time the gate is switched from given by:
high to low to high again, a packet of charge dQ moves TR = (PD)(θJA)
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In where PD is the power dissipated by the regulator and θJA
continuous mode, IGATECHG = f(QT + QB) where QT and is the thermal resistance from the junction of the die to
QB are the gate charges of the internal top and bottom the ambient temperature. For the 38-Lead 5mm × 7mm
switches. Both the DC bias and gate charge losses are QFN package, the θJA is 34°C/W.
proportional to VIN and thus their effects will be more The junction temperature, TJ, is given by:
pronounced at higher supply voltages.
TJ = TA + TR
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In where TA is the ambient temperature.
continuous mode the average output current flowing Note that at higher supply voltages, the junction tempera-
through inductor L is “chopped” between the main ture is lower due to reduced switch resistance (RDS(ON)).
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both Checking Transient Response
top and bottom MOSFET RDS(ON) and the duty cycle The regulator loop response can be checked by looking
(DC) as follows:
at the load transient response. Switching regulators take
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) several cycles to respond to a step in load current.
The RDS(ON) for both the top and bottom MOSFETs can When a load step occurs, VOUT immediately shifts by an
be obtained from the Typical Performance Character- amount equal to ∆ILOAD(ESR), where ESR is the effective
istics curves. Thus, to obtain I2R losses, simply add series resistance of COUT. ∆ILOAD also begins to charge or
RSW to RL and multiply the result by the square of the discharge COUT generating a feedback error signal used by
average output current. the regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
Other losses including CIN and COUT ESR dissipative
or ringing that would indicate a stability problem. The ITH
losses and inductor core losses generally account for
pin external components and output capacitor shown in
less than 2% of the total loss.
the Typical Application on the front page of this data sheet
Thermal Considerations will provide adequate compensation for most applications.

In most applications, the LTC3418 does not dissipate Design Example

much heat due to its high efficiency.
As a design example, consider using the LTC3418 in an
But, in applications where the LTC3418 is running at high application with the following specifications: VIN = 3.3V,
ambient temperature with low supply voltage and high VOUT = 2.5V, IOUT(MAX) = 8A, IOUT(MIN) = 200mA, f = 1MHz.
duty cycles, such as in dropout, the heat dissipated may Because efficiency is important at both high and low load
exceed the maximum junction temperature of the part. current, Burst Mode operation will be utilized.
If the junction temperature reaches approximately 150°C,
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 LTC3418
APPLICATIONS INFORMATION
First, calculate the timing resistor: capacitance needed for loop stability. For this design, five
100µF ceramic capacitors will be used.
7.3 • 1010
R OSC = – 2.5k = 70.5k CIN should be sized for a maximum current rating of:
1• 106
 2.5V  3.3V
Use a standard value of 69.8k. Next, calculate the inductor IRMS = (8A )   – 1= 3.43ARMS
value for about 40% ripple current:  3.3V  2.5V

 2.5V   2.5V  Decoupling the PVIN and SVIN pins with four 100µF capaci-
L =   1–  = 0.19µH tors is adequate for this application.
 (1MHz ) ( 3.2A )   3.3V 
The burst clamp and output voltage can now be pro-
Using a 0.2µH inductor results in a maximum ripple cur- grammed by choosing the values of R1, R2 and R3. The
rent of: voltage on the MODE pin will be set to 0.67V by the resistor
   2.5V  divider consisting of R2 and R3. A burst clamp voltage of
2.5V
ΔIL =   1–  = 3.03A 0.67V will set the minimum inductor current, IBURST, to
 (1MHz) (0.2µH)   3.3V  approximately 1.2A.
COUT will be selected based on the ESR that is required to If we set the sum of R2 and R3 to 200k, then the following
satisfy the output voltage ripple requirement and the bulk equations can be solved.

L1
0.2µH VOUT
VIN 3 1
PVIN SW 2.5V
3.3V
CIN 4 2 COUT 8A
100µF PVIN SW 100µF
×4 9 11 ×5
PVIN SW
10 12 C1
PVIN SW R1
22 20 22pF 432k
PVIN SW X7R
RSS RPG 23 21
2.2M 100k PVIN SW
RSVIN 28 30
PVIN SW
1Ω 29 31
PVIN SW
24 25
CSVIN SVIN VFB
1µF R2
LTC3418
X7R 33.2k
CSS 35 27
TRACK SYNC/MODE
1000pF
5 38
X7R PGOOD PGND
7 37
RUN/SS PGND
26 36
I PGND
ROSC 69.8k 6 TH 34 R3
RITH
CITH 7.5k RT PGND 169k
820pF 8 33
SGND PGND
X7R
13 32
C1 PGND PGND
47pF 14 19
X7R PGND PGND
15 18
PGND PGND
17 16
PGND VREF VREF
CREF
2.2µF
X7R
CIN, COUT: AVX 18126D107MAT 3418 F04
L1: TOKO FDV0620-R20M

Figure 4. 2.5V, 8A Regulator at 1MHz, Burst Mode Operation

3418fc

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LTC3418
APPLICATIONS INFORMATION
segregated with all small-signal components returning
R2+R3 = 200k to the SGND pin at one point which is then connected
R2 0.8V to the PGND pin close to the LTC3418.
1+ =
R3 0.67V 2. Connect the (+) terminals of the input capacitor(s), CIN,
The two equations shown above result in the following as close as possible to the PVIN and PGND pins at all
values for R2 and R3: R2 = 33.2k, R3 = 169k. The value four corners of the package. These capacitors provide
of R1 can now be determined by solving the equation: the AC current into the internal power MOSFETs.
R1 2.5V 3. Keep the switching node, SW, away from all sensitive
1+ = small-signal nodes.
202.2k 0.8V
R1= 430k 4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
A value of 432k will be selected for R1. Figure 4 shows components. You can connect the copper areas to any
the complete schematic for this design example. DC net (PVIN, SVIN, VOUT, PGND, SGND or any other
DC rail in your system).
PC Board Layout Checklist
5. Connect the VFB pin directly to the feedback resistors.
When laying out the printed circuit board, the following The resistor divider must be connected between VOUT
checklist should be used to ensure proper operation of and SGND.
the LTC3418. Check the following in your layout.
6. To minimize switching noise coupling to SVIN, place
1. A ground plane is recommended. If a ground plane layer an optional local filter between SVIN and PVIN. Most
is not used, the signal and power grounds should be designs do not require this filter.

Top Layer Bottom Layer

Figure 5. LTC3418 Layout Diagram

3418fc

16 For more information www.linear.com/LTC3418

 LTC3418
TYPICAL Applications
3.3V, 8A Step-Down Regulator Synchronized to 1.25MHz
L1
0.33µH VOUT
VIN 3 1
PVIN SW 3.3V
5V CIN 4 2 COUT 8A
100µF PVIN SW 100µF
×2 9 11 ×3
PVIN SW
10 12 C1
PVIN SW R1
22 20 1000pF 6.34k
PVIN SW X7R
RSS RPG 23 21
2.2M 100k PVIN SW
28 30
PVIN SW
29 31
PVIN SW
24 25
SVIN VFB
RSVIN CSVIN
1Ω 1µF LTC3418
X7R CSS 35 16
TRACK VREF VREF
1000pF CREF
5 38
X7R PGOOD PGND 2.2µF
7 37 X7R
RUN/SS PGND
26 36
I PGND
ROSC 69.8k 6 TH 34 R2
RITH
CITH RT PGND 2k
2k
2200pF 8 33
SGND PGND
X7R C1 13 32
47pF PGND PGND
X7R 14 19
PGND PGND
15 18
PGND PGND
27 17
SYNC/MODE PGND

CIN, COUT: TDK C3225X5R0J107M 3418 TA02

1.25MHz CLOCK L1: VISHAY DALE IHLP-2525CZ-01

1.2V, 8A Step-Down Regulator at 2MHz, Forced Continuous Mode

L1
0.2µH VOUT
VIN 3 1
PVIN SW 1.2V
3.3V
4 2 COUT 8A
CIN PVIN SW 100µF
100µF 9 11
PVIN SW ×3
×4
10 12 C1
PVIN SW R1
22 20 1000pF 1k
PVIN SW X7R
RSS RPG 23 21
2.2M 100k PVIN SW
28 30
PVIN SW
29 31
PVIN SW
24 25
SVIN VFB
RSVIN CSVIN
1Ω 1µF LTC3418
X7R 35 16
TRACK VREF VREF
CSS 27 38 CREF
SYNC/MODE PGND 2.2µF
1000pF
5 37 X7R
X7R PGOOD PGND
7 36
RUN/SS PGND
26 34 R2
ITH PGND 2k
ROSC 30.1k 6 33
RITH
CITH RT PGND
4.99k
2200pF 8 32
SGND PGND
X7R C1 14 19
47pF PGND PGND
X7R 15 18
PGND PGND
13 17
PGND PGND

CIN, COUT: AVX 12106D107MAT 3418 TA03

L1: COOPER FP3-R20
3418fc

For more information www.linear.com/LTC3418 17

LTC3418
TYPICAL Applications
1.8V, 8A Step-Down Regulator with Tracking

I/O SUPPLY 2.5V

R4 R3
2k 2.55k
L1
0.2µH VOUT
35 1
TRACK SW 1.8V
VIN 3 2 COUT 8A
PVIN SW 100µF
3.3V CIN 4 11 ×2
100µF PVIN SW
×4 9 12 C1
PVIN SW R1
10 20 1000pF 2.55k
PVIN SW X7R
RSS RPG 22 21
2.2M 100k PVIN SW
23 30
PVIN SW
29 31
PVIN SW
28 25
PVIN VFB
RSVIN LTC3418
1Ω 24 16
SVIN VREF VREF
CSVIN C 5 38 CREF
SS PGOOD PGND
1µF 1000pF 2.2µF
X7R 27 37 X7R
X7R SYNC/MODE PGND
7 36
RUN/SS PGND
26 34 R2
I PGND
ROSC 69.8k 6 TH 33
2k
RITH
CITH RT PGND
3.32k
2200pF 8 32
SGND PGND
X7R C1 13 19
47pF PGND PGND
X7R 14 18
PGND PGND
15 17
PGND PGND

CIN, COUT: TDK C3225X5R0J107M 3418 TA04

L1: VISHAY DALE IHLP-2525CZ-01

3418fc

18 For more information www.linear.com/LTC3418

 LTC3418
TYPICAL Applications
1.8V, 16A Step-Down Regulator
L1
0.2µH
VIN 3 1
3.3V PVIN SW
CIN1 4 2
100µF PVIN SW
×4 9 11
PVIN SW
10 12 C2
PVIN SW R1
22 20 1000pF 2.55k
PVIN SW X7R
RSS1 RPG1 23 21
2.2M 100k PVIN SW
28 30
PVIN SW
29 31
PVIN SW
24 25
SVIN VFB
RSVIN1 CSVIN1
1Ω 1µF LTC3418
X7R 35 38
TRACK PGND
5 37
PGOOD PGND VOUT
7 36 1.8V
RUN/SS PGND
26 34 COUT 16A
C1A I PGND 100µF
ROSC1 59k 6 TH 33 ×4
47pF RT PGND
X7R 8 32 R2
SGND PGND 2k
13 19
CSS1 PGND PGND
1000pF 14 18
X7R PGND PGND
15 17
PGND PGND
27 16
SYNC/MODE VREF CREF1
2.2mF
X7R
RUN

RITH
CITH
2k
2200pF
X7R

L2
0.2µH
3 1
PVIN SW
CIN2 4 2
100µF PVIN SW
×4 9 11
PVIN SW
10 12 C3
RSS2 RPG2 PVIN SW R3
2.2M 100k 22 20 1000pF 2.55k
PVIN SW X7R
23 21
PVIN SW
28 30
PVIN SW
29 31
PVIN SW
24 25
SVIN VFB
RSVIN2 CSVIN2
1Ω 1µF LTC3418
X7R CSS2 35 38
TRACK PGND
1000pF
5 37
X7R PGOOD PGND
7 36
RUN/SS PGND
26 34
I PGND
C1B ROSC2 69.8k 6 TH 33
47pF RT PGND
8 32 R4
X7R SGND PGND 2k
13 19
PGND PGND
14 18
PGND PGND
15 17
PGND PGND
27 16
SYNC/MODE VREF CREF2
2.2µF CIN1, CIN2, COUT: TDK C3225X5R0J107M
X7R L1, L2: VISHAY DALE IHLP-2525CZ-01

3418 TA06
3418fc

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LTC3418
Package Description
Please refer to http://www.linear.com/product/LTC3418#packaging for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)

0.70 ±0.05

5.50 ±0.05
5.15 ±0.05

4.10 ±0.05

3.00 REF 3.15 ±0.05

PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH
R = 0.30 TYP OR
0.75 ±0.05 3.00 REF 0.35 × 45° CHAMFER
5.00 ±0.10
0.00 – 0.05 37 38

0.40 ±0.10
PIN 1
TOP MARK 1
(SEE NOTE 6)
2

5.15 ±0.10
7.00 ±0.10 5.50 REF

3.15 ±0.10

(UH) QFN REF C 1107

0.200 REF 0.25 ±0.05 R = 0.125 R = 0.10

0.50 BSC TYP TYP
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3418fc

20 For more information www.linear.com/LTC3418

 LTC3418
Revision History (Revision history begins at Rev C)

REV DATE DESCRIPTION PAGE NUMBER

C 1/17 Modified Application Circuits 19, 22

3418fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3418
as described herein will not infringe on existing patent rights. 21
LTC3418
Typical Application
Low Noise 1.5V, 8A Step-Down Regulator
L1
0.2µH VOUT
VIN 3 1
PVIN SW 1.5V
2.5V CIN 4 2 COUT 8A
100µF PVIN SW 100µF
×4 9 11 ×3
PVIN SW
10 12 C1
PVIN SW R1
22 20 1000pF 1.78k
PVIN SW X7R
RSS RPG 23 21
2.2M 100k PVIN SW
28 30
PVIN SW
29 31
PVIN SW
24 25
SVIN VFB
RSVIN CSVIN
1Ω 1µF LTC3418
X7R CSS 35 16
TRACK VREF VREF
1000pF CREF
5 38
X7R PGOOD PGND 2.2µF
7 37 X7R
RUN/SS PGND
26 36
ITH PGND
ROSC 69.8k 6 34 R2
RITH
CITH 3.32k RT PGND 2k
2200pF 27 33
SYNC/MODE PGND
X7R
C1 8 32
SGND PGND
47pF 13 19
X7R PGND PGND
14 18
PGND PGND
15 17
PGND PGND

CIN, COUT: TDK C3225X5R0J107M 3418 TA05

L1: VISHAY DALE IHLP-2525CZ-01

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LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V,
DC/DC Converter IQ = 20µA, ISD < 1µA, ThinSOT Package
LTC3407 Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V,
DC/DC Converter IQ = 40µA, ISD < 1µA, MS Package
LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V,
DC/DC Converter IQ = 60µA, ISD < 1µA, MS Package
LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V
DC/DC Converter IQ = 60µA, ISD < 1µA, TSSOP16E Package
LTC3413 3A (IOUT Sink/source), 2MHz, Monolithic Synchronous 90% Efficiency, VIN: 2.25V to 5.5V, VOUT = VREF/2,
Regulator for DDR/QDR Memory Termination IQ = 280µA, ISD < 1µA, TSSOP16E Package
LTC3414 4A (IOUT), 4MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
DC/DC Converter IQ = 64µA, ISD < 1µA, TSSOP20E Package
LTC3416 4A (IOUT), 4MHz, Synchronous Step-Down 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V,
DC/DC Converter with Tracking IQ = 300µA, ISD < 1µA, TSSOP20E Package
3418fc

22 Linear Technology Corporation

LT 0117 REV C • PRINTED IN THE USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC3418
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3418  LINEAR TECHNOLOGY CORPORATION 2005