Features Description: LTC3894 150V Low I Step-Down DC/DC Controller With 100% Duty Cycle Capability

LTC3894
150V Low IQ Step-Down

DC/DC Controller with
100% Duty Cycle Capability
FEATURES DESCRIPTION
n Wide Operating VIN Range: 4.5V to 150V The LTC®3894 is a high voltage step-down DC/DC switch-
n Wide V
OUT Range: 0.8V to 60V ing regulator controller. It drives a P-channel power
n 9μA I when Regulating 48V to 3.3V MOSFET switch allowing 100% duty cycle operation. It
Q IN OUT
n 16μA I when Regulating 12V to 3.3V enables a low part count, simple, and robust solution for
Q IN OUT
n Very Low Dropout Operation: 100% Duty Cycle high reliability, high voltage applications.
n Adjustable Input Overvoltage Lockout
The LTC3894 operates over a wide input voltage range
n Programmable PGOOD Undervoltage Monitor
from 4.5V to 150V and can regulate output voltages
n R
SENSE or Inductor DCR Current Sensing from 0.8V to 60V. It offers excellent light load efficiency,
n Selectable High Efficiency Burst Mode® Operation or
drawing only 9μA quiescent current while regulating the
Pulse-Skipping Mode at Light Loads output voltage with no load. Its peak current mode, con-
n Programmable Fixed Frequency: 50kHz to 850kHz
n Phase-Lockable Frequency: 75kHz to 800kHz
stant frequency architecture provides for good control of
n Internal Fixed Soft-Start and External Programmable
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
Soft-Start or Voltage Tracking
n Strong MOSFET Gate Driver with Selectable
with an external resistor and can be synchronized to an
external clock from 75kHz to 800kHz.
Undervoltage Lockout Thresholds
n Optional External NMOS for Gate Driver Bias in High The LTC3894 offers programmable output voltage soft-
Power Applications start or tracking. Safety features include overvoltage,
overcurrent and overtemperature protection with a power
good output monitor with adjustable threshold.
APPLICATIONS
The LTC3894 is available in a thermally enhanced 20-Pin
n Automotive and Industrial Power Systems
n Telecommunication Power Systems
TSSOP package with leads removed to accommodate
n Distributed Power Systems
high voltage creepage and clearance requirements.
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
High Efficiency 150V to 5V Step-Down Regulator Efficiency and Power Loss vs
Load Current
22µH 20mΩ
VIN VOUT 100 10k
6V to 150V 5V, 3A Burst Mode OPERATION
90
12µF 1nF 10µF
330µF
×2 ×2 80 1k
70
POWER LOSS (mW)
SENSE+ SENSE–
EFFICIENCY (%)
RUN GATE
60 EFFICIENCY 100
VIN
PGOOD 50
0.47µF 100k
CAP 40 10
LTC3894
OVLO 422k POWER LOSS
30
DRVUV/EXTG PGUV
EXTS 20 1
VFB
ITH VIN = 12V
GND FREQ TRACK/SS PLLIN/MODE 10 VIN = 24V
3.3nF
80.6k 0 0.1
47pF 36.5k 0.1µF 0.0001 0.001 0.01 0.1 1 3
5.76k
LOAD CURRENT (A)
3894 TA01b
3894 TA01a
Rev 0
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LTC3894
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (VIN), RUN............... –0.3V to 150V
SENSE+, SENSE–, PGOOD Voltage.............. –0.3V to 65V
GATE 1 20 VIN
VIN-VCAP Voltage......................................... –0.3V to 10V RUN 3 18 CAP

VFB, PLLIN/MODE, PGUV, OVLO,
EXTS Voltages.............................................. –0.3V to 6V SENSE+ 5 21 16 DRVUV/EXTG
TRACK/SS Voltage (Note 11)..................... –0.3V to 2.8V SENSE– 6 GND 15 EXTS
ITH, FREQ Voltage........................................ –0.3V to 5V ITH 7 14 OVLO
DRVUV/EXTG Voltage................................... –0.3V to 9V PGUV 8 13 FREQ
Operating Junction Temperature Range (Notes 2, 3) VFB 9 12 PGOOD
LTC3894E, LTC3894I.......................... –40°C to 125°C TRACK/SS 10 11 PLLIN/MODE
Storage Temperature Range................... –65°C to 150°C FE PACKAGE

Lead Temperature (Soldering, 10 sec).................... 300°C 20(16)-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB FOR RATED
ELECTRICAL AND THERMAL CHARACTERISTICS
ORDER INFORMATION http://www.linear.com/product/LTC3894#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3894EFE#PBF LTC3894EFE#TRPBF LTC3894FE 20(16)-Lead Plastic TSSOP –40°C to 125°C
LTC3894IFE#PBF LTC3894IFE#TRPBF LTC3894FE 20(16)-Lead Plastic TSSOP –40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
VIN Input Voltage Operating Range (Note 4) DRVUV = 0V 4.5 150 V
VOUT Regulated Output Voltage Set Point 0.8 60 V
IQ No Load DC Supply Current (Note 5)
Shutdown VIN Pin Current RUN = 0V 7 11 µA
Sleep Mode VIN Pin Current VSENSE– = 2.5V, VFB = 0.83V 27 40 µA
VSENSE– ≥ 3.2V, VFB = 0.83V 7 10 µA
Sleep Mode SENSE– Pin Current (Note 6) VSENSE– ≥ 3.2V, VFB = 0.83V 21 30 µA
Pulse-Skipping Mode VIN Pin Current VFB = 0.83V
VSENSE– = 0V 1.8 mA
VSENSE– = 3.3V 1.5 mA
VSENSE– = 5V 0.8 mA
Rev 0
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LTC3894
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the specified operating
IQ(VINR) Total Input Supply Current in Regulation at VIN = 12V
No Load in Burst Mode (Note 7) Figure 13 Circuit, VOUT = 3.3V 16 µA
Figure 11 Circuit, VOUT = 5V 22 µA
VIN = 48V
Figure 13 Circuit, VOUT = 3.3V 9 µA
Figure 11 Circuit, VOUT = 5V 11 µA
Output Sensing
VFB Regulated Feedback Voltage VITH = 1.2V (Note 8) l 0.788 0.800 0.812 V
Feedback Voltage Line Regulation VIN = 4.5V to 150V (Note 8) ±0.002 0.015 %/V
Feedback Voltage Load Regulation VITH = 0.6V to 1.8V (Note 8) 0.03 0.15 %
gm(EA) Error Amplifier Transconductance VITH = 1.2V, ∆IITH = ±5µA (Note 8) 2 mS
IFB Feedback Input Bias Current –10 ±50 nA
Current Sensing
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V l 88 100 112 mV
(VSENSE+ – VSENSE–)
ISENSE+ SENSE+ Pin Input Current VSENSE+ = 3.3V 0.1 1 µA
ISENSE – SENSE– Pin Input Current in Non-Sleep VSENSE– = 3.3V 200 300 µA
Mode (Note 6) VSENSE– = 5V 880 1260 µA
Start-Up and Shutdown
VRUN RUN Pin Enable Threshold VRUN Rising l 1.14 1.24 1.34 V
VRUNHYS RUN Pin Hysteresis 125 mV
ISS Soft-Start Pin Charging Current VSS = 0V or 0V to 0.8V 8 11 14 µA
VOVLO Overvoltage Lockout Threshold VOVLO Rising Up l 0.77 0.8 0.82 V
Hysteresis 30 mV
Gate Driver and VIN-Cap LDO
VUVLO Undervoltage Lockout DRVUV = 0
(VIN-VCAP) Ramping Up Threshold l 3.4 3.75 4.3 V
(VIN-VCAP) Ramping Down Threshold l 3.25 3.50 3.75 V
Hysteresis 0.25 V
DRVUV = Floating
(VIN-VCAP) Ramping Up Threshold l 5.65 6.0 6.45 V
(VIN-VCAP) Ramping Down Threshold l 5.2 5.55 5.85 V
Hysteresis 0.45 V
VCAP Gate Bias LDO Output Voltage (VIN-VCAP) ICAP = 0mA, 9V ≤ VIN ≤ 150V (Note 9) l 7.5 8.0 8.5 V
VCAPDROP Gate Bias LDO Dropout Voltage (VIN-VCAP) VIN = 5V, ICAP = 15mA (Note 9) 4.1 4.4 V
∆VCAP(LOAD) Gate Bias LDO Load Regulation ICAP = 0mA to 20mA –2.8 –1.3 %
RUP Gate Pull-Up Resistance Gate High 2 Ω
RDN Gate Pull-Down Resistance Gate Low 0.9 Ω
tON(MIN) Gate Minimum On-Time (Note 10) 125 ns
Switching Frequency and Clock Synchronization
f Programmable Switching Frequency RFREQ = 25kΩ 100 kHz
RFREQ = 64.9kΩ 375 440 505 kHz
RFREQ = 105kΩ 810 kHz
Rev 0
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LTC3894
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the specified operating
fLO Low Switching Frequency FREQ = 0V 320 350 380 kHz
fHI High Switching Frequency FREQ = Open 470 530 590 kHz
fSYNC Synchronization Frequency l 75 800 kHz
VCLK(HI) Clock Input High Level into PLLIN/MODE l 2 V
VCLK(LO) Clock Input Low Level into PLLIN/MODE l 0.5 V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.35 V
IPG PGOOD Leakage Current VPGOOD = 65V 1 µA
VPGOV PGOOD Overvoltage Trip Threshold VFB Ramping Positive with Respect to Set 7 10 13 %
Regulated Voltage
Hysteresis 2.5 %
VPGUV PGOOD Undervoltage Trip Threshold VPGUV Ramping Negative 700 720 740 mV
Hysteresis 2.5 %
tPGDL PGOOD Delay PGOOD High to Low 100 µs
PGOOD Low to High 100 µs
VFBOV VFB Overvoltage Lockout Threshold VFB Ramping Positive with Respect to Set 10 %
Regulated Voltage
Hysteresis 2.5 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: The minimum input supply operating range is dependent on the
may cause permanent damage to the device. Exposure to any Absolute UVLO thresholds as determined by the DRVUV/EXTG pin setting.
Maximum Rating condition for extended periods may affect device Note 5: The DC supply current is measured when the LTC3894 is not
reliability and lifetime. switching. Dynamic supply current is higher due to the gate charge being
Note 2: The LTC3894 is tested under pulsed load conditions such that delivered at the switching frequency.
TJ ≈ TA. The LTC3894E is guaranteed to meet performance specifications Note 6: SENSE1– bias current is reflected to the input supply by the
from 0°C to 85°C. Specifications over the –40°C to 125°C operating formula
junction temperature range are assured by design, characterization and IVIN = ISENSE1– • VOUT/(VIN • η), where η is the efficiency.
correlation with statistical process controls. The LTC3894I is guaranteed Note 7: The total input supply current in Burst Mode is the total current
over the –40°C to 125°C operating junction temperature range. Note that drawn from input supply as measured in the Typical Application circuit on
the maximum ambient temperature consistent with these specifications page 1 and Figure 13 on page 30 with no load current. The specification
is determined by specific operating conditions in conjunction with board is not tested in production.
layout, the rated package thermal impedance and other environmental
Note 8: The LTC3894 is tested in a feedback loop that servos the error
factors. High temperatures degrade operating lifetimes; operating lifetime
amplifier output voltage (on ITH pin) to a specified voltage and measures
is derated for junction temperatures greater than 125ºC. The junction
the resultant VFB voltage.
temperature (TJ, in °C) is calculated from the ambient temperature (TA, in
°C) and power dissipation (PD, in Watts) according to the formula: Note 9: Positive ICAP current flows into the CAP pin and discharges the
capacitor between the VIN and CAP pins.
TJ = TA + (PD • θJA)
Note 10: The minimum on-time condition is specified for an inductor
where θJA = 38°C/W for the TSSOP package.
peak-to-peak ripple current > 40% of IMAX.
Note 3: This IC includes overtemperature protection that is intended to
Note 11: The absolute maximum rating for TRACK/SS pin is 2.8V when
protect the device during momentary overload conditions. The maximum
the pin is driven externally. When the pin is not driven, it may be pulled
rated junction temperature will be exceeded when this protection is active.
higher by the IC, typically to 4.7V.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Rev 0

LTC3894
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Pulse-Skipping Mode Operation Burst Mode Operation Transient Response:

Waveforms Waveforms Pulse-Skipping Mode Operation
VOUT VOUT
50mV/DIV 50mV/DIV IL
2A/DIV
VSW
10V/DIV ILOAD
VSW 2A/DIV
10V/DIV
IL VOUT
IL 500mA/DIV 100mV/DIV
500mA/DIV
3894 G01 3894 G02 3894 G03

2µs/DIV 20µs/DIV 100µs/DIV
VIN = 12V VIN = 12V VIN = 12V
VOUT = 5V VOUT = 5V VOUT = 5V
ILOAD = 100mA ILOAD = 100mA LOAD STEP = 100mA TO 2A
FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT
Transient Response: Dropout Behavior

Burst Mode Operation (100% Duty Cycle) Low VIN Operation
VIN
IL 2V/DIV
2A/DIV
VIN
ILOAD VOUT = VIN 2V/DIV
2A/DIV
VOUT
2V/DIV
VOUT
VOUT DROPOUT 2V/DIV
100mV/DIV GATE
10V/DIV SW
10V/DIV
3894 G04 3894 G05 3894 G06
100µs/DIV 100ms/DIV 20ms/DIV
VIN = 12V VIN TRANSIENT 12V TO 4V VIN = 0V TO 7.8V
VOUT = 5V AND BACK TO 12V AND BACK TO 0V
LOAD STEP = 100mA TO 2A VOUT = 12V, ILOAD = 100mA VOUT = 5V, ILOAD = 100mA
Soft Start-Up into a Prebiased

Normal Soft Start-Up Output Output Tracking
RUN
VIN 5V/DIV
5V/DIV
VOUT PREBIASED
TO 2.6V
VOUT
TRACKSS 1V/DIV
200mV/DIV TRACK/SS
200mV/DIV
VOUT TRACK/SS
1V/DIV 500mV/DIV VOUT
2V/DIV
3894 G07 3894 G08 3894 G09
1ms/DIV 2ms/DIV 20ms/DIV
VIN = 12V VIN = 12V VIN = 12V
ILOAD = 100mA ILOAD = 500mA ILOAD = 500mA
Rev 0

LTC3894
Burst Mode Input Current Over Pulse-Skipping Mode Input Shutdown Input Current vs
Input Voltage (No Load) Current vs Input Voltage Input Voltage
30.0 5.0 8.0
VOUT = 5V VOUT = 5V FIGURE 11 CIRCUIT
TOTAL INPUT SUPPLY CURRENT (µA)
ILOAD = 0A ILOAD = 0A
TOTAL INPUT SUPPLY CURRENT (mA)
TOTAL INPUT SUPPLY CURRENT (µA)

25.0 FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT
4.2
7.0
20.0
3.4
15.0 6.0
2.5
10.0
5.0
1.7
5.0
0 0.9 4.0
0 25 50 75 100 125 150 0 30 60 90 120 150 0 25 50 75 100 125 150
VIN (V) VIN (V) VIN (V)
3894 G10 3894 G11 3894 G12
Free Running Frequency Over Output Regulation vs Load Output Regulation vs

Temperature Current Temperature
600 0.010 1.0
VIN = 12V VIN = 12V
VOUT = 5V 0.8 VOUT = 5V
550 ILOAD NORMALIZED AT ILOAD = 1A ILOAD = 200mA
0.006 0.6
FIGURE 11 CIRCUIT VOUT NORMALIZED TO TA = 25°C
NORMALIZED ∆VOUT (%)
NORMALIZED ∆VOUT (%)

0.4 FIGURE 11 CIRCUIT
500
0.002 0.2
F (kHz)
450 0.0
–0.002 –0.2
400
–0.4
–0.006 –0.6
350
OPEN FREQ PIN Burst Mode OPERATION Burst Mode OPERATION
–0.8
GND FREQ PIN PULSE–SKIPPING PULSE-SKIPPING
300 –0.010 –1.0
–75 –50 –25 0 25 50 75 100 125 150 175 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –75 –25 25 75 125 175
TEMPERATURE (°C) ILOAD (A) TEMPERATURE (°C)
3894 G13 3894 G14 3894 G15
Overcurrent Protection Short-Circuit Protection VIN Line Transient Behavior

SHORT-CIRCUIT REGION
4A TRIGGER
ILOAD 1A 1A
2A/DIV
VOUT
5V/DIV VIN
IL SOFT
2A/DIV 20V/DIV
RECOVERY
IL GATE
VOUT 2A/DIV 20V/DIV
2V/DIV VOUT
VOUT DROOPS IN CURRENT LIMIT 20mV/DIV
3894 G16 3894 G17 3894 G18
10ms/DIV 500µs/DIV 5ms/DIV
VIN = 12V VIN = 12V VIN = 12V, SURGE TO 100V
FIGURE 11 CIRCUIT ILOAD = 500mA ILOAD = 2A
FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT
Rev 0

LTC3894
Maximum Current Sense Maximum Current Sense

Threshold vs ITH Voltage Buck Foldback Current Limit Threshold vs Duty Cycle
100 120.000 120.0
MAXIMUM CURRENT SENSE THRESHOLD (mV)

PULSE SKIPPING MODE
Burst Mode OPERATION
CURRENT SENSE THRESHOLD (mV)
80 100.000 100.0
60 80.000 80.0
40 60.000 60.0
20 40.000 40.0
0 20.000 20.0
MAXIMUM CURRENT SENSE/ITH = 90mV/V PGUV < 0.72V
–20 0 0
0 0.3 0.6 1.0 1.3 1.6 0 100 200 300 400 500 600 700 800 0 15 30 45 60 75 90
ITH (V) FEEDBACK VOLTAGE (mV) DUTY CYCLE (%)
3894 G19 3894 G20 3894 G21
IVIN and ISENSE– vs VSENSE– IVIN and ISENSE– vs VSENSE–

CLC vs VIN at 150°C (Burst Mode Operation) (Burst Mode Operation)
120 30.000 30.000
100 25.000 25.000
IVIN AND ISENSE+ (µA)

IVIN AND ISENSE+ (µA)
80 20.000 20.000
VIN RISING
60 15.000 15.000 SENSE– RISING
SENSE– FALLING
VIN FALLING
40 10.000 10.000
VOUT = 0V
VOUT = 0.5V
20 5.000 5.000
VOUT = 1.0V
VOUT = 2.0V (ZOOMED IN VSENSE–)
0 0 0
3.50 3.75 4 4.25 4.50 4.75 5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 2.5 3 3.5 4 4.5 5 5.5
VIN (V) VSENSE– (V) VSENSE– (V)
3894 G22 3894 G23 3894 G24
IVIN and ISENSE– vs VSENSE– IVIN and ISENSE– vs VSENSE–

(Pulse-Skipping Mode) (Pulse-Skipping Mode) ISENSE+ vs VSENSE+
2.000 2.000 100.000
1.750 1.750
0
1.500 1.500
IVIN AND ISENSE– (mA)
IVIN AND ISENSE– (mA)
–100.000
1.250 1.250
ISENSE+ (nA)
1.000 1.000 IVIN RISING –200.000

ISENSE– RISING
0.750 0.750 ISENSE– FALLING
IVIN FALLING –300.000
0.500 0.500
–400.000
0.250 0.250
(ZOOMED IN VSENSE–)
0 0 –500.000
0 5 10 15 20 25 30 35 40 45 50 55 60 65 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5
VSENSE– (V) VSENSE– (V) VSENSE+ (V)
3894 G25 3894 G26 3894 G27
Rev 0

LTC3894
Shutdown (RUN) Threshold vs GATE Bias LDO (VIN - VCAP) Load GATE Bias LDO (VIN - VCAP)
Temperature Regulation Dropout Regulation
1.300 0.00 7.00
VIN = 12V VIN = 7V
1.250 –0.60 6.88
(VIN –VCAP) REGULATION (%)
(VIN -VCAP) REGULATION (V)

RUN PIN VOLTAGE (V)
1.200 –1.20 6.75
1.150 –1.80 6.63
1.100 –2.40 6.50
1.050 –3.00 125°C 6.38 125°C

RUN RISING 25°C 25°C
RUN FALLING –55°C –55°C
1.000 –3.60 6.25
–75 –50 –25 0 25 50 75 100 125 150 175 0 4 8 12 16 20 0 4 8 12 16 20
TEMPERATURE (°C) IGATE (mA) IGATE (mA)
3894 G28 3894 G29 3894 G30
PIN FUNCTIONS
GATE (Pin 1): Gate Drive Output for External P-Channel and SENSE– pins across the sense resistor. For DCR sens-
MOSFET. The voltage swing on this pin is between CAP ing, Kelvin connect SENSE+ and SENSE– pins across the
and VIN. The GATE driver output is held low at VCAP to filter capacitor. When SENSE– is greater than 3.2V, the
turn on the P-channel MOSFET and held high at VIN to SENSE– pin supplies power to internal circuitry. To reduce
turn off the MOSFET. The gate driver output is held high sensing errors, minimize the impedance in series with the
when (VIN-VCAP) is less than VUVLO. SENSE– pin.
RUN (Pin 3): Run Control High Impedance Input. A RUN ITH (Pin 7): Error Amplifier Output and Switching
voltage above the 1.26V threshold enables normal opera- Regulator Compensation Point. The voltage on this pin
tion, while forcing this pin below 1.12V shuts down the sets the current sense threshold.
controller. Forcing this pin below 0.7V shuts down the
PGUV (Pin 8): Pgood Undervoltage (UV) Comparator
entire LTC3894, reducing quiescent current to approxi- High Impedance Input. Connect the PGUV pin to the out-
mately 7µA. This pin can be tied to VIN directly or pulled put through a resistor feedback divider or connect directly
up by a resistor. Do not float this pin. to VFB pin to program the output PGOOD UV threshold.
SENSE+ (Pin 5): Differential Current Sensing (+) Input. When the PGUV pin voltage falls below 0.72V (0.8V – 10%)
For RSENSE current sensing, Kelvin (4-wire) connect or lower, the PGOOD pin is asserted low after a 100µs
SENSE+ and SENSE– pins across the sense resistor. For blanking period.
DCR sensing, Kelvin connect SENSE+ and SENSE– pins VFB (Pin 9): Output Feedback Sense Input. A resistor
across the sense filter capacitor. divider from the output to this pin sets the regulated out-
SENSE– (Pin 6): Differential Current Sensing (–) Input. For put voltage. The LTC3894 will nominally regulate VFB to
RSENSE current sensing, Kelvin (4-wire) connect SENSE+ the internal reference value of 0.8V.
Rev 0

LTC3894
PIN FUNCTIONS
TRACK/SS (Pin 10): Soft-Start and External Tracking Input. ensure a graceful recovery. Connect this pin to GND when
The LTC3894 regulates the VFB voltage to the smaller of the OVLO function is not used.
0.8V or the voltage on the SS pin. An internal 10μA pull-up EXTS (Pin 15): Source Terminal Connection for the
current source is connected to this pin. A capacitor to Optional External N-Channel MOSFET. When an optional
ground at this pin sets the ramp time to the final regulated external N-channel MOSFET is used to provide bias to
output voltage. Alternatively, another voltage supply con- the gate driver, connect this pin to the MOSFET source
nected through a resistor divider to this pin allows the terminal and connect a 0.1µF bypass capacitor next to
output to track the other supply during start-up. the the pin to ensure stable operation (see Applications
PLLIN/MODE (Pin 11): External Reference Clock Input Information section on page 21). When not in use, con-
and Burst Mode Enable/Disable. When an external clock nect this pin to ground. Do not float this pin.
is applied to this pin, the internal phase-locked loop will DRVUV/EXTG (Pin 16): Driver Undervoltage Lockout
synchronize the turn-on edge of the gate drive signal with
(UVLO) Select Pin and External N-Channel Gate
the rising edge of the external clock. When no external Connection. This is a dual function pin. Grounding this
clock is applied, this input determines the mode of opera- pin selects a UVLO threshold of 3.75V between VIN and
tion during light loading. Floating this pin selects low IQ CAP. Floating or connecting it to a voltage greater than
Burst Mode operation. Pulling to ground selects pulse- 400mV selects a UVLO threshold of 6V. When an external
skipping mode operation. N-channel MOSFET is used for the gate driver bias, con-
PGOOD (Pin 12): Power Good Monitor Output. This open nect its gate terminal to the pin through a 1k resistor. This
drain logic output is pulled to ground when the VFB pin is selects the 6V UVLO threshold by default.
10% above its regulation point (OV) or when the PGUV pin CAP (Pin 18): Lower Supply Rail for Gate Driver Bias.
voltage is below the PGOOD undervoltage (UV) threshold VIN is the higher supply rail. The gate driver bias supply
VPGUV. There is a 100µs delay before PGOOD changes
voltage (VIN-VCAP) is regulated to 8V when VIN is greater
state in response to either an OV or a UV event.
than 8V. A low ESR ceramic bypass capacitor of at least
FREQ (Pin 13): Switching Frequency Setpoint Input. The 0.47μF is required from VIN to CAP pin to maintain stable
switching frequency is programmed between 75kHz and voltage regulation. The capacitor value needs to increase
850 kHz by an external setpoint resistor RFREQ connected to a minimum of 2.2µF if an external N-channel MOSFET
between the FREQ pin and SGND. An internal 20µA current is used for gate driver bias. To ensure stable low noise
source creates a voltage across the external setpoint resis- operation, the bypass capacitor should be placed adjacent
tor to set the internal oscillator frequency. Alternatively, to the VIN and CAP pins and connected using the same
this pin can be driven directly by a DC voltage to set the PCB metal layer.
oscillator frequency. Grounding selects a fixed operating VIN (Pin 20): Chip Power Supply. A minimum bypass
frequency of 350kHz. Floating selects a fixed operating
capacitor of 1µF is required from the VIN pin to GND.
frequency of 535kHz. For best performance use a low ESR ceramic capacitor
OVLO (Pin 14): Overvoltage Lockout High Impedance and place the capacitor near the VIN pin and GND pin to
Input. For an adjustable VIN overvoltage protection, con- minimize the size of the high current loop.
nect this pin through a resistor divider to VIN. When the
GND (Exposed Pad Pin 21): Chip Ground. The exposed
voltage on this pin is greater than the 0.8V lockout thresh- pad must be soldered to the circuit board for electrical
old, ,the external P-channel MOSFET is turned off imme- contact and for rated electrical and thermal performance
diately and the TRACK/SS pin is discharged to GND to of the package.
Rev 0

LTC3894
FUNCTIONAL DIAGRAM
ROVLO1 ROVLO2
VIN
CIN
OVLO
8V 0.8V VIN
UVLO
CAP
+
20µA
–
+
– CAP
–
+
REXTG
DRVUV/EXTG
+ DRUV
EXT CEXTG 1.26V –

NMOS SHDN
EXTS GATE
DRIVER
CEXTS LDO
OPTIONAL GATE
LOGIC GATE
MP
CONTROL DRIVER
RUN Q L
VIN + S R VOUT
Burst Mode IN COUT
1.26V – OPERATION CCAP
LDO
CLOCK PLLIN/MODE
+ O.425V
OUT
MODE/CLOCK
DETECT – VIN – 8V CAP D1
PLL
ICMP
SYSTEM – + SENSE+
20µA
FREQ
VCO +
SENSE–
–
RFREQ + 10µA
GND TRACK/SS
+
VOUT SLOPE + 0.8V
SHDN CSS
COMPENSATION –
RPGD
PGOOD OV + O.88V EA RFB2
(gm = 2mS) VFB
DELAY
–
100µs RFB1
UV +
– O.72V ITH PGUV
3894 FD
RPGUV2
RITH
RPGUV1
CITH1
Rev 0

LTC3894
OPERATION
Main Control Loop (Refer to Functional Diagram) MOSFET is used, a minimum capacitance of 2.2µF (low
The LTC3894 uses a constant frequency peak current- ESR ceramic) is recommended between VIN and CAP.
mode control architecture to regulate the output voltage For VIN ≤8V, the LDO will be in dropout and the CAP
in an nonsynchronous step-down DC/DC switching regu- voltage will be near ground (the VIN-CAP differential volt-
lator. The VFB input is compared to an internal reference age will nearly equal VIN). If VIN-CAP is less than VUVLO,
by a transconductance error amplifier (EA). The internal the LTC3894 enters a UVLO state where the external
reference can be either a fixed 0.8V reference VREF or P-channel MOSFET is turned off and most internal cir-
the voltage input on the TRACK/SS pin. In normal opera- cuitry is shut down. In order to exit UVLO, the VIN-CAP
tion VFB regulates to the internal 0.8V reference voltage. voltage must exceed either 3.75V or 6V depending on
In soft-start or tracking mode, when the TRACK/SS pin the DRVUV /EXTG voltage setting. When an external
voltage is less than the internal 0.8V reference voltage, N-channel MOSFET bias path is used, a UVLO threshold
VFB will regulate to the TRACK/SS pin voltage. The error of 6V is selected by default.
amplifier output connects to the ITH pin. The voltage level
on the ITH pin is then summed with a slope compensation Shutdown and Soft-Start
ramp to create the peak inductor current set point. When the RUN pin is below 0.7V, the controller and most
The peak inductor current is measured through a sense internal circuits are disabled. In this micropower shut-
resistor RSENSE placed across the SENSE+ and SENSE– down state, the LTC3894 draws only 7μA. The RUN pin
pins. The resultant differential voltage from SENSE+ to voltage must rise above 1.24V to enable the controller. The
SENSE– is proportional to the inductor current and is RUN pin can be tied to or pulled up to an external supply
compared to the peak inductor current set point. During of up to 150V or it can be driven directly by a logic gate.
normal operation the P-channel power MOSFET is turned The start-up of the output voltage VOUT is controlled by
on when the clock leading edge sets the SR latch through the voltage on the TRACK/SS pin. When the voltage on the
the S input. The P-channel MOSFET is turned off through TRACK/SS pin is less than the 0.8V internal reference, the
the SR latch R input when the differential voltage of VFB pin is regulated to the voltage on the TRACK/SS pin. This
VSENSE+ – VSENSE– is greater than the peak inductor cur- allows the TRACK/SS pin to be used to program a soft-start
rent set point and the current comparator, ICMP, trips high. by connecting an external capacitor from the TRACK/SS pin
After the MOSFET is turned off, an external Schottky diode to signal ground. An internal 10μA pull-up current charges
carries inductor current until it reaches zero or the begin- this capacitor, creating a voltage ramp on the TRACK/SS pin.
ning of the next clock cycle. As the TRACK/SS voltage rises from 0V to 0.8V, the output
voltage VOUT rises smoothly from zero to its final value.
Gate Driver Bias(VIN-CAP) and Undervoltage
Lockout (UVLO) Alternatively, the TRACK/SS pin can be used to cause the
startup of VOUT to track that of another supply. Typically,
Power for the P-channel MOSFET gate driver is derived
this requires connecting the TRACK/SS pin to an external
from the VIN and CAP pins. The CAP pin is regulated
resistor divider from the other supply to ground. (See
to 8V below VIN by an internal low dropout linear
Applications Information section.) During a shutdown,
regulator(LDO).A minimum capacitance of 0.47μF (low
input overvoltage, and input undervoltage, or overtem-
ESR ceramic) is required between VIN and CAP to assure
perature event, the TRACK/SS pin is discharged to ground
stability. The internal VIN-CAP LDO can generate signifi-
to ensure smooth restart.
cant on-chip heat when using a P-channel MOSFET with
large gate capacitance at high VIN and high switching If the slew rate of the TRACK/SS pin is greater than
frequency. An external N-channel MOSFET bias path can 0.6V/ms, the output will track an internal soft-start
be used to move the heat off chip and its connections ramp instead of the TRACK/SS pin. The internal soft-
are shown on page 10. When the external N-channel start offers a smooth start-up of the output in the case
Rev 0

LTC3894
OPERATION
of a short-circuit recovery where the output voltage will even though the ITH voltage may indicate a lower current
recover from near ground. setpoint value.
When the PLLIN/MODE pin is connected to ground for
Light Load Current Operation (Burst Mode Operation
pulse-skipping mode, the LTC3894 will skip pulses during
or Pulse-Skipping Mode)
light loads. In this mode, ICMP may remain tripped for
At light loads, the LTC3894 operates in either pulse-skip- several cycles and force the external P-channel MOSFET
ping mode or high efficiency Burst mode. To select pulse- to stay off, thereby skipping pulses. This mode offers the
skipping operation, tie the PLLIN/MODE pin to ground. To benefits of smaller output ripple, lower audible noise, and
select Burst Mode operation, float the PLLIN/MODE pin. reduced RF interference, at the expense of lower efficiency
In Burst Mode operation, if the VFB is higher than the refer- when compared to Burst Mode operation.
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V, Frequency Selection and Clock Synchronization
the internal sleep signal goes high, enabling sleep mode. The switching frequency of the LTC3894 can be selected
In sleep mode, much of the internal circuitry is turned using the FREQ pin. If the PLLIN/MODE pin is not being
off, reducing the quiescent current the LTC3894 draws to driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through
30µA. When the SENSE– pin voltage is greater than 3.2V,
an external resistor. Tying the FREQ pin to signal ground
the majority of this current (25µA) is drawn by SENSE–
selects 350kHz, while floating selects 535kHz. Placing a
and only 6µA is drawn by the VIN pin. For output voltages
greater than 3.2V, this dramatically reduces the total qui- resistor between the FREQ pin and signal ground allows
the frequency to be programmed between 50kHz and
escent current drawn from the input supply in sleep mode.
850kHz.
When referred back to the input supply, the quiescent
current is reduced by the DC/DC voltage conversion ratio The phase-locked loop (PLL) on the LTC3894 will syn-
and the incremental efficiency from VOUT to VIN. chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
Therefore, for the typical application on the first page with
Burst Mode selected, the total input supply current at no the turn-on edge of the external P-channel MOSFET to be
load in regulation can be estimated using: aligned with the rising edge of the synchronizing signal.
The oscillator’s default frequency is based on the oper-
V ⎛ 0.8V ⎞
IQ(VINR) = 6µA + OUT = ⎜ + 22µA ⎟ ating frequency set by the FREQ pin. If the oscillator’s
0.9 • VIN ⎝ RFB1 ⎠ default frequency is near the external clock frequency,

only slight adjustments are needed for the PLL to syn-
where RFB1 is the lower feedback divider resistor. chronize the external P-channel MOSFET’s turn-on edge
As the output voltage and hence the feedback voltage to the rising edge of the external clock. This allows the
decreases, the error amplifier’s output will rise. When PLL to lock rapidly without deviating far from the desired
the output voltage drops enough, the ITH pin is recon- frequency. The PLL is guaranteed from 75kHz to 750kHz.
nected to the output of the error amplifier, and the con- The clock input levels should be greater than 2V for logic
troller resumes normal operation by turning on the exter- high and less than 0.5V for logic low.
nal P-channel MOSFET on the next cycle of the internal
oscillator. Power Good
In Burst Mode operation, the peak inductor current has The PGOOD pin connects to the open-drain output of an
to reach at least 25% of current limit for the current com- internal N-channel MOSFET. The MOSFET pulls the PGOOD
parator, ICMP, to trip and turn the P-MOSFET back off, pin low when either the VFB pin voltage is overvoltage at
10% or more above or the PGUV pin is undervoltage at
Rev 0

LTC3894
OPERATION
10% or more below the 0.8V internal voltage reference. foldback reduces the power dissipation in the Schottky
The PGOOD pin is also pulled low during an overtempera- diode and assures robust operation during a continu-
ture, RUN pin shutdown, VIN overvoltage or VIN under- ous short-circuit fault. Current limit foldback is disabled
voltage lockout event. When the VFB pin voltage is less during soft-start (as long as the VFB voltage is keeping
than 0.88V (0.8V + 10%) and PGUV is above 0.72V (0.8V up with the TRACK/SS voltage). Note that the LTC3894
– 10%), the internal N-channel MOSFET is turned off and continuously monitors the inductor current and prevents
the PGOOD pin is allowed to be pulled up by an external current runaway under all conditions.
resistor to VOUT or another source no greater than 60V.
LTC3894 has an internal overtemperature protection cir-
The PGOOD open-drain output has a 100μs delay before cuit that shuts off the controller and the external P-channel
it can transition states. MOSFET when internal die temperature exceeds 180°C.
When the VFB voltage is higher than 0.88V (0.8V + 10%) The circuit also discharges the TRACK/SS pin to GND to
nominal, this is considered an overvoltage condition and ensure a smooth restart.
the external P-MOSFET is immediately turned off and
remains turned off until VFB falls below 0.88V with built- Input Supply Overvoltage Lockout (OVLO Pin)
in hysteresis of 20mV. The LTC3894 implements a protection feature that inhibits
switching when the input voltage rises above a program-
Current Limit Foldback mable operating range. By using a resistor divider from
In the event of an output short-circuit or overcurrent con- the input supply to ground, the OVLO pin serves as a
dition that causes the output voltage to fall to less than precise input supply voltage monitor. Switching is dis-
72% of its nominal regulated level and the PGUV pin volt- abled when the OVLO pin rises above 0.8V, which can be
age is less than 0.72V, current limit foldback is activated, configured to limit switching to a specific range of input
progressively lowering the peak current limit in propor- supply voltage. An input supply overvoltage event triggers
tion to the drop of VOUT until reaching a minimum cur- a TRACK/SS reset, which results in a graceful recovery
rent limit of about 36% of full current limit. Current limit from an input supply transient.
APPLICATIONS INFORMATION
The LTC3894 is a current mode, constant frequency The typical application on the front page is a basic
nonsynchronous step-down DC/DC controller with a LTC3894 application circuit where the inductor current
P-channel power MOSFET acting as the main switch is sensed using a low value sense resistor, RSENSE, placed
and a Schottky power diode acting as the commutat- between the power inductor and VOUT. Once the required
ing (catch) diode. The input range extends from 4.5V to output voltage and operating frequency have been deter-
150V. The output range can be programmed from 0.8V mined, external component selection is driven by load
to 60V. The LTC3894 can transition from regulation to requirements, and begins with the selection of inductor
100% duty cycle when the input voltage drops below the and RSENSE. Next, the power MOSFET and catch diode are
programmed output voltage. Additionally, the LTC3894 selected. Finally, input and output capacitors are selected.
offers Burst Mode operation with a very low quiescent
current, delivering outstanding efficiency in light load Output Voltage Programming
operation not typically found in a controller. The LTC3894 The output voltage is programmed by connecting a feed-
is a low pin-count, robust and easy to use solution in back resistor divider from the output to the VFB pin as
applications which require high efficiency and operate shown in Figure 1. The output voltage in steady state
with widely varying high voltage inputs.
Rev 0

LTC3894
operation is set by the feedback resistors according to 1000.0
the equation: 900.0

800.0
REFERENCE CURRENT (kHz)

⎛ R ⎞
VOUT = 0.8V • ⎜ 1+ FB2 ⎟ 700.0
⎝ R FB1 ⎠ 600.0

500.0
To improve the transient response, a feedforward capaci- 400.0
tor CFF may be used. Great care should be taken to route 300.0
the VFB line away from noise sources, such as the inductor 200.0
or the GATE signal that drives the external P-MOSFET. 100.0

0
VOUT 15 30 45 60 75 90 105 120 135 150
REFERENCE VOLTAGE (kΩ)
3894 F02
LTC3894 RFB2 CFF
VFB Figure 2. Switching Frequency vs Resistor on FREQ Pin
RFB1
3894 F01 The free-running switching frequency can be programmed

Figure 1. Setting the Output Voltage from 50kHz to 850kHz by connecting a resistor from FREQ
pin to signal ground. The resulting switching frequency as
a function of resistance on FREQ pin is shown in Figure 2.
Switching Frequency and Clock Synchronization Set the free-running frequency to the desired synchroni-
The choice of operating frequency is a trade-off between zation frequency using the FREQ pin so that the internal
efficiency and component size. Lowering the operat- oscillator is prebiased to approximately the synchroni-
ing frequency improves efficiency by reducing MOSFET zation frequency. While it is not required that the free-
switching losses but requires larger inductance and/ running frequency be near the external clock frequency,
or capacitance to maintain low output ripple voltage. doing so will minimize synchronization time.
Conversely, raising the operating frequency degrades
efficiency but reduces component size. Inductor Selection
The LTC3894 can free run at a user programmed switch- The operating frequency and inductor selection are inter-
ing frequency, or it can synchronize to an external clock. related in that higher operating frequencies allow the
When a clock signal is applied to the PLLIN/MODE pin, use of smaller inductor and capacitor values. A higher
the turn-on of the external P-channel MOSFET is coin- frequency generally results in lower efficiency because
cidental with the rising edge of the applied clock. The of MOSFET gate charge and transition losses. In addi-
switching frequency of the LTC3894 is programmed with tion to this basic trade-off, the effect of inductor value
the FREQ pin, and the external clock is applied at the on ripple current and low current operation must also be
PLLIN/MODE pin. Table 1 highlights the different states considered.
in which the FREQ pin can be used in conjunction with The inductor value has a direct effect on ripple current. The
the PLLIN/MODE pin. inductor ripple current, ∆IL, decreases with higher induc-
Table 1 tance or higher frequency and increases with higher VIN.
FREQ PIN PLLIN/MODE PIN FREQUENCY Given the desired input and output voltages, the induc-
0V DC Voltage 350kHz tor value and operation frequency determine the ripple
Floating DC Voltage 535kHz current:
Resistor to GND DC Voltage 50kHz to 850kHz
⎛ V ⎞⎛ V ⎞
Any of the Above External Clock Phase Locked to External Clock ΔIL = ⎜ OUT ⎟ ⎜ 1– OUT ⎟
⎝ f •L ⎠ ⎝ VIN ⎠

Rev 0

LTC3894
Lower ripple current reduces core losses in the induc- VIN
tor, ESR losses in the output capacitors and results in VIN
lower output ripple. The highest efficiency operation can GATE

RSENSE
be obtained at low frequency with small ripple current. CAP VOUT
However, achieving this requires a large inductor. There LTC3894
is a trade-off between component size, efficiency, and
SENSE+
operating frequency. C1*
A reasonable starting point for ripple current is 40% of SENSE–

GND
IOUT(MAX). The largest ripple current occurs at the highest 3894 F03a
VIN. To guarantee that the ripple current does not exceed (3a) Using a Resistor to Sense Current
a specified maximum, the inductance should be chosen
according to: VIN
⎛ VOUT ⎞ ⎛ V ⎞ VIN
L=⎜ ⎟ ⎜ 1– OUT ⎟ INDUCTOR
⎝ f • ΔIL(MAX) ⎠ ⎝ VIN(MAX) ⎠ GATE
L DCR
CAP VOUT
The inductor value also has secondary effects. The tran- LTC3894
sition to Burst Mode operation begins when the average R1
inductor current required results in a peak current below SENSE+
25% of the current limit determined by RSENSE. Lower C1* R2

SENSE–
inductor values (higher ∆IL) will cause this to occur at GND
lower load currents, which can cause a dip in efficiency in (R1||R2) • C1 = L/DCR 3894 F03b
the upper range of low current operation. In Burst Mode *PLACE C1 NEAR SENSE PINS RSENSE(EQ) = DCR(R2/(R1+R2))
operation, lower inductance values will cause the burst (3b) Using the Inductor DCR to Sense Current
frequency to decrease. Figure 3. Current Sensing Methods
Inductor Core Selection Inductor Current Sensing

Once the inductance value has been determined, the type LTC3894 can be configured to use either low value series
of inductor must be selected. Core loss is independent of resistor sensing (Figure 3a) or DCR (inductor resistance)
core size for a given inductor value, but it is very depen- sensing (Figure 3b). The choice between the two current
dent on the inductance selected. As inductance increases, sensing schemes is largely a design trade-off between
core losses decrease. Unfortunately, increased inductance cost, power consumption and accuracy. DCR sensing is
requires more turns of wire and therefore copper losses becoming popular because it saves expensive current
will increase. sensing resistors and is more power efficient, especially
Ferrite designs have very low core loss and are preferred in high current applications. However, current sensing
for high switching frequencies, so design goals can con- resistors provide the most accurate current limits for the
centrate on copper loss and preventing saturation. Ferrite controller.
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is SENSE+ and SENSE– Pins
exceeded. This results in an abrupt increase in inductor The SENSE+ and SENSE– pins are the inputs to the dif-
ripple current and consequent output voltage ripple. Do ferential current comparator. The common mode voltage
not allow the core to saturate! range on these pins is 0V to 65V (absolute maximum),
enabling the LTC3894 to regulate an output voltage up
Rev 0

LTC3894
to a nominal 60V (allowing margin for tolerances and peak-to-peak ripple current, ∆IL. To calculate the sense
transients). The SENSE+ pin is high impedance. This high resistor value, use the equation:
impedance allows the current comparators to be used in VSENSE(MAX)
inductor DCR sensing. RSENSE =
ΔI
The impedance of the SENSE– pin changes depending on IOUT(MAX) + L
2
the common mode voltage. When SENSE– is less than
2.9V, it is high impedance, drawing less than 1µA. When Choose a sense resistor with low parasitic inductance to
SENSE– is above 3.2V, pin current increases considerably improve sensing accuracy.
and can be as high as 1.2mA. To ensure that the application will deliver full load cur-
Any voltage drop caused by the current along the SENSE– rent over the full operating temperature range, choose the
PCB board trace directly translates into errors in current minimum value (88mV) for the VSENSE(MAX) threshold in
sensing. The impedance of the SENSE– board layout trace the Electrical Characteristics table and take into account
need to be minimized to maintain high sensing accuracy. inductance tolerance as listed in inductor manufacturer’s
data sheet (typically ±20%).
Optional filter component C1, mutual to the sense lines,
should be placed close to the LTC3894, and the sense When using the controller in high duty cycle conditions,
lines should run close together to a 4-wire Kelvin con- the maximum output current level will be reduced due to
nection underneath the current sense element (shown in the internal compensation required to meet the stability
Figure 4). Sensing current elsewhere can effectively add criterion for buck regulators operating at greater than 50%
parasitic inductance and capacitance to the current sense duty factor. A curve is provided in the Typical Performance
element, degrading the information at the sense terminals Characteristics section to estimate this reduction in peak
and making the programmed current limit unpredictable. inductor current depending upon the operating duty fac-
If DCR sensing is used (Figure 3b), R1 should be placed tor. (See Maximum Current Sense Threshold vs Duty
close to the switching node, to prevent noise from cou- Cycle curve on page 7).
pling into sensitive small-signal nodes.
TO SENSE FILTER Inductor DCR Sensing
NEXT TO THE CONTROLLER
For applications requiring the highest possible efficiency
at high load currents, the LTC3894 is capable of sensing
SWITCHING NODE COUT the voltage drop across the inductor DCR, as shown in
CURRENT FLOW
Figure 3b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
3894 F04
INDUCTOR OR RSENSE
Figure 4. Sense Lines Placement with Inductor or Sense Resistor can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
Low Value Resistor Current Sensing an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
A typical sensing circuit using a discrete resistor is shown DCR sensing.
in Figure 3a. RSENSE is chosen based on the required out-
put current. The voltage across the resistor, VSENSE, is If the external (R1||R2) • C1 time constant is chosen to
proportional to inductor current. The LTC3894 current be exactly equal to the L/DCR time constant, the voltage
comparator has a fixed maximum current sense threshold drop across the external capacitor is equal to the drop
VSENSE(MAX) of 100mV (typical). across the inductor DCR multiplied by R2/(R1 + R2). R2
scales the voltage across the sense terminals for appli-
The current comparator threshold voltage sets the peak of cations where the DCR is greater than the target sense
the inductor current, yielding a maximum average output resistor value. To properly dimension the external filter
current, IOUT(MAX), equal to the peak value less half the
Rev 0

LTC3894
components, the DCR of the inductor must be known. It The maximum power loss in R1 is related to duty cycle,
can be measured using a good RLC meter, but the DCR and will occur in continuous mode at the maximum input
tolerance is not always the same and varies with tempera- voltage:
ture; consult the manufacturers’ data sheets for detailed
information.
PLOSS R1=
( VIN(MAX) − VOUT ) • VOUT
Using the inductor ripple current value from the Inductor R1
Value Calculation section, the target sense resistor value Ensure that R1 has a power rating higher than this value.
is: If high efficiency is necessary at light loads, consider this
VSENSE(MAX) power loss when deciding whether to use DCR sensing
RSENSE(EQUIV) = or sense resistors. Light load power loss can be mod-
ΔI
IOUT(MAX) + L estly higher with a DCR network than with a sense resis-
2
tor, due to the extra switching losses incurred through
To ensure that the application will deliver full load cur- R1. However, DCR sensing eliminates a sense resistor,
rent over the full operating temperature range, choose the reduces conduction losses and provides higher efficiency
minimum value (88mV) for the VSENSE(MAX) threshold in at heavy loads. Peak efficiency is about the same with
the Electrical Characteristics table. either method.
Next, determine the DCR of the inductor. When provided, Power MOSFET Selection
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature The LTC3894 drives a P-channel power MOSFET that
coefficient of copper resistance, which is approximately serves as the main switch for the asynchronous step-
0.4%/°C. A conservative value for TL(MAX) is 100°C. down converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown volt-
To scale the maximum inductor DCR to the desired sense age VBR(DSS), threshold voltage VGS(TH), on-resistance
resistor value, use the divider ratio RD: RDS(ON), gate charge QG, and the MOSFET’s thermal resis-
R SENSE(EQUIV ) tance θJC(MOSFET) and θJA(MOSFET).
RD =
DCR M AX at TL(M AX) A partial list of P-channel MOSFET devices suitable

for a 150V high current LTC3894 application includes
C1 is usually selected to be in the range of 0.1μF to FDMC86263P (Fairchild), SIR873DP (Vishay), IRF6218S
0.47μF. This forces R1|| R2 to around 2k, reducing error (Infineon), FDMC86259P (Fairchild), and Si7439DP
that might have been caused by the SENSE+ pin’s ±1μA (Vishay).
current.
The gate driver bias voltage VIN-VCAP is set by an internal
The equivalent resistance R1||R2 is scaled to the room LDO regulator. In normal operation, the CAP pin will be
temperature inductance and maximum DCR: regulated to 8V below VIN. A minimum 0.47µF capacitor
L is required between the VIN and CAP pins to ensure LDO
R1!R2 = stability. If required, additional capacitance can be added
(DCR at 20°C)•C1 to accommodate higher gate currents. The capacitance

should be increased to a minimum of 2.2µF when the
The sense resistor values are:
external N-channel MOSFET is used. In shutdown and
R1!R2 R1•RD R1!R2 Burst Mode operation, the CAP LDO is turned off. In the
R1= ; R2 = =
RD 1−RD 1−RD event of CAP leakage to ground, the CAP voltage is lim-
ited to 9V by a weak internal clamp from VIN to CAP. As
a result, a minimum 10V VGS rated MOSFET is required.
Rev 0

LTC3894
The power dissipated by the P-channel MOSFET when the specified for a given VSD test voltage, but can be adjusted
LTC3894 is in continuous conduction mode is given by: for different VSD voltages by multiplying by the ratio of
the adjusted VSD to the curve specified VSD value. A way
PMOSFET ≅ D •IOUT 2 • ρτ •RDS(ON) + to estimate the CMILLER term is to take the change in gate
charge from points a and b (or the parameter QGD on a
⎛I ⎞
VIN2 • ⎜ OUT ⎟ • (CMILLER ) • manufacturer’s data sheet) and dividing it by the specified
⎝ 2 ⎠ VSD test voltage, VSD(TEST).
⎡ RDN RUP ⎤ Q GD
⎢ + ⎥•f CMILLER ≅
⎣ ( VIN – VCAP ) – VMILLER VMILLER ⎦
VSD(TEST)

where D is duty factor, RDS(ON) is on-resistance of The term with CMILLER accounts for transition loss,
P-MOSFET, ρt is temperature coefficient of on-resistance, which is highest at high input voltages. For VIN < 20V,
RDN is the pull-down driver resistance specified at 0.9Ω the high-current efficiency generally improves with larger
typical and RUP is the pull-up driver resistance specified at MOSFETs, while for VIN > 20V, the transition losses rap-
2Ω typical. VMILLER is the Miller effective VGS voltage and idly increase to the point that the use of a higher RDS(ON)
is taken graphically from the power MOSFET data sheet. device with lower CMILLER actually provides higher effi-
ciency. When an application is intended for use at low
The power MOSFET input capacitance CMILLER is VIN, care must be taken to select a P-channel MOSFET
the most important selection criteria for determin- with threshold voltage VGS(TH) low enough to operate at
ing the transition loss term in the P-channel MOSFET low VIN.
but is not directly specified on MOSFET data sheets.
CMILLER is a combination of several components, but Schottky Diode Selection
it can be derived from the typical gate charge curve
included on most data sheets (Figure 5). The curve is When the P-MOSFET is turned off, a power Schottky diode
generated by forcing a constant current out of the gate of a is required to function as a commutating diode to carry the
common-source connected P-MOSFET that is loaded with inductor current. The average diode current is therefore
a resistor, and then plotting the gate voltage versus time. dependent on the P-MOSFET’s duty factor. The worst case
The initial slope is the effect of the gate-to-source and condition for diode conduction is a short-circuit condition
gate-to-drain capacitances. The flat portion of the curve where the Schottky must handle the maximum current
is the result of the Miller multiplication effect of the drain- as its duty factor approaches 100% (and the P-channel
to-gate capacitance as the drain voltage rises across the MOSFET’s duty factor approaches 0%). The diode there-
resistor load. The Miller charge (the increase in coulombs fore must be chosen carefully to meet worst case voltage
on the horizontal axis from a to b while the curve is flat) is and current requirements. The equation below describes
the continuous or average forward diode current rating
required, where D is the regulator duty factor.
G S
IF(AVG) ≅ I OUT(MAX) • (1–D)
MILLER EFFECT
VSG D +
V
– SD(TEST)

a b
IGATE RLOAD
Once the average forward diode current is calculated,
QIN
CMILLER = (QB – QA)/VSD(TEST)
the power dissipation can be determined. Refer to the
Schottky diode data sheet for the power dissipation
3894 F05
(a) (b)
PDIODE as a function of average forward current IF(AVG).
Figure 5. (a) Typical P-MOSFET Gate Charge Characteristics PDIODE can also be iteratively determined by the two equa-
and (b) Test Set-Up to Generate Gate Charge Curve tions below, where VF(IOUT,TJ) is a function of both IF(AVG)
Rev 0

LTC3894
and junction temperature TJ. Note that the thermal resis- Since ∆IL increases with input voltage, the output ripple
tance θJA(DIODE) given in the data sheet is typical and is highest at maximum input voltage. Typically, once the
can be highly layout dependent. It is therefore impor- ESR requirement is satisfied, the capacitance is adequate
tant to make sure that the Schottky diode has adequate for filtering and has the necessary RMS current rating.
heat sinking.
Multiple capacitors placed in parallel may be needed to
T J ≅ P DIODE • θ J A(DIODE) + T A meet the ESR and RMS current handling requirements.
P DIODE ≅ I F( AVG) • V F(IOUT,TJ ) Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
The Schottky diode forward voltage is a function of both packages. Specialty polymer capacitors offer very low
IOUT and TJ, so several iterations may be required to ESR but have lower specific capacitance than other types.
satisfy both equations. The Schottky forward voltage VF Tantalum capacitors have the highest specific capacitance,
should be taken from the Schottky diode data sheet curve but it is important to only use types that have been surge
showing Instantaneous Forward Voltage. The forward tested for use in switching power supplies. Aluminum
voltage will decrease as a function of TJ and increase as electrolytic capacitors have significantly higher ESR, but
a function of IF. The nominal forward voltage will also tend can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
to increase as the reverse breakdown voltage increases.
term reliability. Ceramic capacitors have excellent low ESR
It is therefore advantageous to select a Schottky diode
characteristics but can have a high voltage coefficient and
appropriate to the input voltage requirements.
audible piezoelectric effects.
CIN and COUT Selection The high Q of ceramic capacitors with trace inductance
The input capacitance CIN is required to filter the square can also lead to significant ringing. When used as input
wave current through the P-channel MOSFET. Use a low capacitors, care must be taken to ensure that ringing from
ESR capacitor sized to handle the maximum RMS current. inrush currents and switching does not pose an overvolt-
age hazard to the power switch and controller. To dampen
V VIN input voltage transients, add a small 5μF to 40μF alumi-
ICIN(RMS) ≅ IOUT(MAX) • OUT • –1 num electrolytic capacitor with an ESR in the range of
VIN VOUT
0.5Ω to 2Ω. High performance through-hole capacitors
The formula has a maximum at VIN = 2VOUT, where may also be used, but an additional ceramic capacitor
ICIN(RMS) = IOUT(MAX)/2. This simple worst-case condition in parallel is recommended to reduce the effect of lead
is commonly used for design because even significant inductance.
deviations do not offer much relief. Note that ripple cur-
rent ratings from capacitor manufacturers are often based Discontinuous and Continuous Operation
on only 2000 hours of life, which makes it advisable to The LTC3894 operates in discontinuous conduction
derate the capacitor. (DCM) until the load current is high enough for the induc-
The selection of COUT is primarily determined by the ESR tor current to be positive at the end of the switching cycle.
required to minimize voltage ripple and load step tran- The output load current at the continuous/discontinuous
sients. The ∆VOUT is approximately bounded by: boundary IOUT(CDB) is given by the following equation:
(VIN – VOUT)( VOUT+ VF )
⎛ 1 ⎞ I OUT(CDB) ≅
ΔVOUT ≤ ΔIL ⎜ ESR+ 2 • L • f •(VIN + VF )
⎝ 8 • f •COUT ⎟⎠

Rev 0

LTC3894
The continuous/discontinuous boundary is inversely VIN
proportional to the inductor value. Therefore, if required, R3

IOUT(CDB) can be reduced by increasing the inductor value. RUN
R4 LTC3894
RUN Pin and VIN Overvoltage/Undervoltage Lockout OVLO
The LTC3894 is enabled using the RUN pin. It has a rising R5 3894 F06
threshold of 1.24V with 100mV of hysteresis. Pulling the

RUN pin below 1.12V shuts down the main control loop. Figure 6. Adjustable UV and OV Lockout
Pulling it below 0.8V disables the controller and most
internal circuits. In this state the LTC3894 draws only 7μA For applications that do not require an OVLO, the OVLO
of quiescent current. pin can be tied directly to ground. The RUN pin in this type
of application can be used as an external UVLO using the
The RUN pin is high impedance and must be externally previous equations with R5 = 0Ω.
pulled up/down or driven directly by logic. The RUN pin
can tolerate up to 150V (absolute maximum), so it can be Similarly, for applications that do not require an adjustable
conveniently tied to VIN in always-on applications where UVLO, the RUN pin can be tied to VIN. In this configura-
the controller is enabled continuously and never shut tion, the UVLO threshold is limited to the internal VIN-CAP
down. UVLO thresholds (VUVLO) as shown in the Electrical
Characteristics table. The resistor values for the OVLO can
The RUN and OVLO pins can alternatively be configured as be computed using the previous equations with R3 = 0Ω.
adjustable undervoltage (UVLO) and overvoltage (OVLO)
lockouts on the VIN supply with a resistor divider from VIN PGOOD Programming in Dropout Applications
to ground. A simple resistor divider can be used as shown (PGUV Pin)
in Figure 6 to meet specific VIN voltage requirements.
The PGUV or Power Good Undervoltage pin is included
The current that flows through the R3-R4-R5 divider will to give greater flexibility in defining a normal range of
directly add to the shutdown, sleep, and active current operating VOUT for the LTC3894. In a conventional DC/DC
of the LTC3894, and care should be taken to minimize controller, the OV and UV comparators monitor the VFB pin
the impact of this current on the overall efficiency of the and define a fixed ± power good window about a regula-
application circuit. Resistor values in the megaohm range tion point for VOUT. In the LTC3894, the OV comparator
may be required to keep the impact on quiescent shut- monitors the VFB pin and the UV comparator monitors the
down and sleep currents low. To pick resistor values, the PGUV pin. For a typical application that does not operate
sum total of R3 + R4 + R5 (RTOTAL) should be chosen in dropout, the PGUV pin can be tied to the VFB pin to
first based on the allowable DC current that can be drawn establish a conventional ±10% PGOOD window around
from VIN. the regulation point, outside of which VOUT enters UV
The individual values of R3, R4 and R5 can be calculated and OV condition respectively. Because the LTC3894 is a
from the following equations: 100% duty cycle controller, it can be used in applications
where dropout or operating VOUT below regulation is part
0.8V of normal operation. For those applications, the PGUV
R 5 = R TOTAL •
R ISING VIN OVLO THR ESHOLD pin can be used to establish a lower limit for PGOOD
1.24V independent of the VFB pin.
R 4 = R TOTAL • –R5
R ISING VIN UVLO THR ESHOLD A good example of defining power good in both regu-
R 3 = R TOTAL – R 5 – R 4
lation and dropout is a 12V battery output preregulator
with a wide ranging VIN and VOUT regulation point set at
12V. If the defined operating output range is 12V to 9V
Rev 0

LTC3894
a conventional power good cannot be used because 9V internal LDO with an external N-channel MOSFET. This
is under the VFB UV threshold (12V – 10% or 10.8V). option will move the power dissipation off chip and lower
In this example, the PGOOD window is defined between the internal chip temperature. To effectively keep the chip
10% above 12V and 10% below 9V. The Output Voltage and board temperature low, sufficient heat sink is required
OV (VOUTOV) is 13.2V and Output Voltage UV (VOUTUV) for the N-channel MOSFET. The connections for the
is 8.1V. N-channel MOSFET are shown in the Functional Diagram
VOUT on page 10. Connecting the N-channel MOSFET auto-
matically select the UVLO threshold of 6V. External buf-
LTC3894 RUV2
fer resistor REXTG (1k) and ceramic bypass capacitors
PGUV CEXTS and CEXTG (0.1µF each, 20V rated) are required and
RUV1 need to be placed as close as practical to the N-channel
3894 F07 MOSFET source terminal and EXTG pin respectively to
Figure 7. Programmable Power Good UV ensure stable operation.
External N-Channel MOSFET Selection

To set PGUV to trigger at 9V minus 10% or 8.1V use a
resistor divider as seen in Figure 7. The resistors RUV1 When selecting an external NMOS device for the external
and RUV2 set the divided output to the PGUV pin. VOUTUV gate driver charge path, threshold VGS(TH) ,maximum VDS
is defined as the voltage where the divided output on the rating, and maximum power rating need to be considered
PGUV pin is 0.72V (0.8V – 10%). The resistor divider may for the maximum VIN used in an application . A NMOS with
be calculated as follows: VGS(TH) less than 5V should be used. During operation,
the maximum continuous voltage drop across the external
RUV(1,2) is chosen based on IQ current requirements. N-channel MOSFET VDS can be calculated as:
R UV(1,2) = R UV1 + R UV2 = Assume 500k
VDS(EXT.NMOS) = VIN – 8V
0.72V The average current flowing through the NMOS can be
R UV1 = R UV(1,2) •
VOUTUV calculated as:
0.72V IAVG_NMOS = QG(ext. PFET) • f
R UV1 = 500k • = 44k
8.1
where QG(ext. PFET) is the total Gate charge needed to turn
R UV2 = R UV(1,2) – R UV1 = 500k – 44k = 456k, Use 453k
on the external PFET in a switching cycle, f is the switch-
ing frequency.
External N-Channel MOSFET Bias Path for the Gate
Total power dissipation in the N-channel MOSFET is:
Driver (DRVUV/EXTG Pin and EXTS Pin)
PNMOS = VDS(EXT.NMOS) • IAVG_NMOS = (VIN – 8V) •
The LTC3894 has an internal LDO to regulate the gate
QG(ext. PFET) • f
driver bias voltage (VIN-CAP) to a nominal 8V and provide
the gate drive current. The amount of the gate current As it can be seen, the maximum power dissipation occurs
depends on the external P-channel MOSFET gate capaci- at maximum VIN of 150V.
tance and switching frequency. Charging and discharging For example , in an application where VIN = 150V,
the gate of the external P-channel MOSFET will result in an QG(ext. PFET) = 30nC, f = 350kHz, PNMOS = 142V • 30nC •
effective gate drive current and power loss inside the chip. 350kHz = 142V • 10.5mA = 1.49W
For applications where a large gate drive current and Sufficient heat sink is needed to remove the heat
high VIN generate excessively high internal power dis- generated.
sipation, the LTC3894 offers an option to bypass the
Rev 0

LTC3894
EXTERNAL EXTERNAL
SUPPLY SUPPLY
VOLTAGE
VOLTAGE
VOUT VOUT
TIME TIME 3894 F08a
Coincident Tracking Ratiometric Tracking
Figure 8(a). Two Different Modes of Output Tracking
EXT. V VOUT EXT. V VOUT

RFB2 RFB2 R1 RFB2
R2 0.8V
TRACK/SS TO VFB TRACK/SS ≥ TO VFB
R1+ R2 EXT. V
RFB1 RFB1 R2 RFB1
3894 F08b
Coincident Tracking Setup Ratiometric Tracking Setup
Figure 8(b): Setup for Ratiometric and Coincident Tracking
External Soft-Start and Output Tracking TRACK/SS pin to scale the ramp rate appropriately. Two
common implementations of tracking as shown in Figure 8a
Start-up characteristics are controlled by the voltage on
are coincident and ratiometric. For coincident tracking,
the TRACK/SS pin. When the voltage on the TRACK/SS
make the divider ratio from the external supply the same
pin is less than the internal 0.8V reference, the LTC3894
regulates the VFB pin voltage to the voltage on the TRACK/ as the divider ratio for the feedback voltage. Ratiometric
SS pin. When the TRACK/SS pin is greater than the inter- tracking could be achieved by using a different ratio than
nal 0.8V reference, the VFB pin voltage regulates to the the feedback (Figure 8b).
0.8V internal reference. The TRACK/SS pin can be used to Note that the constant TRACK/SS pin current produces a
program an external soft-start function or to allow VOUT small offset error to the resistive divider tracking. Account
to track another supply during start-up. for the error or minimize it by selecting small tracking
resistor values.
Soft-start is enabled by connecting a capacitor from the
TRACK/SS pin to ground. An internal 10µA current source
Short-Circuit Faults: Current Limit and Foldback
charges the capacitor, providing a linear ramping voltage
at the TRACK/SS pin that causes VOUT to rise smoothly In the LTC3894, the maximum inductor current is inher-
from 0V to its final regulated value. The total soft-start ently limited by the current mode controller by the maxi-
time will be approximately: mum current sense threshold voltage VSENSE(MAX).
0.8V LTC3894 also includes current foldback to help limit load
tSS = C SS • current when the output is shorted to ground. When the
10µA
output feedback VFB voltage is less than 72% of the 0.8V
When the LTC3894 is configured to track another supply, a internal reference (560mV), and PGUV is less than 0.72V,
voltage divider can be used from the tracking supply to the current limiting foldback is activated. The current limit will
Rev 0

LTC3894
continue to drop as VFB drops until reaching a minimum
VIN
foldback current of about 36% of the the full operational
current limit.
VOUT
VOLTAGE
Under short-circuit conditions with very low duty cycles,
cycle skipping will begin in order to limit the short-circuit INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
current, thus preventing current limit runaway. In this
situation, the power Schottky diode will be dissipating ~ 650µs TIME
most of the power that is considerably reduced by the (a)
current limit foldback. The short-circuit ripple current is
determined by the minimum on-time, tON(MIN), the input VOUT
VOLTAGE
voltage and inductor value:
SHORT-CIRCUIT INTERNAL SOFT-START
⎛V ⎞
ΔI L(SC)= tON(MIN) ⎜ IN ⎟ INDUCED RECOVERY
⎝ L ⎠

TIME
The resulting average short-circuit current is: (b)
VIN
1 VIN
ISC = 45% •ILIM(MAX) – ΔIL(SC)
2
VOUT VIN
DROPOUT VOUT
VOLTAGE
Short-Circuit Recovery and Internal Soft-Start

INTERNAL SOFT-START
An internal soft-start feature guarantees a maximum posi- INDUCED RECOVERY
tive output voltage slew rate in all operational cases. In a

TIME
short-circuit recovery condition for example, the output
(c)
recovery rate is limited by the internal soft-start so that 3894 F09
output voltage overshoot and excessive inductor current Figure 9. Internal Soft-Start (a) Allows Soft Start-Up without
buildup is prevented. an External Soft-Start Capacitor and Allows Soft Recovery from
(b) a Short-Circuit or (c) a VIN Dropout
The internal soft-start voltage and the external TRACK/SS
pin operate independently. The output will track the lower Fault Conditions: Overtemperature Protection
of the two voltages. The slew rate of the internal soft-start At higher temperatures, or in cases where the internal
voltage is roughly 0.6V/ms, which translates to a total power dissipation causes excessive self heating on chip,
soft-start time of 1.3ms. If the slew rate of the TRACK/SS the overtemperature shutdown circuitry will shut down
pin is greater than 0.6V/ms the output will track the inter- the LTC3894. When the junction temperature exceeds
nal soft-start ramp. To assure robust fault recovery, the approximately 180°C, the overtemperature circuitry shuts
internal soft-start feature is active in all operational cases. down most of the LTC3894 chip including the external
If a short-circuit condition occurs which causes the output P-channel MOSFET and discharges TRACK/SS to ground.
to drop significantly, the internal soft-start will assure a Once the junction temperature drops back to the approxi-
soft recovery when the fault condition is removed. mately 165°C, the chip turns back on and restarts with a
The internal soft-start assures a clean soft ramp-up from soft-start ramp. Long term overstress (TJ > 125°C) should
any fault condition that causes the output to droop, guar- be avoided as it can degrade the performance or shorten
anteeing a maximum ramp rate in soft-start, short-circuit the life of the part.
fault release, or output recovery from drop out. Figure 9
illustrates how internal soft-start controls the output
ramp-up rate under varying scenarios.
Rev 0

LTC3894
UVLO Selection (DRVUV/EXTG Pin) An automotive battery droops during a cold crank con-
dition. The typical automotive battery voltage is 12V to
The DRVUV/EXTG pin can be used to select one of the
14.4V, which has more than enough headroom for the
two Undervoltage Lockout thresholds (UVLO) for the Gate
LTC3894 to start up. Onboard electronics which are pow-
drive bias voltage(VIN-CAP). When the pin is grounded,
ered by a DC/DC regulator require a minimum supply volt-
the gate drive UVLO threshold is set to 3.75V. When
age for seamless operation during the cold crank condi-
DRVUV/EXTG is floated, the UVLO is set to 6V.
tion, and the battery may droop close to these minimum
Table 2 summarizes the values of UVLO threshold selected supply requirements during a cold crank. The DC/DC
for different EXTG and EXTS pin configurations. Note that regulator should not exacerbate the situation by having
when the external N-channel MOSFET is used, the 6V excessive voltage drop between the already suppressed
UVLO is selected by default. battery voltage input and the output of the regulator
Table 2
which powers these electronics. As seen in Figure 10, the
TYPICAL UVLO EXT
LTC3894’s 100% duty cycle capability allows low dropout
RISING THRESHOLD NMOS DRVUV/EXTG EXTS from the battery to the output. The drop from VIN to VOUT
3.75V No GND GND is determined by the output Load current multiplied by the
6V No FLOAT GND total series resistance in dropout mode. The guaranteed
6V Yes* Connected to Connected to UVLO falling thresholds of 3.5V and 5.75V assure suf-
External N-Channel External N-Channel ficient margin for continuous, uninterrupted operation in
MOSFET GATE MOSFET SOURCE
extreme cold crank battery drooping conditions. However,
*(Connect the external N-channel MOSFET drain to the CAP pin.)
additional input capacitance or slower soft-start time may
be required at low VIN in order to limit VIN droop caused
VIN Undervoltage Lockout (UVLO) by inrush currents, especially if the input source has a
With the user selectable UVLO threshold, The LTC3894 is sufficiently large output impedance.
designed to accommodate applications requiring widely
VBATTERY
varying input voltages from 4.5V to 150V. 12V
There is a built-in hysteresis between UVLO rising and

VOLTAGE
UVLO falling thresholds and its implication must be care-

fully considered in low VIN operation. When DRVUV/EXTG 5V
VOUT
pin is grounded, the nominal UVLO threshold with VIN ris- LTC3894’s 100% DUTY CYCLE CAPABILITY ALLOWS
VOUT TO RIDE VIN WITHOUT SIGNIFICANT DROP-OUT
ing is 3.75V and the nominal UVLO falling is 3.5V. For the
low UVLO threshold selection, the operating input voltage TIME 3894 F10
range of the LTC3894 is guaranteed to be 3.75V to 150V Figure 10. Typical Automotive Cold Crank
over temperature, but the initial VIN ramp must exceed
4V to guarantee a start-up. When the DRVUV/EXTG pin is Minimum On-Time Considerations
greater than 300mV, the nominal UVLO threshold rising
The minimum on-time, tON(MIN), is the smallest time dura-
is 6V and nominal UVLO falling is 5.55V. For this high
tion that the LTC3894 is capable of turning on an external
UVLO threshold selection, the operating input voltage
P-channel MOSFET, and is typically 100ns. It is determined
range of the LTC3894 is guaranteed to be 5.55V to 150V
by internal timing delays and the gate charge required to
over temperature, but the initial VIN ramp must exceed 6V
turn on the MOSFET. Low-duty-cycle applications may
to guarantee a start-up.
Rev 0

LTC3894
approach this minimum on-time limit, so care should be 2. Transition Loss: Transition loss of the P-channel
taken to ensure that: MOSFET becomes significant only when operating
V OUT
at high input voltages (typically 20V or greater.) The
t ON(MIN) < P-channel transition losses (PPMOSTRL) can be deter-
V IN(MAX ) • f mined from the following equation:

If the duty cycle falls below what can be accommodated ⎛I ⎞
PPMOSTRL = VIN2 • ⎜ OUT ⎟ • (CMILLER ) •
by the minimum on-time, the controller will skip cycles. ⎝ 2 ⎠
However, the output voltage will continue to regulate, but
the voltage and current ripple will increase. ⎡ RDN RUP ⎤
⎢ + ⎥•f
( V −
⎣ IN CAPV ) – VMILLER V MILLER ⎦
Efficiency Considerations
3. Gate Charging Loss: Charging and discharging the gate
The percent efficiency of a switching regulator is equal to of the MOSFET will result in an effective gate charg-
the output power divided by the input power times 100%. ing current. Each time the P-channel MOSFET gate is
It is often useful to analyze individual losses to determine switched from low to high and low again, a packet of
the dominant contributors and therefore where efficiency charge dQ moves from the capacitor across VIN-VCAP
improvements can be made. Percent efficiency can be and is then replenished from VIN by the internal VCAP
expressed as: regulator. The resulting dQ/dt current is a current out
% Efficiency = 100% - (L1+L2+L3+…) of VIN flowing to ground. The total power loss in the
controller including gate charging loss is determined
where L1, L2, L3, etc., are the individual losses as a per- by the following equation:
centage of input power.
PCNTRL = VIN • (IQ + f •QG(PMOSFET))
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses 4. Schottky Loss: The Schottky diode loss is most signifi-
in LTC3894 application circuits. cant at low duty factors (high step down ratios). The
1. I2R Loss: I2R losses result from the P-channel MOSFET critical component is the Schottky forward voltage as
resistance, inductor resistance, the current sense resis- a function of junction temperature and current. The
tor, and input and output capacitor ESR. In continu- Schottky power loss is given by the following equation.
ous mode operation the average output current flows PDIODE ≅ (1–D)•IOUT • VF(IOUT,TJ)
through L but is chopped between the P-channel
MOSFET and the bottom side Schottky diode. The fol- When making adjustments to improve efficiency, the input
lowing equation may be used to determine the total I2R current is the best indicator of changes in efficiency. If
loss: changes cause the input current to decrease, then the
⎛ I2 ⎡RDCR +RSENSE +D • ⎤ efficiency has increased. If there is no change in input
+ ΔI2L ⎞
PL 2R ≈ ⎜ OUT •⎢ ⎥+ current, there is no change in efficiency.
⎝ 12 ⎟
⎠ (
⎢⎣ RDS(ON) +RESR(CIN) ) ⎥⎦
OPTI-LOOP® Compensation
ΔI2L
•RESR(COUT) OPTI-LOOP compensation, through the availability of
12
the ITH pin, allows the transient response to be opti-
mized for a wide range of loads and output capacitors.
The ITH pin not only allows optimization of the control
Rev 0

LTC3894
loop behavior but also provides a test point for the step- at the ITH pin signal which is in the feedback loop and
down regulator ’s DC-coupled and AC-filtered closed-loop is the filtered and compensated feedback loop response.
response. The DC step, rise time and settling at this test
The gain of the loop increases with RITH and the band-
point truly reflects the closed-loop response. Assuming a
width of the loop increases with decreasing CITH1. If RITH
predominantly second order system, phase margin and/
is increased by the same factor that CITH1 is decreased,
or damping factor can be estimated using the percentage the zero frequency will be kept the same, thereby keeping
of overshoot seen at this pin. The bandwidth can also be the phase the same in the most critical frequency range
estimated by examining the rise time at this pin. of the feedback loop. In addition, a feedforward capaci-
The ITH series RITH-CITH1 filter sets the dominant pole- tor, CFF , can be added to improve the high frequency
zero loop compensation. Additionally, a small capacitor response, as shown in Figure 1. Capacitor CFF provides
placed from the ITH pin to signal ground, CITH2, may be phase lead by creating a high frequency zero with RFB2
required to attenuate high frequency noise. The values can which improves the phase margin. The output voltage set-
be modified to optimize transient response once the final tling behavior is related to the stability of the closed-loop
PCB layout is done and the particular output capacitor system and will demonstrate overall performance of the
type and value have been determined. The output capaci- step-down regulator.
tors need to be selected because their various types and In some applications, a more severe transient can be
values determine the loop feedback factor gain and phase. caused by switching in loads with large (>10μF) input
An output current pulse of 20% to 100% of full load cur- capacitors. If the switch connecting the load has low
rent having a rise time of 1μs to 10μs will produce output resistance and is driven quickly, then the discharged
voltage and ITH pin waveforms that will give a sense of input capacitors are effectively put in parallel with COUT ,
the overall loop stability without breaking the feedback causing a rapid drop in VOUT . No regulator can deliver
loop. The general goal of OPTI-LOOP compensation is to enough current to prevent this problem. The solution is
realize a fast but stable ITH response with minimal output
to limit the turn-on speed of the load switch driver. A hot
droop due to the load step. For a detailed explanation of
swap controller is designed specifically for this purpose
OPTI-LOOP compensation, refer to Application Note 76. and usually incorporates current limiting, short-circuit
Switching regulators take several cycles to respond to a protection and soft starting.
step in load current. When a load step occurs, VOUT imme-
diately shifts by an amount equal to ∆ILOAD • ESR, where PC Board Layout Checklist
ESR is the effective series resistance of COUT . ∆ILOAD also When laying out the printed circuit board, the following
begins to charge or discharge COUT , generating a feed- checklist should be used to ensure proper operation of
back error signal used by the regulator to return VOUT to the LTC3894.
its steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate 1. Multilayer boards with dedicated ground layers are
a stability problem. preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for VIN, VOUT
Connecting a resistive load in series with a power MOSFET, and GND for good filtering and minimal copper loss. If
then placing the two directly across the output capacitor a ground layer is used, then it should be immediately
and driving the gate with an appropriate signal generator below (and/or above) the routing layer for the power
is a practical way to produce a realistic load-step condi- train components which consist of CIN, sense resistor,
tion. The initial output voltage step resulting from the step P-MOSFET, Schottky diode, inductor, and COUT. Flood
change in output current may not be within the bandwidth unused areas of all layers with copper for better heat
of the feedback loop, so this signal cannot be used to sinking.
determine phase margin. This is why it is better to look
Rev 0

LTC3894
2. Keep signal and power grounds separate except at the 5. The SENSE– and SENSE+ leads should be routed
point where they are shorted together. Short signal and together as a differential pair with minimum PC trace
power ground together only at a single point with a nar- spacing. The optional filter capacitor between SENSE+
row PCB trace (or single via in a multilayer board). All and SENSE– should be as close as possible to the IC.
power train components should be referenced to power Ensure accurate current sensing with Kelvin connec-
ground and all small signal components (e.g., CITH1, tions at the SENSE resistor. DCR sensing resistor R1
RFB1, RFB2, RFREQ, CSS etc.) should be referenced to should be placed close to the switch node. Current
signal ground. through the SENSE– trace can be 1mA or higher and IR
drop along the trace can adversely affect current sens-
3. Place CIN, CCAP, the Schottky diode, the P-channel
ing accuracy. Care must be taken to reduce SENSE–
MOSFET, inductor, and primary COUT capacitors close
board trace impedance.
together in one compact area. The junction connecting
the drain of P-MOSFET, cathode of Schottky, and (+) 6. Place the resistive feedback divider RFB1/2 as close as
terminal of inductor (this junction is commonly referred possible to the VFB pin and connect it between the (+)
to as the switch or phase node) should be compact but terminal of COUT or the output regulation point and
large enough to handle the inductor currents without signal ground. The divider shall not share a common
large copper losses. Place the source of P-channel path with SENSE– connection and should be away from
MOSFET as close as possible to the (+) plate of CIN any noisy power train path and components.
capacitor(s) that provides the bulk of the AC current 7. Place the ceramic CCAP capacitor as close as possible
(these are normally the ceramic capacitors), and connect to VIN and CAP pins. This capacitor provides the gate
the anode of the Schottky diode as close as possible to charging current for the power P-channel MOSFET.
the (–) terminal of the same CIN capacitor(s). The high
dI/dt loop formed by CIN, the MOSFET, and the Schottky 8. Place small signal components as close to their respec-
diode should have short leads and PCB trace lengths to tive pins as possible. This minimizes the possibility of
minimize high frequency EMI and voltage stress from PCB noise coupling into these pins. Give priority to
inductive ringing. The (–) terminal of the primary COUT VFB, ITH, and FREQ pins. Use sufficient isolation when
capacitor(s) which filters the bulk of the inductor ripple routing a clock signal into PLLIN /MODE pin so that the
current (these are normally the ceramic capacitors) clock does not couple into sensitive small signal pins.
should also be connected close to the (–) terminal of 9. Minimize the length of board connection between the
CIN. Gate pin and gate terminal of the external P-channel
4. Keep high dV/dt signals on the GATE and the switch MOSFET and the connection between the CAP pin and
nodes away from sensitive small signal traces and the drain terminal of the external N-channel MOSFET
components. All of these nodes have very large and when it is used.
fast moving signals and therefore should be kept on
the output side of the LTC3894 and occupy minimum
PC trace area.
Rev 0

LTC3894
TYPICAL APPLICATIONS
L1 RSENSE
MP1 22µH 20mΩ VOUT
VIN
5V
6V TO 150V
CIN2 + CIN1 COUT2 + COUT1 3A
D1 CSNS 330µF 10µF
0.22µF 12µF
200V 160V 1nF 6.3V 50V
×2 ×2 ×2
RPG
RUN GATE SENSE+ SENSE–
100k
VIN PGOOD
CVIN1
CCAP
0.1µF RFB2
0.47µF
200V CAP 422k
LTC3894 PGUV
OVLO CVIN1: 0.1µF 200V MURATA GRM31CR72D104KW03L
VFB
DRVUV/EXTG CCAP: 0.47µF 16V MURATA GCM188R71C474KA55L
EXTS CIN1:12µF 160V ILLINOIS CAPACTOR 126AVG160MGBJ
CIN2: 0.22µF 200V MURATA GRM32DR72D224KW01
ITH
CITH1 RFB1 RSENSE : 20mΩ SUSUMU KRL3216E-M-R020-F-T1
GND FREQ TRACK/SS PLLIN/MODE
3.3nF 80.6k L1: 22µH WURTH ELEKTRONIK 7447709220
RITH1 CITH2 RFREQ CSS1 MP1: FAIRCHILD FDMS86263P
5.76k 47pF 36.5k 0.1µF D1: DIODES PDS4150
COUT2: 330µF 6.3V AVS TPSD337M006R0050
COUT1: 10µF 50V MURATA GRM31CR61H106MA12L
3894 TA02a
Efficiency vs Load Current Power Loss vs Load Current

100 10k
Burst Mode OPERATION Burst Mode OPERATION
90
80 1k
70
POWER LOSS (mW)
EFFICIENCY (%)
60 100
50
40 10
VIN = 12V VIN = 12V
30 VIN = 24V VIN = 24V
20 VIN = 48V 1 VIN = 48V
VIN = 100V VIN = 100V
10 VIN = 150V VIN = 150V
0 0.1
0.0001 0.001 0.01 0.1 1 3 0.0001 0.001 0.01 0.1 1 3
LOAD CURRENT (A) LOAD CURRENT (A)
3894 TA02b 3894 TA02c
Figure 11. High Efficiency 150V to 5V/3A, 200kHz Step-Down Regulator
Rev 0

LTC3894
L1 RSENSE
MP1 68µH 33mΩ VOUT
VIN
60V**
30V TO 120V*
CIN2 + CIN1 COUT2 + COUT1 2A
D1 RSP 100µF 4.7µF
1µF 12µF
10Ω 63V 100V
250V 160V
×3 ×2 CSNS ×3
1nF
ROV3
953k
RUN GATE SENSE+ SENSE– RPG
100k
VIN PGOOD
CVIN1 ROV2 CCAP RFB3
0.1µF 33.2k 0.47µF 1M
CAP
LTC3894 PGUV
OVLO
ROV1 RFB2
DRVUV/EXTG 3.74k
6.65k
EXTS VFB
ITH RFB1
CITH1 GND FREQ TRACK/SS PLLIN/MODE 13.7k
330pF
RITH1 CITH2 RFREQ CSS1
450kHz
48.7k 10pF 64.9k 0.1µF CIN1: 12µF 160V ILLINOIS CAP 126AVG160MGBJ
EXTERNAL CLOCK
CIN2: 1µF 250V TDK CGA8P3X7T2E105KS
COUT1: 4.7µF 100V TDK CGA6M3X7S2A475K
* SURGES TO 150V, OVLO STOPS SWITCHING WHEN VIN > 120V. 3894 TA03a
COUT2: 100µF 63V UNITED CHEMI-CON EMVH630ARA101MKE0S
REGULATOR SHUTS DOWN WHEN VIN < 30V. L1: 60µH WURTH ELEKTRONIK 7447709680
** VOUT FOLLOWS VIN WHEN VIN < 60V. MP1: FAIRCHILD FDMC86259P
PGOOD UNDERVOLTAGE = 42V D1: ST MICRO STPS10150CG
Efficiency and Power Loss vs Load Current

100 10
PULSE–SKIPPING MODE
90 VIN = 75V
80 VOUT = 60V
70
POWER LOSS (mW)
EFFICIENCY (%)
60
50 1
40
30 POWER LOSS
20
EFFICIENCY
10
0 0.1
0.0001 0.001 0.01 0.1 1 3
LOAD CURRENT (A)
3894 TA03b
Figure 12. High Efficiency 120V Input to 60V Step-Down Regulator with Surge Protection to 150V
Rev 0

LTC3894
L1
VIN MP1 15µH VOUT Efficiency and Power Loss vs Load Current
6V 3.3V 100 10
TO 150V CIN2 + CIN1 RDCR1 RDCR2 COUT2 + COUT1 3A Burst Mode OPERATION
1µF 12µF D1 16.9k 220µF 10µF 90 VIN = 28V
63.4k
250V 160V 6.3V 50V VOUT = 3.3V
80 1
×3 ×3 ×2
CDCR
47nF 70
POWER LOSS (mW)

EFFICIENCY (%)
60 0.1
50 EFFICIENCY
RPG
RUN GATE SENSE+ SENSE–
100k 40 POWER LOSS 0.01
VIN PGOOD
CCAP RFB3 30
0.47µF 1M
CAP 20 0.001
CVIN1 LTC3894 PGUV
0.1µF VFB 10
200V
OVLO 0 0.0001
DRVUV/EXTG 0.0001 0.001 0.01 0.1 1 3
EXTS RFB1 LOAD CURRENT (A)
ITH GND FREQ TRACK/SS PLLIN/MODE 3894 TA04b
CITH1 316k
4.7nF
CITH2 RFREQ CSS1
RITH1 47pF 32.4k 0.1µF CIN1: 12µF 160V ILLINOIS CAP 126AVG160MGBJ
7.5k CIN2: 1µF 250V TDK CGA8P3X7T2E105KS
COUT1: 10µF 50V MURATA GRM31CR61H106MA12L
3894 TA04a
COUT2: 220µF 6.3V KEMET T520B227M006ATE045
L1: 15µH WURTH ELEKTRONIK 744771115
MP1: FAIRCHILD FDMS86263P
D1: ST MICRO STPS10150CG
Figure 13. 6V to 150V Input, 3.3V/3A Output, 175kHz Step-Down Regulator
L1 RSENSE Efficiency and Power Loss vs Load Current

VIN MP1 39µH 33mΩ VOUT 100 100k
6V 12V** Burst Mode OPERATION
TO 100V CIN2 + CIN1 COUT1 + COUT2 2A 90 VIN = 48V
D1 CSNS 330µF 22µF
4.7µF 100µF 80 VOUT = 12V 10k
100V 100V 1nF 16V 16V
×2 70
POWER LOSS (mW)

EFFICIENCY (%)
60 1k
100k 50 EFFICIENCY
VIN PGOOD
CCAP 40 100
0.47µF
CAP RFB3 30
CVIN1 LTC3894 1M POWER LOSS
0.1µF PGUV 20 10
CFB2
OVLO
10pF 10
DRVUV/EXTG VFB
EXTS 0 1
RFB1 0.0001 0.001 0.01 0.1 1 2
ITH GND FREQ TRACK/SS PLLIN/MODE
CITH1 71.5k LOAD CURRENT (A)
150pF 3894 TA05b
CSS1
RITH1 CITH2 0.1µF CIN1: 100µF 100V PANASONIC EEE-FK2A101AM
280k 47pF CIN2: 4.7µF 100V TDK CGA6M3X7S2A475K
COUT1: 330µF 16V AVX TCJE337M016R0050
** VOUT FOLLOWS VIN WHEN VIN < 12V 3894 TA05a
COUT2: 22µF 16V TDK C3225X5R1C226MT
L1: 39µH WURTH ELEKTRONIK 7447709390
D1: VISHAY V12P10
Figure 14. 6V to 100V Input, 12V/2A Output, 350kHz Step-Down Regulator
Rev 0

LTC3894
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3894#packaging for the most recent package drawings.
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1924 Rev Ø)
Exposed Pad Variation CB
6.40 – 6.60*
3.86 (.252 – .260)
(.152) 3.86
(.152)
20 18 16 15 14 13 12 11
6.60 ±0.10
2.74
4.50 ±0.10 (.108)
6.40
SEE NOTE 4 2.74 (.252)
(.108) BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 3 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°
0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30 FE20(16) (CB) TSSOP REV 0 0512
(.0077 – .0118)
NOTE: TYP
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 31
LTC3894
TYPICAL APPLICATION
High Efficiency 6V to 80V Input, 5V/3A Output, Step-Down Regulator
L1 RSENSE
VIN MP1 15µH 22mΩ VOUT Efficiency and Power Loss vs Load Current
5V
6V TO 80V
CIN2 + COUT2 COUT1 + COUT2 3A
100 10k
D1 CSNS Burst Mode OPERATION
4.7µF 22µF 10µF 220µF 90
100V 820pF 50V 6.3V
×2 80 1k
70
POWER LOSS (mW)

EFFICIENCY (%)
60 100
100k EFFICIENCY
VIN PGOOD 50
CVIN1 CCAP
0.1µF 0.47µF RFB3 40 10
CAP 1M
LTC3894 30
OVLO PGUV
DRVUV/EXTG 20 1
EXTS VFB POWER LOSS
10 VIN = 12V
ITH VIN = 24V
CITH1 RFB1
GND FREQ TRACK/SS PLLIN/MODE 0 0.1
3.3nF 187k 0.0001 0.001 0.01 0.1 1 5
RITH1 CITH2 RFREQ CSS1 LOAD CURRENT (mA)
7.5k 82pF 60.4k 0.1µF 3894 TA06b
COUT2: 220µF 6.3V KEMET T520B227M006ATE045 3894 TA06a
L1: 15µH COILCRAFT SER1390-153MLB

D1: DIODES INC SBR3U100LP7
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V ≤ VIN ≤ 105V, 1V ≤ VOUT ≤ VIN, IQ = 2μA Fixed Frequency 200kHz
to 2MHz, 5mm × 6mm QFN
LTC7810 150V, Low IQ, Dual, 2-Phase Synchronous Step-Down 4.5V ≤ VIN ≤ 150V, 1V ≤ VOUT ≤ 60V, Low 16µA IQ, Adjustable Gate
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Rev 0
32
D16856-0-4/18(0)
www.analog.com
For more information www.analog.com  ANALOG DEVICES, INC. 2018

Features Description: LTC3894 150V Low I Step-Down DC/DC Controller With 100% Duty Cycle Capability

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LTC3894

150V Low IQ Step-Down

Document Feedback For more information www.analog.com 1

VIN-VCAP Voltage......................................... –0.3V to 10V RUN 3 18 CAP

LTC3894E, LTC3894I.......................... –40°C to 125°C TRACK/SS 10 11 PLLIN/MODE

Storage Temperature Range................... –65°C to 150°C FE PACKAGE

ORDER INFORMATION http://www.linear.com/product/LTC3894#orderinfo

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Pulse-Skipping Mode Operation Burst Mode Operation Transient Response:

3894 G01 3894 G02 3894 G03

Transient Response: Dropout Behavior

Soft Start-Up into a Prebiased

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TOTAL INPUT SUPPLY CURRENT (mA)

TOTAL INPUT SUPPLY CURRENT (µA)

Free Running Frequency Over Output Regulation vs Load Output Regulation vs

NORMALIZED ∆VOUT (%)

Overcurrent Protection Short-Circuit Protection VIN Line Transient Behavior

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Maximum Current Sense Maximum Current Sense

MAXIMUM CURRENT SENSE THRESHOLD (mV)

MAXIMUM CURRENT SENSE THRESHOLD (mV)

IVIN and ISENSE– vs VSENSE– IVIN and ISENSE– vs VSENSE–

100 25.000 25.000

IVIN AND ISENSE+ (µA)

IVIN and ISENSE– vs VSENSE– IVIN and ISENSE– vs VSENSE–

IVIN AND ISENSE– (mA)

1.000 1.000 IVIN RISING –200.000

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1.250 –0.60 6.88

(VIN –VCAP) REGULATION (%)

(VIN -VCAP) REGULATION (V)

1.200 –1.20 6.75

1.150 –1.80 6.63

1.100 –2.40 6.50

1.050 –3.00 125°C 6.38 125°C

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EXT CEXTG 1.26V –

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the equation: 900.0

REFERENCE CURRENT (kHz)

or the GATE signal that drives the external P-MOSFET. 100.0

3894 F01 The free-running switching frequency can be programmed

14 For more information www.analog.com

tor, ESR losses in the output capacitors and results in VIN

lower output ripple. The highest efficiency operation can GATE

A reasonable starting point for ripple current is 40% of SENSE–

25% of the current limit determined by RSENSE. Lower C1* R2

Inductor Core Selection Inductor Current Sensing

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