This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2805685, IEEE
Transactions on Power Electronics

Single-Stage Switched-Capacitor Module (S3CM)

Topology for Cascaded Multilevel Inverter
Sze Sing Lee, Member, IEEE

Abstract: - A two-stage switched-capacitor based multilevel compared to H-bridge.

inverter possesses a drawback such that switches in the second Switched-capacitor based topology is another promising
stage (i.e. H-bridge) endure higher voltage stress. To resolve this compact module which is gaining popularity in the recent years,
problem, this letter proposes a single-stage switched-capacitor mainly attributed to its voltage boosting capability which has made
module (S3CM) topology for cascaded multilevel inverter which the reduction in the number of dc sources possible [7], [8]. An
ensures the peak inverse voltage across all switches within the dc innovative switched-capacitor module (SCM) topology recently
source voltage. Nine voltage levels can be generated with only one reported in [9] is capable of generating up to 9 voltage levels with
dc source and two incorporated capacitors. Hence, the number of a single dc source. Voltage boosting is validated with the
isolated dc sources are significantly reduced compared to cascaded achievement of its maximum voltage level twice of the input dc
H-bridge. In addition, voltage boosting gain of two is achieved. A source. Capacitor voltage balancing is not a concern since two
comparative analysis against the recent topology reveals that the capacitors are integrated such that their average voltage are equal
proposed S3CM topology achieves switch count reduction. The during operation.
operation of the proposed topology is validated through circuit It is worth mentioning that SCM in [9] is a two-stage topology
analysis followed by experimental results of a single module (9- consisting of a switched-capacitor circuit and a H-bridge, as
level) prototype. illustrated in Fig.1. Switches in the H-bridge (second stage) have
to withstand voltage twice of the input dc source. In case it is used
Index Terms: Cascaded multilevel inverter, single-stage, switched- for high-voltage applications, two series-connected switches are
capacitor module required for S7 – S10 and S5 to ensure the PIV of all switches do
not exceed dc source voltage (Vdc). In this instance, each SCM is
I. INTRODUCTION comprised of a diode and a total switch count of 15.
The initiative of this work is to establish an alternative topology,
Cascaded H-bridge (CHB) multilevel inverter (MLI) is termed as single-stage switched-capacitor module (S3CM) which
ubiquitous in high-voltage applications due to its inherent resolved the drawbacks of Fig. 1, while at the same time retaining
modularity [1]. Alternatively, there are recent attempts to replace all its benefits. The PIV of all switches in the proposed S3CM are
H-bridge by establishing module topologies which is capable of within the dc source voltage, Vdc. The paper is organized as follows:
generating more voltage levels with reduced switch count [2]. section II presents the proposed module topology for cascaded MLI
Among the various module topologies, an envelope type of and the comparative analysis against Fig. 1 and CHBMLI, section
module presented in [3] utilizes a combination of T-type inverter III discusses the experimental results of a prototype, and finally
and some additional switches to control four unequal dc sources. section IV draws the conclusion.
On the other hand, [4] demonstrated a square T-type module
comprises two back-to-back connected T-type inverters which is II. PROPOSED S3CM TOPOLOGY
able to produce 17 levels with only 12 switches and four unequal
dc sources. Similar concept with further switch count reduction is The proposed S3CM topology is able to generate up to nine
proposed in [5], [6]. Nonetheless, unlike CHB where all switches voltage levels. It is constituted by twelve switches, two capacitors
are restricted their peak inverse voltage (PIV) within one level (one and only one dc source, as depicted in Fig. 2. The number of levels
dc source), these newly established module topologies entails some and output voltage can be further increased by cascading multiple
of their switches to block voltage greater than one level (sum of all (N) modules. It is worth emphasized that the PIV of all switches in
the dc sources) during OFF state, thus renders them less appropriate the proposed S3CM topology are equivalent to Vdc, with the
for high-voltage applications. Despite multiple series-connected exception of two switches, i.e. S9 and S10 which blocks only half
switches can be implemented to cater for PIV greater than one level, of the Vdc. With merely low voltage rating switches, it can
they will essentially forfeit their merit of switch count reduction accomplish output voltage up to twice Vdc . On that account, it does
not require series-connected switches when high-voltage
Manuscript received January 11, 2018; revised and resubmitted January 30, applications is considered.
2018; accepted February 9, 2018.
S. S. Lee is with University of Southampton Malaysia Campus (USMC), Johor
Detailed circuit analysis concerning switching states of the
Bahru 79200, Malaysia (e-mail: [email protected] ). proposed module topology is illustrated in Fig. 3. A comparative

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2805685, IEEE
Transactions on Power Electronics

analysis among cascaded MLI with the proposed S3CM, the SCM are kept within Vdc. Therefore, two series-connected switches must
topology [9], and the H-bridge is conducted in Fig. 4. For fair be considered for S5 and S7–S10 for the SCM topology in [9] (Fig.
comparison, voltage stress of all the switches in these topologies 1).

Fig. 1. Switched-capacitor module (SCM) topology presented in [9]. Fig. 2. The proposed single-stage switched-capacitor module (S3CM) topology for
cascaded MLI.

Fig. 3. Switching states of the proposed S3CM topology.

TABLE I
EQUATIONS FOR CASCADED MLI USING DIFFERENT MODULES WITH
ALL SWITCHES PIV WITHIN THE DC SOURCE, Vdc
Proposed S3CM SCM in [9] H-Bridge
Levels 8N+1 8N+1 2N+1
Switches 12N 15N 4N
Diodes - N -
DC sources N N N
Capacitors 2N 2N -
Voltage gain 2 2 1
Fig. 4. Comparative analysis for cascaded MLI using the proposed S3CM, SCM N = number of cascaded modules/H-bridges
[9] (Fig. 1) and H-bridge. Voltage gain = ratio of the maximum voltage level to the sum of all dc sources

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2805685, IEEE
Transactions on Power Electronics

With cascaded H-bridge as a benchmark, cascaded MLI using III. SIMULATION AND EXPERIMENTAL RESULTS
both the SCM topology in [9] and the proposed S3CM topology
illustrate less number of switches for a given voltage level, with the Simulations were conducted for both the steady-state and
latter results in more switch count reduction. Besides, both dynamic conditions. Fig. 6 shows the output voltage, load current
topologies demonstrate the same number of dc sources, which is and capacitors voltage for N=1. Seven voltage levels are clearly
also significantly less than the cascaded H-bridge for all voltage seen with both capacitors voltages balanced averagely about 100V.
levels. It is also worth emphasized that cascaded H-bridge and the Unequal capacitances for C1 and C2 were then simulated
proposed S3CM topology require no diode in their circuitry, while considering 20% tolerances in each capacitor. Result depicted in
N diodes are mandatory in the SCM topology [9]. All equations Fig.7 demonstrates that both the capacitor voltages are still
related to the compared modules for cascaded MLI are summarized oscillating around 100V albeit the different peak-to-peak
in Table I. magnitude. The voltage ripple across C1 is smaller than that across
Some detailed comparisons between the proposed S3CM C2 due to its higher capacitance. A step load change was also
topology and the SCM topology in [9] are depicted in Fig. 5. It is conducted with load current increased to twice its original
worth emphasize that the switching sequences of the capacitors in magnitude. Findings from Fig.8 show that the capacitors voltages
S3CM are identical to that in [9]. C1 discharges for a longer period are slightly unbalanced after the step load change and gradually
during the positive half-cycle while C2 discharges for a longer stabilizes at 100V, which once again confirming its capacitor
period in the negative half-cycle. Nonetheless, they have equal voltage balancing ability during operation.
discharging periods when symmetrical ac voltage is under
consideration. This implies their equal average voltage, as similar
to [9].
The number of conducting semiconductor devices and the
number of switching transitions between both topologies are also
considered for power conversion efficiency comparison purpose.
Considering PIV for all switches are within Vdc, the proposed S3CM
has less conducting switches for 1.5Vdc, 2Vdc, -1.5Vdc and -2Vdc,
indicating its lower conduction loss. Besides, it also presents less
number of switch/diode commutations for all voltage level
transitions, except when the transition is between Vdc and 1.5Vdc.
Its two zero states introduces more switching transitions when the Fig. 6. Simulated steady-state waveforms for single S3CM (9-level).
output voltage is 0V. The proposed S3CM topology exhibits a total
of 56 switching transitions over one fundamental cycle, as oppose
to a total of 88 switching transitions in the SCM topology [9],
which signifies its advantage of lower switching loss.

Fig. 7. Simulated capacitor voltage considering 20% tolerances in capacitance.

Fig. 8. Simulated waveforms for step load change.

Sinusoidal pulse width modulation (SPWM) which is

prevalently used in industrial applications is employed to further
verify the operation of the proposed S3CM. The corresponding
simulation results under two different modulation indexes for the
Fig. 5. Comparisons between the proposed S3CM and the SCM in [9]. case of purely resistive load and resistive-inductive load are shown
in Fig. 9(a) and (b) respectively. Three voltage levels, i.e. 0.5Vdc, 0,
and -0.5Vdc are sufficient for generating low voltage at modulation
index of 0.2, indicating the feasibility of wide range modulation
index in the proposed S3CM topology.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2805685, IEEE
Transactions on Power Electronics

Note that the simulation considers ideal capacitors (C1 and C2)
without internal series resistance, their voltage waveforms are thus
showing instant charging with approximately zero rise time, as
opposed to the slower rising time as shown in the experiment. In
both simulation and experimental waveforms, the longest
discharging period for C1 and C2 takes place when the output
voltage equals to {1.5Vdc, 2Vdc} and {–1.5Vdc, –2Vdc} respectively.
Good agreement between experimental and simulation waveforms
(a) further confirms the validity of the proposed S3CM topology.

IV. CONCLUSION

In this letter, a 9-level inverter module based on single-stage

switched-capacitor circuit is established for cascaded MLI. The
proposed S3CM topology requires only single dc source with a
voltage boosting gain of two. Circuit analysis demonstrated that the
(b) voltage stress across all switches are within the dc source voltage.
Fig. 9. Simulated waveforms with sinusoidal pulse width modulation (SPWM) for Therefore, it is capable of generating more levels and higher
(a) purely resistive load, and (b) resistive-inductive load. voltages up to twice the dc source by using switches with low
voltage rating. Comparative analysis against the recent SCM
topology and the H-bridge for cascaded MLI validates its merits of
reduced switch count as well as reduced dc source count. The
performance of the proposed topology are convincingly validated
via experiments, with all the results are in good agreement with
theoretical analysis. The improvements of the proposed S3CM
topology made it an attractive alternative for high-voltage dc-ac
power conversion systems.

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