IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO.

3, MARCH 2021 2505

Letters
A High Step-Up Switched-Capacitor 13-Level Inverter With Reduced
Number of Switches
Ki-Mok Kim , Jung-Kyu Han , and Gun-Woo Moon

Abstract—This letter presents a new single-phase 13-level switched- However, two symmetrical dc sources are required to regulate the
capacitor inverter with a reduced number of switches and a voltage boost voltage of the clamping capacitors. A back-end H-bridge (HB) in
gain of 6. The proposed topology with a single dc source can achieve 13-level
output, sextuple boost, and self-voltage balance of capacitors using only [5]–[7] is used for generating negative voltage levels. However, four
14 switches. The proposed inverter does not use a back-end H-bridge switches on the HB must withstand the peak output voltage, making it
with four switches that must withstand the peak load voltage, and the unsuitable for high-voltage applications. On the other hand, a single-dc
voltage stress of all switches does not exceed half of the peak load voltage. source inverter without HB was presented in [8]. This topology has
The operation principle including the self-voltage balance of capacitors is
described in detail. An analysis of the proposed inverter in comparison to
lower voltage stress on individual switches; however, as the number of
recent topologies with a single-input dc source is performed mainly in terms voltage levels increases, the number of capacitors and power switches
of the number of switches and cost function. Simulation and experimental also increases. Two types of SC-based nine-level inverters with a single
results verify the feasibility of the proposed topology. dc source were presented in [9] and [10], respectively. Both can achieve
Index Terms—Boost inverter, multilevel inverters (MLIs), self-voltage the voltage balance of capacitors without auxiliary circuits and control.
balance, switched-capacitor (SC). Nonetheless, their voltage boost gain is only two. The topology with
a voltage boost gain of four and the least number of switches and
capacitors was proposed in [11]. However, two of the total switches
I. INTRODUCTION have to block the peak load voltage. In [12], a single-source inverter
with a voltage boost gain of four was presented. The voltage stress of
M ULTILEVEL inverters (MLIs) have been known as one of
the most popular solutions for power conversion of renewable
energy sources, such as photovoltaic cells, wind turbines, and fuel
its switches does not exceed twice the input dc voltage, but the switch
count is high.
cells [1]. The main advantages of MLIs are higher voltage operating In this letter, a 13-level (13L) switched capacitor inverter (13LSCI)
capability, lower dv/dt, low voltage stress on switches, and better with fewer switches and a high voltage gain is presented. The proposed
harmonic performance [2]. In general, there are three main types of MLI topology can achieve a 13L output and a voltage boost gain of 6
topologies:neutral-point-clamped MLI (NPC-MLI), flying capacitor using only 14 switches. In addition, the voltage stress of all power
MLI (FC-MLI), and cascade H-bridge MLI (CHB-MLI) [3]. As the switches is kept at less than half the peak load voltage; therefore, it
number of output levels increases, the number of clamping diodes is suitable for high-voltage applications. Moreover, the self-voltage
in NPC-MLI, flying capacitors in FC-MLI, and isolated dc sources balance of capacitors is guaranteed without using any auxiliary circuits
in CHB-MLI also increase significantly. Furthermore, NPC and FC or additional control methods.
topologies require auxiliary circuits and complicated control algorithms The circuit configuration, its operation principle including the self-
to maintain the voltage balance of the capacitors. In addition, a front-end voltage balance of capacitors, and the modulation method are described
dc–dc boost converter or a load-end transformer is required to achieve in detail in Section II. An analysis of the proposed topology in com-
a higher ac voltage [5]. All of these make the inverter system complex, parison to other recent topologies is carried out in Section III mainly in
bulky, and expensive. terms of the number of switches and the cost function (CF). Section IV
As a new approach to overcome the aforementioned drawbacks, presents simulation and experimental analysis, which were conducted
a switched-capacitor (SC)-based MLI (SCMLI) has been extensively to verify its feasibility and performance. Finally, the conclusion is
investigated. The SCMLI can effectively increase the number of output presented in Section V.
levels with switched capacitors and boost the input voltage without
any bulky transformer or inductor. The SC-based T-type topology in II. PROPOSED 13LSCI TOPOLOGY
[4] was presented with nine-level output voltage, which can maintain
the voltage balance of capacitors without auxiliary balance circuits. A. Circuit Description
Fig. 1 shows a circuit diagram of the proposed 13LSCI. It consists of
Manuscript received April 27, 2020; revised May 29, 2020 and July 4, 2020; one dc source, three capacitors, one diode, and only 14 power switches.
accepted July 21, 2020. Date of publication July 28, 2020; date of current The 13LSCI topology can generate up to 13 voltage levels, and the
version October 30, 2020. This work was supported by the National Research
Foundation of Korea (NRF) funded by the Korea government (MSIP) under number of output levels can be further expanded by connecting multiple
Grant 2019R1A2B5B02070509. (Corresponding author: Gun-Woo Moon.) (N) modules in series. The proposed topology has no back-end HB and
The authors are with the Department of Electrical Engineering, the peak inverse voltage (PIV) of all switches is limited to less than
KAIST, Daejeon 34141, South Korea (e-mail: [email protected]; half of the output load voltage, making it suitable for high-voltage
[email protected]; [email protected]).
Color versions of one or more of the figures in this article are available online applications. Also, the switches S3 and S4 can perform two operations
at https://ieeexplore.ieee.org. (charging and discharging of capacitors) at the same time in the states
Digital Object Identifier 10.1109/TPEL.2020.3012282 (2, 5, 9, 12), as shown in Fig. 2 and Table I, contributing to reducing

0885-8993 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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2506 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 3, MARCH 2021

TABLE I
SWITCHING STATES FOR THE PROPOSED INVERTER

Fig. 1. Circuit diagram of the proposed sextuple boost 13L inverter.

∗
C: Charge, D: Discharge

the number of switches. Moreover, without using a heavy and bulky

transformer or inductor, only three capacitors C1 , C2 , and C3 are used
to generate an output voltage six times higher than the input voltage,
which can increase the power density of the inverter system.

B. Operation Principle and Self-Voltage Balance

Current flow paths including the reverse current path for inductive
load and switching states are shown in Fig. 2 and Table I, respectively.
The proposed inverter has 13 operating states in a cycle. During one
cycle, positive, negative, and zero outputs are generated in states 1–6,
states 8–13, and state 7, respectively. To achieve a 13L output and
sextuple boost, capacitors C1 /C2 and C3 are expected to be charged on
Vin and 3Vin , respectively. In state 1, as shown in Fig. 2(a), capacitor
C1 is in parallel with dc source Vin and charged to Vin . Also, C1 and
C2 are connected in series with C3 , so that the total amplitude of Vin
is generated. In state 2, capacitor C2 is in parallel with the dc source
voltage and charged with Vin when both S4 and S11 are turned ON. At
the same time, Vin and capacitor C1 are connected in series through
S4 , generating the total amplitude of 2Vin . In state 3, Vin , C1 , and C2
are connected in series when both S3 and S4 are turned ON, so that
3Vin is delivered to the load. During state 3, capacitor C3 is connected
in parallel with 3Vin and charged with 3Vin . In state 4, Vin and C3
(charged to 3Vin ) are connected in series; thus, 4Vin is delivered to
load. In state 5, Vin and C1 are in series with C3 , and 5Vin is delivered
to the load. At the same time, C2 is charged with Vin . In state 6, Vin
and three capacitors (C1 , C2 , and C3 ) are connected in series, which
results in the generation of 6Vin . During state 6, all three capacitors are
discharged simultaneously. On the other hand, negative outputs in states
8 to 13 are generated symmetrically opposite to the positive outputs in
states 1 to 6. Finally, in state 7, zero outputs are generated, and C1 and
C2 are charged with Vin , as shown in Fig. 2(g) and (h), respectively.
All capacitors in the proposed topology are self-balanced by the
series-parallel operation. As shown in Fig. 2(a)–(h) and Table I, the
Fig. 2. Current flow paths and switching states at positive half-cycle and zero capacitors C1 , C2 , and C3 are equally charged in parallel and discharged
state. (a) State 1: vo = +1Vin . (b) State 2: vo = +2Vin . (c) State 3: vo = +3Vin . in series in a cycle. Therefore, the voltages of the three capacitors can
(d) State 4: vo = +4Vin . (e) State 5: vo = +5Vin . (f) State 6: vo = +6Vin . (g) be balanced at their respective values without any auxiliary circuits and
State 7: vo = +0. (h) State 7: vo = −0.
control.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 3, MARCH 2021 2507

D. Switching and Conduction Loss

The switching loss is caused by nonideal operation of switch devices,
which can be calculated by using the linear approximation of voltage
and current during turn-ON and turn-OFF period [7]. The switching
losses of the active switches are obtained by
 ton
1
Pon, k = f v (t) i (t) dt = f Vsw,k Ion ton (3)
0 6
 toff
1
Poff,k = f v (t) i (t) dt = f Vsw,k Ioff toff (4)
0 6
⎛ ⎞
14 
Non,k

Noff,k

Psw = ⎝ Pon,k,i + Poff,k,i ⎠ (5)

k=1 i=1 i=1

where ton and toff are turn-ON and turn-OFF time of the switch, respec-
tively. Ion is the switch current when the switch becomes fully turned
ON, and Ioff is the switch current prior to the turn-OFF of the switch. Vsw,k
is the OFF-state voltage of the kth switch. f is the fundamental frequency,
Non,k and Noff,k are the number of turning on and turning OFF the kth
switch during a fundamental period. The ton and toff are related to the
selected switch, while Vsw,k depends on the inverter topology.
In the proposed inverter, both S9 and S10 operate only once during
one fundamental period, so the values of Non,k and Noff,k are reduced.
Consequently, the switching loss that depends on the number of switch-
ing transitions is reduced. Moreover, the PIV of all switches in the
proposed topology is maintained at half the peak load voltage, so the
Vsw,k is reduced, reducing switching loss. In addition, the feature of
boost ability and relatively numerous levels with self-voltage balance
allows the proposed topology to operate at lower switching frequency,
contributing to reducing switching loss.
Fig. 3. Modulation method for the proposed 13L inverter. (a) PWM waveform. The conduction loss is mostly caused by the ON-state resistances
(b) NLevel and G against M. (c) PWM generator using FPGA. and forward voltage drops of devices in the output current paths. The
maximum output current flows through devices at maximum number
of output levels (NLevel,max ), which causes the largest voltage drop
across switch devices, resulting in the largest conduction loss. In
C. Modulation Method this respect, the number of conducting devices (NCD,max ) including
switches and diodes at NLevel,max was investigated for the evaluation
In this work, the phase disposition level-shifted carrier pulsewidth of conduction loss between the topologies, which is listed in Table
modulation (PWM) (PD-LSC-PWM) [5], [11] is adopted for modulat- II. The numbers in parentheses indicate the value including additional
ing the proposed 13L inverter. As shown in Fig. 3(a), the six triangular switches as described in Section III. In the proposed circuit, the number
carriers (vc1 –vc6 ) of the same frequency with the same peak-to-peak of conducting switches at NLevel,max is 7, which is a smaller value
amplitude are disposed, and compared with a sinusoidal reference (|vref compared to 13L topologies in [5]–[8], whereas it has a larger value
|). When |vref | is greater than the triangular carriers, the active switches than 9-level topologies in [9]–[12].
are turned on, and vice versa. The modulation index (M) and voltage
gain (G) are defined, respectively, as
III. COMPARATIVE ANALYSIS

Aref To evaluate the advantages and disadvantages of the proposed topol-

M= (1) ogy, it was compared to similar recent topologies with a single input dc
6Ac
source mainly in terms of the number of switches (Nsw ) and CF. Com-
Vo parative results are listed in Table II. To make an acceptable assessment
G= (2)
Vin between the topologies with different output levels and voltage gain, the
proportion of Nsw and CF over the number of output levels (NLevel )
where Aref , Ac , and Vo are the amplitude of the reference voltage, the was used. The PIV of all switches in the proposed 13LSCI does not
carrier voltage, and the output bus voltage, respectively, and Vin is the exceed half of the peak load voltage (6Vin ), whereas four switches on the
input dc source voltage. The output voltage levels and voltage gain (G) HB in [5]–[7] and two switches in [11] have to withstand the peak load
change depending on the value of the modulation index (M). The range voltage. Therefore, for high-voltage applications, two series-connected
of the number of output levels (NLevel ) and G is from 13 to 3, and from switches with half rating (3Vin ) each are required for [5]–[7] and [11].
6 to 1, respectively, as shown in Fig. 3(b). The PD-LSC-PWM for the In this instance, additional four and two switches would be required for
proposed topology is implemented by the FPGA-based PWM generator [5]–[7] and [11], respectively. The values of Nsw , Ngd , NNSW , and
Level
CF
shown in Fig. 3(c). N
including these additional switches are indicated by numbers
Level

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2508 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 3, MARCH 2021

TABLE II
COMPARISON BETWEEN THE PROPOSED TOPOLOGY AND OTHER RECENT TOPOLOGIES

∗
NSW , Ngd , Nd , Ncap , and NLevel : Number of switches, gate drivers, diodes, capacitors, and output levels, respectively. NCD,max : Number of conducting devices
including switches and diodes at maximum number of output levels. Gm : Maximum gain

Fig. 4. Simulated waveforms. (a) Output voltage (vo ) and load current (io ) at M = 0.9. (b) vo and io at M = 0.35. (c) Capacitors’ voltage at M = 0.9.
(d) Capacitors’ voltage at M = 0.35.

in parentheses in Table II. Considering the numbers in parentheses, the is smaller than that of other recent topologies for both α= 0.5 and α=
proposed topology and [6] has the smallest value with respect to NNSW , 1.5. Consequently, the proposed topology has remarkable advantages
Level
but [6] requires nine more diodes and two more capacitors compared to in terms of reducing the number of switches and the overall cost.
the proposed circuit. Furthermore, compared to the proposed 13LSCI
with sextuple boost, [11] requires two more diodes and the maximum IV. SIMULATION AND EXPERIMENTAL RESULTS
voltage gains of [9], [10] and [11], [12] are only 2 and 4, respectively.
The CF is used to evaluate the overall cost in comparison with the The simulations and experimental verification of the proposed 13L
aforementioned topologies, which can be expressed as topology were conducted by using PSIM software and an experimental
prototype. The circuit parameters for the simulation and experimental

CF = Nsw + Ngd + Nd + Ncap + α T SV(pu) (6) system are listed in Table III. The simulated waveforms are shown in
Fig. 4(a)–(d). Fig. 4(a) shows the waveforms of output voltage and load
where α is the weight coefficient to measure the importance between the current at a modulation index M of 0.9. It can be observed that the output
number of components and T SV(pu) (total standing voltage per unit) voltage waveform contains 13L, and the peak value of the output voltage
[1]. As seen in Table II, the value of N CF in the proposed inverter reaches approximately 336 V at the input of 56V, thus, verifying the 13L
Level

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 36, NO. 3, MARCH 2021 2509

TABLE III amplitude was slightly lower than the theoretical amplitude. This is
INVERTER PARAMETERS IN THE SIMULATION AND EXPERIMENT caused by the voltage reduction of the capacitors, the internal resistance
of the switch devices, and the line impedances. The simulation and
experimental results are consistent with the theoretical analysis.

V. CONCLUSION
This letter presented a 13L inverter topology with reduced switch
count, sextuple boost ability, and self-voltage balance. The proposed
topology with a single dc source employs only 14 switches without a
back-end HB to achieve the 13L and sextuple boost output. Compar-
ative analysis of the proposed topology and similar recent topologies
validates its advantages of reducing the number of switches and the
overall cost. Simulation and experimental results were presented to
validate the feasibility of the proposed topology, which were consistent
with the theoretical analysis. The proposed topology is expected to be
a competitive alternative for high voltage systems with low-dc input
sources.

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