998 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO.

3, MARCH 2021

A 13-Level Switched-Capacitor-Based
Boosting Inverter
N. Sandeep , Senior Member, IEEE

Abstract—A new boosting multilevel inverter with switched- need for an external boosting circuit thus making the circuit
capacitors is presented in this brief. By employing 13 switches, less complicated [6]–[8].
two diodes, and three capacitors, a 13-level voltage waveform is With the advantage of the SC technique, several MLIs for
synthesized. The capacitor voltages are self-balanced as they are
connected in parallel with the input voltage source for several a higher number of voltage levels have been presented in the
instances in every fundamental cycle. A simple logic gate based literature as an effort to realize a structure with the least num-
pulse-width modulation scheme ensuring power balance among ber of components. A 13-level (13L) inverter in [9] employs
the capacitors is presented. Experimental results obtained from four dc sources and ten switches. Further to this, a “K” type
a laboratory prototype are presented for validating the operation structure in [10] reduces the number of dc sources by two
and ability of the proposed inverter to boost the input by a factor
of six. Finally, a detailed comparison with existing topologies at the cost of three more switches. Despite the effective use
proves the cost-effectiveness, a simpler structure requiring lesser of SCs in [11]–[13], the switch count stands still high while
space and footprint area of the proposed topology. a few of the switches are to be rated for peak output voltage
Index Terms—Multilevel inverter (MLI), switched-capacitor, which is proportional to the boosting factor of the inverter and
voltage boosting. thus unsuitable for high-voltage applications. On this line of
devising a cost-effective topology, recently, the authors in [14]
have developed a circuit requiring ten switches, four capaci-
I. I NTRODUCTION tors, and four diodes with a voltage gain of six. However, it
ULTILEVEL inverters (MLIs) have been widely still requires two switches rated for peak output voltage and
M accepted as a potential solution for high-efficiency elec-
tric power-electronic conversion systems by both research
has a higher total stored energy owing to four capacitors.
This brief presents a 13L SC-based inverter with a boosting
and industry community. The inherent features of MLIs like factor of six. The following are its prominent features:
reduced dv/dt, high-quality output waveform, lower switch- 1) The required number of switches and diodes are 13 and
ing frequency, etc., are the key reasons for the usage of two respectively.
MLIs in a variety of fields including motor drives, renewable 2) The peak inverse voltage for each of the switch is within
energy sources integration, locomotives, to name a few [1]. thrice the input dc source voltage magnitude.
The basic MLIs are cascaded H-bridge (CHB), neutral point 3) Inherent polarity reversal capability.
clamped, and flying capacitor inverters [2]. For a higher num- 4) Only three SCs are required and are inherently balanced
ber of voltage levels, despite many variants of these basic without the need for any sensors or complex control
MLIs are available, i.e., symmetric CHB (SCHB), asymmetric methods.
CHB (ACHB), hybrid NPC with CHB, etc., overall the struc- 5) Four out of 13 switches operate only once in every half-
ture requires a huge number of components and increases the cycle yielding in reduced switching losses.
control complexity. The operation of the proposed topology and the
To overcome the aforesaid issue, several novel MLI topolo- developed pulse-width modulation (PWM) scheme are
gies with reduced component count have been presented [3]. detailed. Experimental tests are performed to validate the cor-
However, the recent trend is towards the use of switched- rectness and the obtained results for steady-state and transient
capacitor (SC) based MLIs [4]. While a majority of SCMLIs conditions are presented. A comprehensive comparative study
are buck type, additional boosting circuits are required espe- is included to prove the merits of the proposed topology
cially in a system powered by solar photovoltaics, fuel cell, or against the existing solutions.
electric vehicle battery [5]. Further, the idea of using SCs in
series/parallel with the input voltage source has eliminated the
II. P ROPOSED 13L I NVERTER T OPOLOGY
Manuscript received August 11, 2020; accepted August 14, 2020. Date of An SC-based 13L inverter is proposed in Fig. 1. It con-
publication August 18, 2020; date of current version February 26, 2021. This sists of 13 switches S1 -S9 with four complementary switches,
brief was recommended by Associate Editor B.-H. Gwee.
The author is with the Department of Electrical Engineering, Malaviya two diodes D1 and D2 , as well as three capacitors C1 -C3 .
National Institute of Technology Jaipur, Jaipur 302017, India (e-mail: The dc input voltage to the inverter is designated as Vdc and
[email protected]). vab is the inverter output voltage. The frontend (left of dc-
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. bus) of the inverter composing of switches S1 , S2 , S̄1 and
Digital Object Identifier 10.1109/TCSII.2020.3017338 S̄2 with diodes D1 and D2 as well as capacitors C1 and C2
1549-7747 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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SANDEEP: 13-LEVEL SWITCHED-CAPACITOR-BASED BOOSTING INVERTER 999

TABLE I
S WITCHING S TATES AND T HEIR E FFECT ON SC S OF THE P ROPOSED 13L I NVERTER

overall reduced power losses. Also, the switches S3 and S5

have the least switching transitions. As mentioned before, the
self-voltage balancing of SCs is ensured by connecting them
in parallel for charging and in series to discharge. Capacitors
C1 and C2 are connected in parallel with the input dc voltage
source during the voltage levels ±Vdc and ±4Vdc , therefore,
are charged to level Vdc . During the voltage levels, ±2Vdc
and ±5Vdc , either C1 or C2 is discharged while the other gets
charged depending on the chosen switch state, i.e., the capac-
itor connected in series with the input dc source discharges.
Thus, there exists redundancy in switching that can be used to
Fig. 1. Circuit topology of the proposed 13L inverter.
replenish that capacitor with larger energy deficiency thereby
the voltage is recovered. In the proposed topology, the redun-
forms a voltage tripler circuit. Assuming that C1 -C2 are large dant switching states are available for voltage levels ±2Vdc and
enough to maintain a constant dc voltage while neglecting the ±5Vdc and a total of 17 states are possible for synthesizing a
on-state resistance and forward voltage drop of the switching 13L stepped ac voltage. Therefore, it is crucial to select and
devices, three different dc-bus voltages (Vdc-bus ) can be gener- arrange these states effectively. Application of switching states
ated. The voltage across C1 -C2 and C3 is maintained at Vdc and two and 16 yields vab = 2Vdc , however, due to continuous
3Vdc respectively without the need for any closed-loop control. discharge, the capacitor C1 experiences larger voltage ripple
In other words, using the technique of series/parallel connec- across it. Hence, these redundant states are to be employed on
tion, the self-voltage balancing of SCs is ensured. This feature an alternate basis to replenish the SCs within the fundamen-
lessens the complexity and cost of the proposed inverter. tal cycle of the output voltage. The capacitance value of the
SCs is chosen based on the longest discharge period, maxi-
mum allowable ripple voltage for a given maximum current
A. Operating Principle and SC Voltage Balancing as detailed in [15].
The various switching states and the active switches for each
of the output voltage levels during the positive half cycle are
shown in Table I and Fig. 2 respectively. In Table I, the entry
“1” and “0” corresponds to the ON and OFF condition of a B. PWM Strategy
particular switch respectively. In Fig. 2, the effect of each of A simple level-shifted PWM scheme is employed for the
the switching states on the SCs voltage is distinctly marked gating signal generation as shown in Fig. 3. A rectified
for a better comprehension. Since four of the 13 switches are sinusoidal reference signal |uref | is compared with six high-
complementary, only nine gating signals have to be synthe- frequency triangular waveforms u1 − u6 . A suitable logic
sized. It is worth highlighting that the switches S8 , S̄8 , S9 , and is applied to the outputs of these comparators yielding in
S̄9 need to be switched only once in every half cycle [refer the level information of the output voltage to be gener-
Table I], thus, have negligible switching losses resulting in ated [16]. The modulation index for such an arrangement is

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1000 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 3, MARCH 2021

Fig. 3. Logic for PWM signal generation.

TABLE II
C OMPARATIVE S UMMARY OF D IFFERENT SC-BASED S INGLE
DC-S OURCE B OOSTING I NVERTER T OPOLOGIES

Fig. 2. Operating states and active switches for positive output voltage levels.

vref
defined as Ma = 6×v cr
with vref and vcr being the ampli-
tude of the reference and triangular waveform respectively.
Among the redundant states, only the combination of switch-
ing states 2-16 with 6-12 or 3-15 with 7-11 will result in
equal power-sharing among the capacitors C1 and C2 owing
to the symmetrical charging/discharging. Thus, the voltage rip-
ple among them will be identical. Further, the gating signals
are obtained by using the level indicator signals and Table I.
For instance, if the chosen combination is 2-16 with 6-12,
then, switch S1 needs to be turned ON for states 4, 5, and 8 comparison are capable of generating a 13L voltage. The
during the positive half cycle and 10, 12, 14, and 16 during switch count for the proposed topology is higher than a few
the negative half cycle. The level indicator outputs corre- of its counterparts. However, the diode count is the least
sponding to these states are tapped and after applying the for the proposed topology. Similar to other prevalent circuits,
suitable logic, the gating signal is generated. A similar pro- the proposed topology also requires a single dc source. The
cess is repeated for deriving gating signals for the rest of the topologies in [9], [10], [20] exhibits a voltage gain of no more
switches. than two, thus, need additional boosting stage.
Among the topologies with a voltage gain of six, the
proposed topology exhibits the least total standing voltage
III. C OMPARISON W ITH OTHER S IMILAR T OPOLOGIES (TSV) which is the sum of maximum voltage to be blocked
A comparative study between the proposed topology and by each of the semiconductor devices. The factor TSV dic-
the existing solution has been carried out. The summary of tates the cost requirement of the semiconductor. This factor
comparison is enlisted in Table II. All the topologies under of least TSV is attributed to the fact that none of the devices

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SANDEEP: 13-LEVEL SWITCHED-CAPACITOR-BASED BOOSTING INVERTER 1001

Fig. 4. Experimental results depicting (a)-(b) Steady-state operation for resistive loading (c)-(d) Steady-state operation for resistive-inductive loading (e)-(f)
Performance during step-change in loading (g)-(h) Performance with undesired initial SC voltages. (i)-(l) Standing voltage across the switching power devices.

in the proposed topology need to block a voltage more than same rating. This factor aids in the reduction of space, cost
3Vdc . While the topology in [14] has a lesser switch count, and footprint requirements of the proposed topology.
two of the ten switches need to block a voltage of 6Vdc .
Therefore, assuming a uniform blocking voltage of not more
than 3Vdc , [14] requires a total of 12 switches. The maxi- IV. R ESULTS AND D ISCUSSION
mum blocking voltage (MBV) for the proposed topology is To verify the feasibility of the proposed 13L inverter, a
comparable to rest of all the reported structures. The other down-scale prototype was built and tested. Discrete IGBTs by
major size and cost influencer in any SC-based inverter are SEMIKRON driven by TLP250 drivers are used to build the
the capacitors. As evident from Table II, the capacitor count prototype. The gating pulses are generated using the dSPACE
is the least for the proposed topology. It is worth mentioning MicroLab box. The input dc voltage is set to 100 V while the
that, in contrast to the topology in [14] which requires two inverter is switched at 5 kHz. A 1.1 mF and 2.2 mF capac-
capacitors rated for 3Vdc , the proposed need only one of the itance were chosen for C1 − C2 and C3 respectively. For the

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1002 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 3, MARCH 2021

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