19-6306; Rev 6/12

DS1312
Nonvolatile Controller with Lithium Battery Monitor

FEATURES PIN ASSIGNMENT

 Converts CMOS SRAM into nonvolatile
memory VCCO 1 8 VCCI VCCO 1 8 VCCI
 Unconditionally write-protects SRAM when VBAT 2 7 BW VBAT 2 7 BW
VCC is out of tolerance TOL 3 6 CEO TOL 3 6 CEO
GND 4 5 CEI GND 4 5 CEI
 Automatically switches to battery backup
supply when VCC power failure occurs DS1312 8-Pin DIP DS1312S-2 8-Pin SOIC
 Monitors voltage of a lithium cell and (300 mils) (150 mils)

provides advanced warning of impending NC 1 16 NC NC 1 20 NC

battery failure VCCO 2 15 VCCI VCCO 2 19 VCCI
 Signals low-battery condition on active low NC 3 14 RST NC 3 18 RST
Battery Warning output signal VBAT 4 13 NC VBAT 4 17 NC
 Optional 5% or 10% power-fail detection NC 5 12 BW NC 5 16 NC
TOL 6 11 CEO NC 6 15 BW
 Space-saving 8-pin DIP and SOIC packages
NC 7 10 NC TOL 7 14 NC
 Optional 16-pin SOIC and 20-pin TSSOP GND 8 9 CEI NC 8 13 CEO
versions reset processor when power failure NC 9 12 NC
occurs and hold processor in reset during DS1312S 16-Pin SOIC GND 10 11 CEI
(300 mils)
system power-up DS1312E 20-Pin TSSOP
 Industrial temperature range of -40°C to
+85°C PIN DESCRIPTION
VCCI - +5V Power Supply Input
VCCO - SRAM Power Supply Output
VBAT - Backup Battery Input
CEI - Chip Enable Input
CEO - Chip Enable Output
TOL - VCC Tolerance Select
BW - Battery Warning Output
(Open Drain)
RST - Reset Output (Open Drain)
GND - Ground
NC - No Connection

DESCRIPTION
The DS1312 Nonvolatile Controller with Battery Monitor is a CMOS circuit which solves the application
problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-
of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write
protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry
uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery
consumption.

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 DS1312
In addition to battery-backup support, the DS1312 performs the important function of monitoring the
remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.
Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority
of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1312
performs such measurement by periodically comparing the voltage of the battery as it supports an internal
resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference
voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning
pin is activated to signal the need for battery replacement.

MEMORY BACKUP
The DS1312 performs all the circuit functions required to provide battery-backup for an SRAM. First, the
device provides a switch to direct power from the battery or the system power supply (VCCI). Whenever
VCCI is less than the switch point VSW and VCCI is less than the battery voltage VBAT, the battery is
switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts.

Second, the DS1312 handles power failure detection and SRAM write-protection. VCCI is constantly
monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and
inhibits chip enable output ( CEO ) in order to write-protect the SRAM. This is accomplished by holding
CEO to within 0.2 volts of VCCO when VCCI is out of tolerance. If CEI is (active) low at the time that
power failure is detected, the CEO signal is kept low until CEI is brought high again. Once CEI is
brought high, CEO is taken high and held high until after VCCI has returned to its nominal voltage level. If
CEI is not brought high by 1.5 µs after power failure is detected, CEO is forced high at that time. This
specific scheme for delaying write protection for up to 1.5 µs guarantees that any memory access in
progress when power failure occurs will complete properly. Power failure detection occurs in the range
of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts
(10% tolerance) when TOL is connected to VCCO.

BATTERY VOLTAGE MONITORING

The DS1312 automatically performs periodic battery voltage monitoring at a factory-programmed time
interval of 24 hours. Such monitoring begins within tREC after VCCI rises above VCCTP, and is suspended
when power failure occurs.

After each 24-hour period (tBTCN) has elapsed, the DS1312 connects VBAT to an internal 1.2 MΩ test
resistor (RINT) for one second (tBTPW). During this one second, if VBAT falls below the factory-
programmed battery voltage trip point (VBTP), the battery warning output BW is asserted. While BW is
active battery testing will be performed with period tBTCW to detect battery removal and replacement.
Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell.
The battery is still retested after each VCC power-up, however, even if BW was active on power-down. If
the battery is found to be higher than VBTP during such testing, BW is deasserted and regular 24-hour
testing resumes. BW has an open-drain output driver.

Battery replacement following BW activation is normally done with VCCI nominal so that SRAM data is
not lost. During battery replacement, the minimum time duration between old battery detachment and
new battery attachment (tBDBA) must be met or BW will not deactivate following attachment of the new

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 DS1312
battery. Should BW not deactivate for this reason, the new battery can be detached for tBDBA and then re-
attached to clear BW .
NOTE: The DS1312 cannot constantly monitor an attached battery because such monitoring would
drastically reduce the life of the battery. As a result, the DS1312 only tests the battery for one second out
of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that
has not been previously flagged with BW ) is removed between battery tests, the DS1312 may not
immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery
is then reattached to the DS1312, the battery may not be tested until the next scheduled test.

NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire
life of a lithium battery. Because the DS1312 only performs battery monitoring when VCC is nominal,
systems which are powered-down for excessively long periods can completely drain their lithium cells
without receiving any advanced warning. To prevent such an occurrence, systems using the DS1312
battery monitoring feature should be powered–up periodically (at least once every few months) in order
to perform battery testing. Furthermore, anytime BW is activated on the first battery test after a power-up,
data integrity should be checked via checksum or other technique.

POWER MONITORING
DS1312S and DS1312E varieties have an additional reset pin. These varieties detect out-of-tolerance
power supply conditions and warn a processor-based system of impending power failure. When VCCI falls
below the trip point level defined by the TOL pin (VCCTP), the VCCI comparator activates the reset signal
RST . Reset occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is connected to
GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to VCCO.

RST also serves as a power-on reset during power-up. After VCCI exceeds VCCTP, RST will be held active
for 200 ms nominal (tRPU). This reset period is sufficiently long to prevent system operation during
power-on transients and to allow tREC to expire. RST has an open-drain output driver.

FRESHNESS SEAL MODE

When the battery is first attached to the DS1312 without VCC power applied, the device does not
immediately provide battery-backup power on VCCO. Only after VCCI exceeds VCCTP will the DS1312
leave Freshness Seal Mode. This mode allows a battery to be attached during manufacturing but not used
until after the system has been activated for the first time. As a result, no battery energy is drained during
storage and shipping.

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 DS1312
FUNCTIONAL BLOCK DIAGRAM Figure 1

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 DS1312
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.5V to +6.0V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature (reflow, SO or TSSOP) +260°C
Lead Temperature (soldering, 10s) +300°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

PDIP
Junction-to-Ambient Thermal Resistance (θJA).…………………...………………………....110°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………40°C/W
8 SO
Junction-to-Ambient Thermal Resistance (θJA).……………………………………………...132°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………38°C/W
16 SO
Junction-to-Ambient Thermal Resistance (θJA).…………………...………………………......71°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………23°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (θJA).……………………………………………..73.8°C/W
Junction-to-Case Thermal Resistance (θJC)……………………………………………………20°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board for the SMT packages. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-
tutorial.

RECOMMENDED OPERATING CONDITIONS (-40°C to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage TOL=GND VCCI 4.75 5.0 5.5 V 2
Supply Voltage TOL=VCCO VCCI 4.5 5.0 5.5 V 2
Battery Supply Voltage VBAT 2.0 6.0 V 2
Logic 1 Input VIH 2.0 VCCI+0.3 V 2, 13
Logic 0 Input VIL -0.3 +0.8 V 2, 13

DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI >VCCTP)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Operating Current (TTL inputs) ICC1 200 400 µA 3
Operating Current (CMOS inputs) ICC2 50 100 µA 3, 6
RAM Supply Current ICCO1 140 mA 4
(VCCO ≥ VCCI -0.2V)
RAM Supply Current ICCO1 200 mA 5
(VCCO ≥ VCCI -0.3V)
VCC Trip Point (TOL=GND) VCCTP 4.50 4.62 4.75 V 2
VCC Trip Point (TOL=VCCO) VCCTP 4.25 4.37 4.50 V 2
VBAT Trip Point VBTP 2.5 2.6 2.7 V 2
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 DS1312
VCC/VBAT Switch Point VSW 2.6 2.7 2.8 V 2
Output Current @ 2.4V IOH -1 mA 8, 11
Output Current @ 0.4V IOL 4 mA 8, 11
Input Leakage IIL -1.0 +1.0 µA
Output Leakage ILO -1.0 +1.0 µA
Battery Monitoring Test Load RINT 0.8 1.2 1.5 MΩ

DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI < VBAT; VCCI < VSW)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Current IBAT 100 nA 3
Battery Backup Current ICCO2 500 µA 7
Supply Voltage VCCO VBAT-0.2 V 2
CEO Output VOHL VBAT-0.2 V 2, 9

CAPACITANCE (TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance ( CEI , TOL) CIN 7 pF
Output Capacitance COUT 7 pF
( CEO , BW , RST )

AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI > VCCTP)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEI to CEO Propagation Delay tPD 5 10 ns
CE Pulse Width tCE 1.5 µs 12
VCC Valid to End of tREC 12 125 ms 10
Write Protection
VCC Valid to CEI Inactive tPU 2 ms
VCC Valid to RST Inactive tRPU 150 200 350 ms 11
VCC Valid to BW Valid tBPU 1 s 11

AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI < VCCTP)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Slew Rate tF 150 µs
VCC Fail Detect to RST Active tRPD 5 15 µs 11
VCC Slew Rate tR 150 µs

AC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI > VCCTP)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Battery Test to BW Active tBW 1 s 11
Battery Test Cycle-Normal tBTCN 24 hr
Battery Test Cycle-Warning tBTCW 5 s
Battery Test Pulse Width tBTPW 1 s
Battery Detach to Battery Attach tBDBA 7 s
Battery Attach to BW Inactive tBABW 1 s 11

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 DS1312
TIMING DIAGRAM: POWER-UP

NOTE:
If VBAT < VSW, VCCO will begin to slew with VCCI when VCCI = VBAT.

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 DS1312
TIMING DIAGRAM: POWER-DOWN

NOTE:
If VBAT < VSW, VCCO will slew down with VCCI until VCCI = VBAT.

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 DS1312
TIMING DIAGRAM: BATTERY WARNING DETECTION

NOTE:
tBW is measured from the expiration of the internal timer to the activation of the battery warning output
BW .

TIMING DIAGRAM: BATTERY REPLACEMENT

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 DS1312
NOTES:
2. All voltages referenced to ground.
3. Measured with outputs open circuited.
4. ICCO1 is the maximum average load which the DS1312 can supply to attached memories at VCCO >
VCCI -0.2V.
5. ICCO1 is the maximum average load which the DS1312 can supply to attached memories at VCCO >
VCCI -0.3V.
6. All inputs within 0.3V of ground or VCCI.
7. ICCO2 is the maximum average load current which the DS1312 can supply to the memories in the
battery backup mode.
8. Measured with a load as shown in Figure 2.
9. Chip Enable Output CEO can only sustain leakage current in the battery backup mode.
10. CEO will be held high for a time equal to tREC after VCCI crosses VCCTP on power-up.
11. BW and RST are open-drain outputs and, as such, cannot source current. External pull-up resistors
should be connected to these pins for proper operation. Both BW and RST can sink 10 mA.
12. tCE maximum must be met to ensure data integrity on power-down.
13. In battery-backup mode, inputs must never be below ground or above VCCO.
14. The DS1312 is recognized by Underwriters Laboratories (UL) under file E99151.

DC TEST CONDITIONS AC TEST CONDITIONS

Outputs Open Output Load: See below
All voltages are referenced to ground Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns

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 DS1312
OUTPUT LOAD Figure 2

ORDERING INFORMATION
TEMP
PART PIN-PACKAGE
RANGE
DS1312+ -40°C to +85°C 8 PDIP
DS1312S-2+ -40°C to +85°C 8 SO
DS1312S+ -40°C to +85°C 16 SO
DS1312E+ -40°C to +85°C 20 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.

PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

8 PDIP P8+2 21-0043 
8 SO S8+4 21-0041 90-0096
16 SO W16+1 21-0042 90-0107
20 TSSOP U20+1 21-0066 90-0116

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 DS1312
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1312 data
sheet. Please review this summary carefully.

1. Changed VBAT max to 6V

2. Changed tBABW from 75 to 1s max

3. Changed block diagram to show UL compliance

The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1312 data
sheet. Please review this summary carefully.

1. Changed AC test conditions

The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1312 data
sheet. Please review this summary carefully.

1. Specified Input Capacitance as being only for CEI , TOL and output capacitance as being only for
CEO , BW and RST . This is not a change but rather a clarification.

2. Add note 13 describing UL recognition.

The following represent the key differences between 08/29/97 and 6/12 version of the DS1312 data sheet.
Please review this summary carefully.

1. Update soldering, ordering, package info, and notes.

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reserves the right to change the circuitry and specifications without notice at any time.
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