M48Z128

M48Z128Y

1 Mbit (128Kb x8) ZEROPOWER SRAM

■ INTEGRATED LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and
BATTERY
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES 32

■ 10 YEARS of DATA RETENTION in the 1

ABSENCE of POWER PMDIP32 (PM)

■ AUTOMATIC POWER-FAIL CHIP DESELECT Module
and WRITE PROTECTION
SNAPHAT (SH)
■ WRITE PROTECT VOLTAGES Battery
(VPFD = Power-fail Deselect Voltage):
– M48Z128: 4.50V ≤ VPFD ≤ 4.75V
– M48Z128Y: 4.20V ≤ VPFD ≤ 4.50V
■ BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
■ PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 128K x 8 SRAMs
■ SURFACE MOUNT CHIP SET PACKAGING TSOP32
(8 x 20mm) SOH28
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED Surface Mount Chip Set Solution (CS)
SEPARATELY)
■ SOIC PACKAGE PROVIDES DIRECT Figure 1. Logic Diagram
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
■ SNAPHAT HOUSING (BATTERY) IS VCC
REPLACEABLE

17 8
Table 1. Signal Names
A0-A16 DQ0-DQ7
A0-A16 Address Inputs

DQ0-DQ7 Data Inputs / Outputs W M48Z128

M48Z128Y
E Chip Enable
E
G Output Enable
G
W Write Enable

VCC Supply Voltage

VSS Ground VSS

AI01194
NC Not Connected Internally

June 2000 1/17

M48Z128, M48Z128Y

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature 0 to 70 °C
TSTG Storage Temperature (V CC Off) –40 to 70 °C
TBIAS Temperature Under Bias –10 to 70 °C

TSLD (2) Lead Solder Temperature for 10 seconds 260 °C

V IO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Table 3. Operating Modes

Mode VCC E G W DQ0-DQ7 Power
Deselect VIH X X High Z Standby
Write 4.75V to 5.5V VIL X VIL D IN Active
or
Read 4.5V to 5.5V VIL VIL VIH DOUT Active
Read VIL VIH VIH High Z Active

Deselect VSO to VPFD (min) X X X High Z CMOS Standby

Deselect ≤ VSO X X X High Z Battery Back-up Mode

Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.

Figure 2. DIP Connections DESCRIPTION

The M48Z128/128Y ZEROPOWER RAM is a
128 Kbit x8 non-volatile static RAM that integrates
NC 1 32 VCC power-fail deselect circuitry and battery control
A16 2 31 A15 logic on a single die. The monolithic chip is avail-
A14 3 30 NC able in two special packages to provide a highly in-
A12 4 29 W tegrated battery backed-up memory solution.
A7 5 28 A13 The M48Z128/128Y is a non-volatile pin and func-
tion equivalent to any JEDEC standard 128K x8
A6 6 27 A8
SRAM. It also easily fits into many ROM, EPROM,
A5 7 26 A9 and EEPROM sockets, providing the non-volatility
A4 8 M48Z128 25 A11 of PROMs without any requirement for special
A3 9 M48Z128Y 24 G write timing or limitations on the number of writes
A2 10 23 A10 that can be performed. The 32 pin 600mil DIP
Module houses the M48Z128/128Y silicon with a
A1 11 22 E
long life lithium button cell in a single package.
A0 12 21 DQ7
For surface mount environments ST provides a Chip
DQ0 13 20 DQ6 Set solution consisting of a 28 pin 330mil SOIC
DQ1 14 19 DQ5 NVRAM Supervisor (M40Z300) and a 32 pin TSOP
DQ2 15 18 DQ4 (8 x 20mm) LPSRAM (M68Z128) packages.
VSS 16 17 DQ3 The 28 pin 330mil SOIC provides sockets with
AI01195 gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.

2/17
 M48Z128, M48Z128Y

Figure 3. Block Diagram

VCC
A0-A16

DQ0-DQ7
POWER 131,072 x 8
VOLTAGE SENSE
SRAM ARRAY
E AND
SWITCHING E
CIRCUITRY
W

G
INTERNAL
BATTERY

VSS AI01196

The unique design allows the SNAPHAT battery READ MODE

package to be mounted on top of the SOIC pack- The M48Z128/128Y is in the Read Mode whenev-
age after the completion of the surface mount pro- er W (Write Enable) is high and E (Chip Enable) is
cess. Insertion of the SNAPHAT housing after low. The device architecture allows ripple-through
reflow prevents potential battery damage due to access of data from eight of 1,048,576 locations in
the high temperatures required for device surface- the static storage array. Thus, the unique address
mounting. The SNAPHAT housing is keyed to pre- specified by the 17 Address Inputs defines which
vent reverse insertion. one of the 131,072 bytes of data is to be accessed.
The SNAPHAT battery package is shipped sepa- Valid data will be available at the Data I/O pins
rately in plastic anti-static tubes or in Tape & Reel within Address Access time (t AVQV) after the last
form. The part number is ”M4Z28-BRxxSH1”. address input signal is stable, providing that the E
The M48Z128/128Y also has its own Power-fail and G (Output Enable) access times are also sat-
Detect circuit. The control circuitry constantly mon- isfied. If the E and G access times are not met, val-
itors the single 5V supply for an out of tolerance id data will be available after the later of Chip
condition. When VCC is out of tolerance, the circuit Enable Access time (tELQV) or Output Enable Ac-
write protects the SRAM, providing a high degree cess Time (tGLQV). The state of the eight three-
of data security in the midst of unpredictable sys- state Data I/O signals is controlled by E and G. If
tem operation brought on by low VCC. As VCC falls the outputs are activated before t AVQV, the data
below approximately 3V, the control circuitry con- lines will be driven to an indeterminate state until
nects the battery which maintains data until valid tAVQV. If the Address Inputs are changed while E
power returns. and G remain low, output data will remain valid for
Output Data Hold time (t AXQX) but will go indeter-
minate until the next Address Access.

3/17
M48Z128, M48Z128Y

Figure 4. Hardware Hookup for SMT Chip Set (1)

THS(2) VOUT VCC

SNAPHAT E2
BATTERY(3)
M40Z300 M68Z128
DQ0-DQ7
E E1CON E
E2CON

E3CON

E4CON
A0-A16

A
RST
B W
BL
VSS VSS

AI03625

Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z128 at www.st.com.
2. Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z128).
3. SNAPHAT ordered separately.

Table 4. AC Measurement Conditions Figure 5. AC Testing Load Circuit

Input Rise and Fall Times ≤ 5ns
5V
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no longer 1.9kΩ
driven.
DEVICE
UNDER OUT
TEST

1kΩ CL = 100pF or 5pF

CL includes JIG capacitance

AI01030

4/17
 M48Z128, M48Z128Y

Table 5. Capacitance (1, 2)

(TA = 25 °C, f = 1MHz)
Symbol Parameter Test Condit ion Min Max Unit
C IN Input Capacitance VIN = 0V 10 pF

CIO (3) Input / Output Capacitance VOUT = 0V 10 pF

Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.

Table 6. DC Characteristics
(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol Parameter Test Conditio n Min Max Unit

ILI (1) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO (1) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC Supply Current E = VIL, Outputs open 105 mA

ICC1 Supply Current (Standby) TTL E = VIH 7 mA

ICC2 Supply Current (Standby) CMOS E ≥ VCC – 0.2V 4 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage IOH = –1mA 2.4 V

Note: 1. Outputs deselected.

Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C)
Symbol Parameter Min Typ Max Unit
M48Z128 4.5 4.6 4.75 V
VPFD Power-fail Deselect Voltage
M48Z128Y 4.2 4.3 4.5 V
V SO Battery Back-up Switchover Voltage 3 V

tDR (2) Data Retention Time 10 YEARS

Note: 1. All voltages referenced to VSS.
2. At 25 °C.

5/17
M48Z128, M48Z128Y

Table 8. Power Down/Up AC Characteristics

(TA = 0 to 70 °C)
Symbol Parameter Min Max Unit

tF (1) V PFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB (2) V PFD (min) to VSO VCC Fall Time 10 µs

tWP Write Protect Time from VCC = VPFD 40 150 µs

tR V SO to VPFD (max) VCC Rise Time 0 µs

tER E Recovery Time 40 120 ms

Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
es VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.

Figure 6. Power Down/Up Mode AC Waveforms

VCC
VPFD (max)

VPFD (min)

VSO

tF tDR tR

tFB

tWP tER

E RECOGNIZED DON’T CARE RECOGNIZED

HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)

AI01031

6/17
 M48Z128, M48Z128Y

Table 9. Read Mode AC Characteristics

(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z128/M48Z128Y
Symbol Parameter -70 -85 -120 Unit
Min Max Min Max Min Max
tAVAV Read Cycle Time 70 85 120 ns

tAVQV (1) Address Valid to Output Valid 70 85 120 ns

tELQV (1) Chip Enable Low to Output Valid 70 85 120 ns

tGLQV (1) Output Enable Low to Output Valid 35 45 60 ns

tELQX (2) Chip Enable Low to Output Transition 5 5 5 ns

tGLQX (2) Output Enable Low to Output Transition 3 3 3 ns

tEHQZ (2) Chip Enable High to Output Hi-Z 30 35 45 ns

tGHQZ (2) Output Enable High to Output Hi-Z 20 25 35 ns

tAXQX (1) Address Transition to Output Transition 5 5 10 ns

Note: 1. CL = 100pF.
2. CL = 5pF.

Figure 7. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A16 VALID

tAVQV tAXQX

DQ0-DQ7 DATA VALID

AI01078

Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.

7/17
M48Z128, M48Z128Y

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

tAVAV

A0-A16 VALID

tAVQV tAXQX

tELQV tEHQZ

tELQX

tGLQV tGHQZ

tGLQX
DQ0-DQ7 DATA OUT

AI01197

Note: Write Enable (W) = High.

WRITE MODE self tWP after VCC falls below VPFD. All outputs
The M48Z128/128Y is in the Write Mode whenev- become high impedance, and all inputs are treated
er W and E are active. The start of a write is refer- as ”don’t care.”
enced from the latter occurring falling edge of W or If power fail detection occurs during a valid ac-
E. A write is terminated by the earlier rising edge cess, the memory cycle continues to completion. If
of W or E. the memory cycle fails to terminate within the time
The addresses must be held valid throughout the tWP, write protection takes place. When VCC drops
cycle. E or W must return high for minimum of tE- below VSO, the control circuit switches power to
HAX from E or tWHAX from W prior to the initiation
the internal energy source which preserves data.
of another read or write cycle. Data-in must be val- The internal coin cell will maintain data in the
id tDVWH prior to the end of write and remain valid M48Z128/128Y after the initial application of VCC
for tWHDX or tEHDX afterward. G should be kept for an accumulated period of at least 10 years
high during write cycles to avoid bus contention; when VCC is less than VSO. As system power re-
although, if the output bus has been activated by a turns and VCC rises above VSO , the battery is dis-
low on E and G, a low on W will disable the outputs connected, and the power supply is switched to
tWLQZ after W falls. external VCC. Write protection continues for tER af-
ter VCC reaches VPFD to allow for processor stabi-
DATA RETENTION MODE lization. After tER, normal RAM operation can
With valid VCC applied, the M48Z128/128Y oper- resume.
ates as a conventional BYTEWIDETM static RAM. For more information on Battery Storage Life refer
Should the supply voltage decay, the RAM will au- to the Application Note AN1012.
tomatically power-fail deselect, write protecting it-

8/17
 M48Z128, M48Z128Y

Table 10. Write Mode AC Characteristics

(TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z128/M48Z128Y
Symbol Parameter -70 -85 -120 Unit
Min Max Min Max Min Max
tAVAV Write Cycle Time 70 85 120 ns

tAVWL Address Valid to Write Enable Low 0 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 0 ns

tWLWH Write Enable Pulse Width 55 65 85 ns

tELEH Chip Enable Low to Chip Enable High 55 75 100 ns

tWHAX Write Enable High to Address Transition 5 5 5 ns

tEHAX Chip Enable High to Address Transition 15 15 15 ns

tDVWH Input Valid to Write Enable High 30 35 45 ns

tDVEH Input Valid to Chip Enable High 30 35 45 ns

tWHDX Write Enable High to Input Transition 0 0 0 ns

tEHDX Chip Enable High to Input Transition 10 10 10 ns

tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 30 40 ns

tAVWH Address Valid to Write Enable High 65 75 100 ns

tAVEH Address Valid to Chip Enable High 65 75 100 ns

tWHQX (1, 2) Write Enable High to Output Transition 5 5 5 ns

Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low after W going low, the outputs remain in the high impedance state.

POWER SUPPLY DECOUPLING Figure 9. Supply Voltage Protection

and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, re-
sulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store en-
ergy, which stabilizes the VCC bus. The energy VCC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be VCC
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
9) is recommended in order to provide the needed 0.1µF DEVICE
filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg- VSS
ative voltage spikes on V CC that drive it to values
below VSS by as much as one Volt. These nega-
tive spikes can cause data corruption in the SRAM AI02169
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
nect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

9/17
M48Z128, M48Z128Y

Figure 10. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A16 VALID

tAVWH

tAVEL tWHAX

tWLWH

tAVWL

W
tWLQZ tWHQX

tWHDX

DQ0-DQ7 DATA INPUT

tDVWH
AI01198

Note: Output Enable (G) = High.

Figure 11. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A16 VALID

tAVEH

tAVEL tELEH tEHAX

tAVWL

tEHDX

DQ0-DQ7 DATA INPUT

tDVEH
AI01199

Note: Output Enable (G) = High.

10/17
 M48Z128, M48Z128Y

Table 11. Ordering Information Scheme

Example: M48Z128Y -70 CS 1

Device Type
M48Z

Supply Voltage and Write Protect Voltage

128 = VCC = 4.75V to 5.5V; VPFD = 4.5V to 4.75V
128Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V

Speed
-70 = 70ns
-85 = 85ns
-120 = 120ns

Package
PM = PMDIP32
CS (1) = Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z128 (TSOP32)

Temperature Range
1 = 0 to 70 °C

Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number
”M4Zxx-BR00SH1” in plastic tube or ”M4Zxx-BR00SH1TR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4Zxx-BR00SH1” in conductive foam since this will drain the lithium button-cell
battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 12. Revision History

Date Revision Details

May 1999 First Issue

Document Layout changed
04/13/00
Surface Mount Chip Set solution added

06/20/00 tGLQX changed (Table 9)

11/17
M48Z128, M48Z128Y

Table 13. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 9.27 9.52 0.365 0.375
A1 0.38 0.015

B 0.43 0.59 0.017 0.023

C 0.20 0.33 0.008 0.013
D 42.42 43.18 1.670 1.700
E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 34.29 41.91 1.350 1.650
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110

N 32 32

Figure 12. PMDIP32 - 32 pin Plastic Module DIP, Package Outline

A1 L C
S B e1 eA

e3

1
PMDIP

Drawing is not to scale.

12/17
 M48Z128, M48Z128Y

Table 14. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004

Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline

A2 A
C
B e eB
CP

D
N

E H

A1 α L
1

SOH-A

Drawing is not to scale.

13/17
M48Z128, M48Z128Y

Table 15. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

Figure 14. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline

A1 A2
A A3

eA B L
eB
D

SHZP-A

Drawing is not to scale.

14/17
 M48Z128, M48Z128Y

Table 16. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090

Figure 15. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline

A1 A2
A A3

eA B L
eB
D

SHZP-A

Drawing is not to scale.

15/17
M48Z128, M48Z128Y

Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm inch
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

B 0.150 0.270 0.0059 0.0106
C 0.100 0.210 0.0039 0.0083
D 19.800 20.200 0.7795 0.7953
D1 18.300 18.500 0.7205 0.7283
e 0.500 – – 0.0197 – –
E 7.900 8.100 0.3110 0.3189
L 0.500 0.700 0.0197 0.0276
α 0° 5° 0° 5°

CP 0.100 0.0039
N 32 32

Figure 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L
Drawing is not to scale.

16/17
 M48Z128, M48Z128Y

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