EEDG 6306 - Application Specific Integrated Circuit Design

Midterm Project
EEDG 6306 - Application Specific Integrated Circuit Design

Erik Jonsson School of Engineering and Computer Science

Midterm Project Report

Submitted to
Dr. Dian Zhou

By
Harshit Sood (HXS190060)
Sai Vamshi Koya (SXK210033)
MSDAP:

Digital audio signal processing has become increasingly popular in multimedia systems, largely
thanks to the advent of general digital signal processor (DSP) chips and high-precision
oversampling A/D and D/A converts. For portable and home entertainment audio systems,
however, the general-DSP-chip-based solution might be too costly and consume too much power,
at least in near years. Then a low-cost and lowpower solution for this purpose should be sought.
By carefully examining digital audio processing applications, we believe there is a possibility to
develop a tiny digital audio processor chip that is capable of performing several basic audio
processing functions with much improved performance/(cost.power) ratios over a general DSP
chip. The fundamental function for this mini stereo digital audio processor (MSDAP) in our mind
is a programmable finite impulse response (FIR) digital filter that has various audio applications
[1, 2]. The performance of the MSDAP is expected to be the same level as that of two general DSP
chips for implementing two-channel FIR digital filtering in audio applications. Its cost might be
reduced by a factor of five to ten, compared to a general DSP chip and, of course, depending on
the production volume. Power dissipation of the MSDAP chip will fall on the level of 100 mW so
that it can also be used in portable systems. (A general DSP chip usually consumes five to ten
times more power using the same IC technology and having comparable performance.)

MSDAP Algorithm:
The FIR digital filtering involves the following linear convolution. ], the MSDAP will focus on
the FIR digital filtering – a fundamental and computation-intensive task

y(n) = h(k )  x(n − k )

where x(n) and y(n) are input and output audio sequences, and h(k) are filter coefficients
with the filter order N. (where N here is 512).
Using this algorithm eliminates the use of a barrel shifter. A barrel shifter is a digital circuit that
can shift a data word by a specified number of bits. Implementing convolution in the
straightforward way would need shifting by different number of bits each time and hence would
require a barrel shifter. Barrel shifters are very hardware intensive and slow. The innovative
approach taken by this algorithm is the use of a single bit shift every time. This greatly reduces the
area and complexity of the designed chip.

Normally, for implementing any kind of the digital filter, a common approach would be to use the
linear convolution method. In this method the signal which needs to be filtered is convolved with
the filter coefficient. The figure below shows an abstract of general convolution approach.
 Figure 1: General convolution approach

For an instance, let’s take an example of filter coefficient as below.

ℎ(𝑘) = 2−3 − 2−7+2−16
Putting it into the equation of Y(n) above, after expanding the equation, it becomes as follows

ℎ(𝑘). 𝑥(𝑛 − 𝑘) = 2−3. 𝑥(𝑛 − 𝑘) − 2−7. 𝑥(𝑛 − 𝑘)+2−16. 𝑥(𝑛 – 𝑘)

The above equation shows that it will use only three shifts and three additions/subtraction
operations instead of using multiplier from DSP chip. One problem with this approach is that for a
4-bit filter coefficient function, the power-of-two (POT) digit can be 16 at max (i.e. 2-16). This
implies that we need a big 16-bit shifter. This type of shifter will need to be programmed to perform
dynamic shifting operation from 1-bit to 16-bits. This can increase the area requirement as well as
it will reduce the overall system performance. This might destroy the whole purpose of making
this design simpler. An excellent idea of using only one single bit shifter is proposed in the MSDAP
paper.

Processor Architecture:

The MSDAP focuses on computing the linear convolution. At time point n, suppose that N data
samples, x(n), x(n-1), …x(n-N+1), are stored in a data RAM. Then, the virtual addresses aj(l),
corresponding to xj(l) with 1 j ≤ l r ≤ and 1 16 ≤ ≤j, can be created based on the filter POT
coefficients when they are available. (The physical address of the data RAM is the sum of the
virtual address and a base address, and the base address is incremented when a new input sample
replaces the oldest sample in the data RAM.) It should also be mentioned that two auxiliary bits
will be attached to each aj(l). The first bit indicates whether +x(n-k) or –x(n-k) will be processed,
while the second determines one-bit shift operations. In summary, the MSDAP should have two
data RAMs with a total capacity of 2×256×16 bits. (We have assumed that two-channel audio
signals are sampled with 16-bit precision.) A program RAM consisting of aj(l), 1 j ≤ l r ≤ and 1 16
≤ ≤j , thus has a capacity of 512×10 bits: two bits of each word indicate the sign and shift
information and the rest eight bits represent a virtual address of xj(l).

Therefore, only about 1.8 kbytes data and program memory circuits will be required in our
MSDAP. (If only one program RAM is used, this implies that two FIR filters perform the identical
transfer functions.)
Based on the above analysis, the block diagram of the MSDAP is readily depicted in Fig. where
only two accumulators and two one-bit shifters are needed in addition to memories and control
circuitry. Let us now turn to the determination of the system clock rates. It is well known that three
industry standards exist concerning the sampling rates of digital audio signals: 48 kHz for studio
use, 44.1 KHz for CD players and 32 kHz likely for digital audio broadcasting. Thus, the highest
sampling rate, namely 48 kHz, requires that each output sample be processed within
1000/48=20.8μs. Taking 512 cycles needed for processing each output sample in the MSDAP into
account, the shortest cycle time then 20.8/512=40.7 ns. In other words, the highest clock rate of
the MSDAP will be 24.58 MHz. (22.58 MHz and 16.39 MHz are the system clock rates for
sampling rates 44.1 kHz and 32 kHz situations, respectively.)

Features :

• A system clock (Sclk) of 26.88MHzand a data clock (Dclk) of 768 KHz is used.
• 16-bit audio input bus and 1-bit wire to release 40-bit audio output.
• Supports dual channel serial inputs with the Dclk.
• Supports dual channel serial outputs with the Sclk.
• Automatic sleep mode when 800 consecutive zero inputs are obtained.
• Has Reset to refresh the data collection and computation.

Block Diagram:
 Figure 2: Interface and communication of MSDAP with controller

Pin Settings:

Sclk (Input)

System clock running at a frequency of 26.88MHz (you may modify this frequency)provides the
timing reference for the internal and control signals, as well as the output samples. Outputs InReady
and OutReady are updated on the rising edge of Sclk.

Dclk (Input)

Data clock running at a frequency of 768kHz (this frequency is fixed) provides thetiming reference
for the input samples.

Start (Input)
When Start is set low, the chip begins to initialize. Start may be asynchronous with Sclk or Dclk.

Reset_n (Input)

When Reset_n is set low, the chip begins to reset. Reset_n may be asynchronous with Sclk or
Dclk.

InReady (Output)

InReady is set high when the chip is ready to receive coefficients or input samples; otherwise it is
set low. InReady is updated on the rising edge of Sclk.
OutReady (Output)

OutReady is set high when the chip is transmitting output samples; otherwise it is set low.
OutReady is aligned with the rising edge of Frame.

InputL (Input)

InputL carries the left channel coefficients and audio samples in serial form. Bit 0 is the sign bit
and is transmitted first. Bit 15 is the LSB and is transmitted last. InputL is read on the falling edge
of Dclk.

InputR (Input)

InputR carries the right channel coefficients and audio samples in serial form. Bit 0is the sign bit
and is transmitted first. Bit 15 is the LSB and is transmitted last. InputR is read on the falling edge
of Dclk.

OutputL (Output)

OutputL carries the left channel serial output samples. Bit 0 is the sign bit and is transmitted first.
Bit 39 is the LSB and is transmitted last. OutputL is updated on the rising edge of Sclk. The output
frame starts with the rising edge of Frame andlasts for 40 Sclk cycles.

OutputR (Output)
OutputR carries the right channel serial output samples. Bit 0 is the sign bit and is transmitted first.
Bit 39 is the LSB and is transmitted last. OutputR is updated on the rising edge of Sclk. The output
frame starts with the rising edge of Frame andlasts for 40 Sclk cycles.

Frame (Input)
Frame aligns the serial coefficients, input and output samples. Frame is set high for one Dclk
cycle when the first bit of the input samples or coefficients is received, and then it is set low.
Flow of Operation:

Figure 3: State Diagram

Operation modes :
STATE 0 (Initialization)
Upon reception of start signal (low level), the system enters in state0 and clears Input, Rj and
Coefficient memories and resets all counters and necessary flags. The clearing operation is
performed in parallel and system enters into state1 after all memories are clear.

STATE 1 (Waiting to receive Rj)

In state1, InReady signal goes high to indicate that the system is ready to receive Rj data and waits
for the Frame signal from the controller. As soon as Frame signal goes high, the system changes its
state to state2.

STATE 2 (Reading Rj)

In state2, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every rising edge of the data clock cycle and stores them into Rj register. As the
input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits for 15
idle Dclk cycles to maintain synchronization of the chip. This is repeated 16 times before
incrementing the pointer to accept next input on next Frame signal. Once all 16 Rj inputs are
received on left and right channels, the system enters in state3.
STATE 3 (Waiting to receive coefficients)
In state3, InReady signal goes high (if it is low) to indicate that the system is ready to receive
coefficient data and waits for the Frame signal from the controller. As soon as Frame signal goes
high, the system changes its state to state4.

STATE 4 (Reading Coefficients)

In state4, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every rising edge of the data clock cycle and stores them into coefficient register.
As the input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits
for 15 idle Dclk cycles to maintain synchronization of the chip. Once all 512 coefficient inputs are
received on left and right channels, the system enters in state5.

STATE 5 (Waiting to receive data)

In state5, InReady signal goes high (if it is low) to indicate that the system is ready to receive input
data and waits for the Frame signal from the controller. As soon as Frame signal goes high, the
system changes its state to state6.

STATE 6 (Working)
In state6, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every falling edge of the data clock cycle and stores them into Input register. As
the input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits for 15
idle Dclk cycles before incrementing the pointer to accept next input on next Frame signal. While
accepting the Inputs, the system also starts computation on the previously accepted input and if any
output is ready to be sent, the OutReady signal is set high and the output which was computed while
receiving the previous input is sent.

STATE 7(Clearing)
State7 is reset state, the system enters into this state on reception of a low signal on Reset pin
regardless of the clock. In this state, the system suspends every operation what it was doing before
coming to this state. The system disregards all the previously accepted inputs except Rj and
coefficient data.
The system exits this state upon reception of a High signal on Reset pin and enters in state5 to
initialize itself to accept input data as if it is accepting it for the first time.

STATE 8(Sleeping)
The system enters into this state when 800 consecutive inputs are received on both left and right
channel. In this state, InReady signal is held high and new inputs are continued to be accepted but
not stored until a non-zero input is encountered on either channel. As soon as a non-zero input is
detected, the system enters into state6 and accepts current input complete.
Frequency:

We have taken Sclk, Dclk, Start, Reset_n, Frame and Input as inputs and InReady, OutReady and
Output as outputs. We have taken Sclk frequency as 26.88 MHz and Dclk frequency as 768KHz.

Input-Output data formats

There are 3 kinds of input to the system of different bit widths. But when accepting them, all are accepted as
16-bit inputs. The frame format of each input data are discussed below.
1.1. Format of rj data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused/ 0 Padded bits MSB Rj data LSB
Figure 4: Format of rj data

Figure 4 shows the format of the rj data frame. The value given by LSB 8 bit represents the number of
coefficients to be selected from the coefficient memory.
1.2. Format of coefficientdata
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Unused/ 0 Padded bits Sign bit MSB Coefficient data LSB
Figure 5: Format of the coefficient data

Figure 5 shows the format of the coefficient data. The idea was to separate the sign bit from address bits. The
sign bit is 9th bit (bit 8) and if it is one then it means that the digit created by LSB 8 bits is negative. The LSB
8-bits represents K value.
1.3. Format of the input data
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB data LSB
Figure 6: Format of the input data

Figure 6 shows the format of the input data frame. Input data is 16 bit hence all bits in the frame are relevant.

1.4. Output Samples :

39 38 37 36 35 34 …. …. …. …. …. 4 3 2 1 0
MSB(sign LSB
bit)
Figure 7: Format of the input data

Figure 7 shows the format of the output data frame. Output data is 40-bit hence all bits in the frame are relevant.
Waveforms:

State 0 -> 1 -> 2

State 2 -> 3 -> 4

State 4 -> 5 -> 6

State 6 -> 8 -> 6

State 6 -> 7 -> 5 -> 6

State 8 -> 6 -> 7 -> 5 -> 6

Complete Waveform

Input data transition format: Parallel

Output data transition format: Serial

Asynchronized Reset