EEDG 6306 - Application Specific Integrated Circuit Design

Midterm Project
EEDG 6306 - Application Specific Integrated Circuit Design

Erik Jonsson School of Engineering and Computer Science

MSDAP Specification
Submitted to
Dr. Dian Zhou

By
Harshit Sood (HXS190060)
Sai Vamshi Koya (SXK210033)
MSDAP Algorithm:

1.1.a. MSDAP Algorithm example:

𝑛
𝑦(𝑛) = ∑𝑘=0 𝑥(𝑛 − 𝑘). ℎ(𝑘)
Let,
ℎ(0) = 2−1 − 2−2 − 2−3
ℎ(1) = 2−3 + 2−2 − 2−1
ℎ(2) = 2−1 + 2−3 + 2−2
This means,
𝑦(𝑛) = (2−1 − 2−2 − 2−3 ). 𝑥(𝑛 − 0) + (2−3 + 2−2 − 2−1 ). 𝑥(𝑛 − 1) + (2−1 + 2−3
+ 2−2 ). 𝑥(𝑛 − 2)
𝑦(𝑛) = 2−1 . [𝑥(𝑛 − 0) − 𝑥(𝑛 − 1) + 𝑥(𝑛 − 2)]
+ 2−2 . [−𝑥(𝑛 − 0) + 𝑥(𝑛 − 1) + 𝑥(𝑛 − 2)] + 2−3 . [𝑥(𝑛 − 0) − 𝑥(𝑛 − 1)
− 𝑥(𝑛 − 2)]
Let,
𝑢2 = [𝑥(𝑛 − 0) − 𝑥(𝑛 − 1) + 𝑥(𝑛 − 2)]
𝑢1 = [−𝑥(𝑛 − 0) + 𝑥(𝑛 − 1) + 𝑥(𝑛 − 2)]
𝑢0 = [𝑥(𝑛 − 0) − 𝑥(𝑛 − 1) − 𝑥(𝑛 − 2)]
Therefore,
𝑦(𝑛) = 2−1 . 𝑢2 + 2−2 . 𝑢1 + 2−3 . 𝑢0
𝑦(𝑛) = 2−1 . (𝑢0 + 2−1 . (𝑢1 + 2−1 . (𝑢2)))

1.1.b. MSDAP Algorithm:

• We wait for start to get low and move to state 0 where we initialize all necessary flags and
counters. Post initialization, we enter state 1 from state 0.
• Here we wait for frame to get high so that we can receive Rj inputs in state 2.
• After all Rjs are collected, we sum all the Rj values to understand how many coefficients we
can expect to capture in state 4.
• Accordingly, we enter state 3 to receive a frame high and start accepting coefficients in state
4.
• In state 5 we wait for a frame to go high and start receiving computing the input data in state
6.
• We collect collect 16-bit input_L and input_R in parallel from testbench.
o Each input for Rj, Coefficients, and Data_in is collected one per Dclock cycle and then
held for 16 cycles.
• The information is then stored in temporary registers.
• Meanwhile, 16-bit data_in is extended to 24-bit signed data. Further 16-bits are added as
padding to support 16 times bit shifts (as number of Rj is 16). Therefore, each data_in is now
a 40-bit data_in signed input.
• New input data is then added to the first index of the shift register.
• The variable a (for input_L) and c (for input_R) controls the loop for Rjs (dependent on total
Rj size)
• The variable b (for input_L) and d (for input_R) controls the loop for each coefficient under
on-going Rj (dependent on Rj value)
• At each clock cycle, these variables work on if conditions
o if (k < rj_size)
o if (l < rj_temp[k])
• After the inner most loop (loop for l) completes i.e. l = rj_temp[k]
o L is reset
o K is incremented (to access next Rj)
o U calculated is arithmetic bit shifted by 1.
• After the loop for k completes i.e. k = rj_size
o Final U calculated is sent out to temporary output register
o Coefficient index is reset (index used to capture coefficient values for R1..R16)
o K is reset (to restart loop for Rj)
• The processed data is now serially sent out in 40 sclk cycles.
• Inside the loop for coefficients, the logic is split in 2 conditions, whether we are calculating
for R0 or for R0+
o If R0
▪ Real 8-bit coefficient is extracted from original 9-bit signed coefficient.
▪ The index for x is calculated using statement: index = coeff_real (value of the
coefficient).
▪ e check for the sign bit of the coefficient we are working with.
• If sign bit is 1: u = u + (~padded_data_in [index] + 1'b1); // 2's
complement and u value update
• If sign bit is 0: u = u + padded_data_in [index]; // u value update
o If R0+
▪ The coefficient index is calculated: coeff_index = coeff_index + rj_temp[k-1]
• This is done so that the coefficient index position can shifted as per the
Rj value.
▪ After this, just like R0 real coefficient and index is calculated and according to
sign bit u value is calculated and updated.
• The 256 sized 40-bit data padded register shifts the existing values by 1 register and adds a
new input to the first index.
• When 800 inputs from both input_L and input_R together are detected, we enter into sleep
mode while keeping outready = 0 and inready = 1. This lets us still capture new inputs while
in sleeping mode and monitor if either input receives a non-zero value. As soon as that is
received, we enter in to Working Mode (state 6) and process that input and release the output.
• In state 5, state 6, or state 8, we have a low level reset_n trigger. Once that is detected, we go
to reset (state 7) and clean all data registers and computation processing registers and output
registers. Once all registers are cleared, we go to state 5 to start accepting new inputs.
Pin Settings MSDAP:
Pin Label IO Function
Sclk Input System Clock (26.88 MHz)
Dclk Input Data Clock (768 KHz)
Start Input Low Level Trigger to start the chip
Reset_n Input Low Level Trigger to Reset the chip
1 Dclk/Sclk pulse to intimate the input
Frame Input
or release of data
Input_L Input 16-bit Bus Input
Input_R Input 16-bit Bus Input
InReady Output Flag to inform input is being read
OutReady Output Flag to inform output is being released
Output_L Output 1-bit Output
Output_R Output 1-bit Output

MSDAP Operation Modes:

Figure 8: State Diagram

State0:
Upon reception of start signal (low level), the system enters in state0 and clears Input, Rj and
Coefficient memories and resets all counters and necessary flags. The clearing operation is
performed in parallel and system enters into state1 after all memories are clear.
State1:
In state1, InReady signal goes high to indicate that the system is ready to receive Rj data and waits
for the Frame signal from the controller. As soon as Frame signal goes high, the system changes
its state to state2.
State2:
In state2, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every rising edge of the data clock cycle and stores them into Rj register. As the
input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits for 15
idle Dclk cycles to maintain synchronization of the chip. This is repeated 16 times before
incrementing the pointer to accept next input on next Frame signal. Once all 16 Rj inputs are
received on left and right channels, the system enters in state3.
State3:
In state3, InReady signal goes high (if it is low) to indicate that the system is ready to receive
coefficient data and waits for the Frame signal from the controller. As soon as Frame signal goes
high, the system changes its state to state4.
State4:
In state4, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every rising edge of the data clock cycle and stores them into coefficient register.
As the input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits
for 15 idle Dclk cycles to maintain synchronization of the chip. Once all 512 coefficient inputs
are received on left and right channels, the system enters in state5.
State5:
In state5, InReady signal goes high (if it is low) to indicate that the system is ready to receive
input data and waits for the Frame signal from the controller. As soon as Frame signal goes high,
the system changes its state to state6.
State6:
In state6, Inready signal is held high and the system starts accepting the incoming bits on left and
right channel on every falling edge of the data clock cycle and stores them into Input register. As
the input data is of 16 bits, this input is captured in 1 Dclk by 16-bit input bus and then waits for
15 idle Dclk cycles before incrementing the pointer to accept next input on next Frame signal.
While accepting the Inputs, the system also starts computation on the previously accepted input
and if any output is ready to be sent, the OutReady signal is set high and the output which was
computed while receiving the previous input is sent.
State7:
State7 is reset state, the system enters into this state on reception of a low signal on Reset pin
regardless of the clock. In this state, the system suspends every operation what it was doing before
coming to this state. The system disregards all the previously accepted inputs except Rj and
coefficient data.
The system exits this state upon reception of a High signal on Reset pin and enters in state5 to
initialize itself to accept input data as if it is accepting it for the first time.
State8:
The system enters into this state when 800 consecutive inputs are received on both left and right
channel. In this state, InReady signal is held high and new inputs are continued to be accepted but
not stored until a non-zero input is encountered on either channel. As soon as a non-zero input is
detected, the system enters into state6 and accepts current input complete.

MSDAP IO Signal Formats:

We have been assigned a Parallel-In-Serial-Out IO Signal Format.
This means, we have a 16-bit bus for the 16-bit input and 1-bit pin for the 40-bit output.

MSDAP SCLK Frequency Calculation:

The DCLK frequency is fixed to be 768KHz (1302.07 ns period).
The time between 2 consecutive inputs received is 16 DCLK cycles (1302.07 * 16 ns = 20833.12 ns).
Therefore, we need a SCLK with high enough frequency to sample 512 coefficients in 20.83312 us.
This also means each coefficient gets (20833.12 / 512 = ~ 40.689 ns) to be completely computed.
But, in order to make our system run faster, we need SCLK with a high frequency and it needs to be synchronous with the
DCLK in other to avoid cases of frequency mismatch.
Therefore, the SCLK frequency to be synchronous with DCLK, we choose SCLK to be 26.88 MHz. This 35 times the
DCLK frequency and through our implementation proves that it can easily compute all coefficients in time.