DSP SHARC Processors PART1
DSP SHARC Processors PART1
DSP SHARC Processors PART1
PROCESSORS
This chapter briefly describes the SHARC processor’s architecture and key
features and compares available models.
Topics include:
• “What are SHARC Processors?” on page 1-1
• “Three Generations of SHARC Processors” on page 1-5
What are SHARC Processors?
SHARC is the name of a family of high-performance 32-bit floating-point
processors based on a Super Harvard Architecture. SHARC processors
dominate the floating-point digital signal processing market, delivering
exceptional core and memory performance complemented by outstanding
I/O throughput. The industry standard SHARC family makes floating-
point processing economical for applications where performance and
dynamic range are key considerations such as home, professional, and
automotive audio, medical, and industrial and instrumentation products.
The SHARC processor portfolio currently consists of three generations of
products providing code-compatible solutions, ranging from entry-level
products priced at less than $10 to the highest performance products
offering fixed- and floating-point computational power to 400 MHz/2400
MFLOPs. Regardless of the specific product choice, all SHARC processors
provide a common set of features and functionality usable across many
signal processing markets and applications. This baseline functionality
enables the SHARC user to leverage legacy code and design experience,
while transitioning to higher-performance, more highly integrated
SHARC products.
By integrating on-chip, single-instruction, multiple-data (SIMD) processing
elements, SDRAM, and I/O peripherals, SHARC processors deliver
breakthrough signal processing performance.
SHARC Applications
The combination of a high performance core surrounded by appropriate
peripherals, a large software library, and award-winning development tools
makes SHARC processors the ideal choice for audio and broad market
processor applications. Here are some applications:
• Home theater/digital home applications. The ADSP-21266,
ADSP-21365/6, and ADSP-21367 processors permit highly efficient
software implementations of audio decode and post processing
algorithms, such as Dolby Digital, Dolby Digital EX, DTS-ES Discrete
6.1, DTS-ESMatrix 6.1, DTS 96/24™ 5.1, MPEG-2 AAC
LC, MPEG-2 BC 2ch, Dolby Pro Logic II, Dolby Pro Logic 2x,
DTS Neo:6, and WMA Pro. Libraries of all standard–and many
proprietary–audio algorithms reside in on-chip ROM, eliminating
the need for external ROM.
• Professional audio applications. A number of the third-generation
SHARC processors are well-suited for professional audio applications
requiring high processing power and advanced on-chip
peripherals such as sample rate conversion, S/PDIF transmitter/
receiver, and BGA and LQFP package options.
• Automotive audio applications. The ADSP-2136x, with integration
of sample-rate conversion, DTCP cipher, precision clock
generators, and serial ports, is an ideal choice for new multichannel
automotive audio designs.
• Broad market use. SHARC processors are available in commercial,
industrial, and automotive temperature grade packages. They are
used in a wide variety of signal processing applications, providing
up to 400 MHz performance in a single instruction, multiple data
architecture (SIMD). Applications include imaging, medical
devices, communications, military, test equipment, 3-D graphics,
speech recognition, and motor control.
Architecture Overview
This section describes architectural features of the SHARC processor.
Super Harvard Architecture
The 32-bit floating-point SHARC processors from Analog Devices are
based on a Super Harvard architecture that balances exceptional core
and
memory performance with outstanding I/O throughput capabilities.
This
architecture extends the original concepts of separate program and
data
memory busses by adding an I/O processor with its associated
dedicated
busses.
In addition to satisfying the demands of the most computationally
intensive,
real-time signal processing applications, SHARC processors integrate
large memory arrays and application-specific peripherals designed to
simplify
product development and reduce time to market.
Performance
Real-time signal processing tasks are I/O and computationally
intensive.
In addition to high-speed math units and single-cycle instruction
execution
(including single-cycle multiply accumulates [MACs]), SHARC
processors are designed for maximum I/O and memory access
bandwidth.
This balance of core speed, memory integration, and I/O bandwidth
achieves the sustained performance critical to real-time applications.
ADSP-21262 EZ-KIT Lite Evaluation System
Processor Core
The processor core consists of two processing elements (each with
three
computation units and data register file), a program sequencer, two
DAGs, a timer, and an instruction cache. All processing occurs in the
processor
core.
Processing Elements
The processor core contains two processing elements: PEx and PEy.
Each