ARM Cortex-M3/M4 Processor Core Features

ARM Cortex-M3/M4 Processor
Core Features
ARM Cortex™-M3 processor
• The first of the Cortex generation of
processors released by ARM in 2006, was
primarily designed to target the 32-bit
microcontroller market.
• It provides excellent performance at low gate

count and comes with many new features
previously available only in high-end
processors.
Offerings of ARM Cortex-M3
• Greater performance efficiency
• Low power consumption
• Enhanced determinism
• Improved code density
• Ease of use
• Lower cost solutions
• Wide choice of development tools
The Cortex-M3 Processor versus
Cortex-M3-Based MCUs
Background of ARM and ARM
Architecture
• Formed in 1990 as Advanced RISC Machines Ltd., a joint venture of Apple
Computer, Acorn Computer Group, and VLSI Technology.
• In 1991, ARM introduced the ARM6 processor family, and VLSI became the
initial licensee.
• Subsequently, additional companies, including Texas Instruments, NEC, Sharp,
and ST Microelectronics, licensed the ARM processor designs, extending the
applications of ARM processors into mobile phones, computer hard disks,
personal digital assistants (PDAs), home entertainment systems, and many
other consumer products.
• These partners create their processors, microcontrollers, and system-on-chip
solutions. This business model is commonly called intellectual property (IP)
licensing.
• In addition to processor designs, ARM also licenses systems-level IP and
various software IPs.
• To support these products, ARM has developed a strong base of development
tools, hardware, and Software are products to enable partners to develop
their own products.
ARM Architecture Versions
Architecture V 7
• A Profile (ARMv7-A):
– Application processors which are designed to handle
complex applications such as high-end embedded
operating systems (OSs) (e.g., Symbian, Linux, and
Windows Embedded).
– These processors requiring the highest processing
power, virtual memory system support with memory
management units (MMUs), and, optionally,
enhanced Java support and a secure program
execution environment.
– Example products include high-end mobile phones
and electronic wallets for financial transactions
Architecture V 7 (contd..)
• R Profile (ARMv7-R):
– Real-time, high-performance processors targeted
primarily at the higher end of the real-time market
– Those applications, such as high-end breaking
systems and hard drive controllers, in which high
processing power and high reliability are essential
and for which low latency is important.
Architecture V 7 (contd..)
• M Profile (ARMv7-M):
– Processors targeting low-cost applications in
which processing efficiency is important and cost,
power consumption, low interrupt latency, and
ease of use are critical, as well as industrial control
applications, including real-time control systems.
Tiva™ TM4C123G Microcontroller
Tiva™ EK-TM4C123GXL LaunchPad
 ARM® Cortex™-M4F
64-pin 80MHz TM4C123GH6PM
 On-board USB ICDI
(In-Circuit Debug Interface)
 Micro AB USB port
 Device/ICDI power switch
 BoosterPack XL pinout also supports
legacy BoosterPack pinout
 2 user pushbuttons
(SW2 is connected to the WAKE pin)
 Reset button
 3 user LEDs (1 tri-color device)
 Current measurement test points
 16MHz Main Oscillator crystal
 32kHz Real Time Clock crystal
 3.3V regulator
 Support for multiple IDEs:
Instruction Set Enhancement
The Relationship between the Thumb Instruction Set in
Thumb-2 Technology and the Traditional Thumb
Cortex-M3 Processor Applications
• Low-cost microcontrollers
• Automotive
• Data communications
• Industrial control
• Consumer products
• To conclude...
– There are already many Cortex-M3 processor-based
products on the market, including low-end products
priced as low as US$1, making the cost of ARM
microcontrollers comparable to or lower than that of
many 8-bit microcontrollers.
A Simplified View of the Cortex-M3/M4
Nested Vectored Interrupt Controller
• Nested Interrupt Support
– The external interrupts and most of the system
exceptions can be programmed to different priority
levels
– If the priority of the new interrupt is higher than the
current level, the interrupt handler of the new
interrupt will override the current running task.
• Vectored Interrupt Support

– The starting address of the interrupt service routine
(ISR) is located from a vector table in memory.
– Hence, it takes less time to process the interrupt
request
Nested Vectored Interrupt Controller
(contd..)
• Dynamic Priority Changes Support
• Reduction of Interrupt Latency

– Automatic saving and restoring some register
contents, reducing delay in switching from one ISR to
another, and handling of late arrival interrupts
• Interrupt Masking
– Using interrupt masking registers BASEPRI, PRIMASK,
and FAULTMASK
Memory Map
• The Cortex-M3 has a predefined memory map.
• This allows the built-in peripherals, such as the
interrupt controller and the debug components,
to be accessed by simple memory access
instructions.
• Most system features are accessible in C program
code.
• Allows high optimization for speed and ease of
integration.
• The 4 GB memory space is divided into ranges..
Memory Map(Contd..)
The Bus Interface
• Several bus interfaces
• Code memory buses: to access code memory
region, two such buses – I-code and D-code
• System bus: to access memory and peripherals.
This provides access to the SRAM, peripherals,
external RAM, external devices, and part of the
system level memory regions.
• Private peripheral bus: provides access to a part
of the system-level memory dedicated to private
peripherals, such as debugging components
The MPU
• Optional
• Allows access rules to be set up for privileged
access and user program access
• When an access rule is violated, a fault exception
is generated, and the fault exception handler will
be able to analyze the problem and correct it, if
possible.
• MPU Usage:
– To protect data use by OS kernel and other privilege
processes
– to make memory regions read-only
Low Power and High Energy Efficiency
• Sleep mode and deep sleep mode supports
• Low gate count and design techniques reduce
circuit activities in the processor to allow active
power to be reduced
• It allows processing tasks to be completed in a
short time, so that the processor can return to
sleep modes as soon as possible to cut down
energy use
• Cortex-M3 revision 2, a new feature called
Wakeup Interrupt Controller (WIC) is available ->
suitable for many ultra-low power applications
Polling Method for Simple Applications
Polling Method with Multiple Devices
Simple Interrupt Driven Application
Application with both Polling and
Interrupt Driven
Application With RTOS
CMSIS
• The CMSIS was developed by ARM
– To allow users of the Cortex- M3/M4
microcontrollers to gain the most benefit from all
these software solutions
– To allow them to develop their embedded
application quickly and reliably
Standardized Access Interface for
Embedded Software Products
Organization of CMSIS
Using CMSIS
• For each MCU device, the MCU vendor provides a header file,
which pulls in additional header files required by the device
driver library, including the Core Peripheral Access Layer
defined by ARM
Accessing Memory-Mapped Registers in C
1. Accessing Peripheral Registers as Pointers.

2. Accessing Peripheral Registers as Pointers to
Elements in a Data Structure.
Accessing Peripheral Registers as Pointers
/* STM32F 100RBT6B e GPIO A Port Configuration Register Low */
#define GPIOA_CRL (*((volatile unsigned long *) (0x40010800)))
/* STM32F 100RBT6B e GPIO A Port Configuration Register High */
#define GPIOA_CRH (*((volatile unsigned long *) (0x40010804)))
/* STM32F 100RBT6B e GPIO A Port Input Data Register */
#define GPIOA_IDR (*((volatile unsigned long *) (0x40010808)))
/* STM32F 100RBT6B e GPIO A Port Output Data Register */
#define GPIOA_ODR (*((volatile unsigned long *) (0x4001080C)))
/* STM32F 100RBT6B e GPIO A Port Bit Set/Reset Register */
#define GPIOA_BSRR(*((volatile unsigned long *) (0x40010810)))
/* STM32F 100RBT6B e GPIO A Port Bit Reset Register */
#define GPIOA_BRR (*((volatile unsigned long *) (0x40010814)))
/* STM32F 100RBT6B e GPIO A Port Configuration Lock Register */
#define GPIOA_LCKR (*((volatile unsigned long *) (0x40010818)))
(contd..)
void GPIOA_reset(void) /* Reset GPIO A */

{
// Set all pins as analog input mode
GPIOA_CRL = 0; // Bit 0 to 7, all set as analog input
GPIOA_CRH = 0; // Bit 8 to 15, all set as analog input
GPIOA_ODR = 0; // Default output value is 0
return;
}
to Elements in a Data Structure
typedef struct #define PERIPH_BASE ((uint32_t)0x40000000)
{ /*!< Peripheral base address in the bit-band region */
.
__IO uint32_t CRL; #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
__IO uint32_t CRH; .
__IO uint32_t IDR; #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
__IO uint32_t ODR; #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
__IO uint32_t BSRR; #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
__IO uint32_t BRR; #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
.
__IO uint32_t LCKR; #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
} GPIO_TypeDef; #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
to Elements in a Data Structure (contd..)
void GPIO_reset(GPIO_TypeDef* GPIOx)
{
// Set all pins as analog input mode
GPIOx->CRL = 0; // Bit 0 to 7, all set as analog input
GPIOx->CRH = 0; // Bit 8 to 15, all set as analog input
GPIOx->ODR = 0; // Default output value is 0
return;
}
GPIO_reset(GPIOA); /* Reset GPIO A */

GPIO_reset(GPIOB); /* Reset GPIO B */
.

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ARM Cortex-M3/M4 Processor

• It provides excellent performance at low gate

• Vectored Interrupt Support

• Reduction of Interrupt Latency

1. Accessing Peripheral Registers as Pointers.

void GPIOA_reset(void) /* Reset GPIO A */

GPIO_reset(GPIOA); /* Reset GPIO A */

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