The ARM Cortex™-M3 processor

Edited by
VIDYA GOGATE
 The ARM Cortex™-M3 processor
• Greater performance efficiency: allowing more work to be done without increasing the frequency or power
requirements

• Low power consumption: enabling longer battery life, especially critical in portable products including wireless
networking applications

• Enhanced determinism: guaranteeing that critical tasks and interrupts are serviced as quickly as
possible and in a known number of cycles

• Improved code density: ensuring that code fits in even the smallest memory footprints

• Ease of use: providing easier programmability and debugging for the growing number of 8-bit and
16-bit users migrating to 32 bits

• Lower cost solutions: reducing 32-bit-based system costs close to those of legacy 8-bit and 16-bit
devices and enabling low-end, 32-bit microcontrollers to be priced at less than US$1 for the first time

• Wide choice of development tools: from low-cost or free compilers to full-featured development
suites from many development tool vendors.
 ATTRACTIVE FEATURES

• Non-maskable interrupts for critical tasks,

• Highly deterministic nested vector interrupts,
• Atomic bit manipulation,
• An optional Memory Protection Unit (MPU).
 Three profiles in the architecture version 7
: A,R,M
• A Profile (ARMv7-A): is designed for high-performance open application platforms.
Application processors which are designed to handle complex applications such as
high-end embedded operating systems (OSs) (e.g., Symbian, Linux, and Windows
Embedded). These processors requiring the highest processing power, virtual
memory system support with memory management units (MMUs), and,
optionally, enhanced Java support and a secure program execution Environment.
Example products include high-end mobile phones and electronic wallets for
financial transactions.
• R Profile (ARMv7-R): designed for high-end embedded systems in which real-time
performance is needed. Real-time, high-performance processors targeted primarily
at the higher end of the real-time1 market—those applications, such as high-end
breaking systems and hard drive controllers, in which high processing power and
high reliability are essential and for which low latency is important.
• M Profile (ARMv7-M): is designed for deeply embedded microcontroller-type
systems. Processors targeting low-cost applications in which processing efficiency
is important and cost, power consumption, low interrupt latency, and ease of use
are critical, as well as industrial control applications, including real-time control
systems.
The ARMv7-M architecture
• contains the following key areas:
• Programmer’s model
• Instruction set
• Memory model
• Debug architecture
 Cortex-M3 Processor Applications
With its high performance and high code density and small silicon footprint, the Cortex-M3 processor is
ideal for a wide variety of applications:

• Low-cost microcontrollers: The Cortex-M3 processor is ideally suited for low-cost microcontrollers, which
are commonly used in consumer products, from toys to electrical appliances.

• Automotive: The Cortex-M3 processor has very high-performance efficiency and low interrupt latency,
allowing it to be used in real-time systems. The Cortex-M3 processor supports up to 240 external
vectored interrupts, with a built-in interrupt controller with nested interrupt supports and an optional
MPU, making it ideal for highly integrated and cost-sensitive automotive applications.

• Data communications: The processor’s low power and high efficiency, coupled with instructions in
Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for many communications applications,
such as Bluetooth and ZigBee.

• Industrial control: In industrial control applications, simplicity, fast response, and reliability are key
factors. Again, the Cortex-M3 processor’s interrupt feature, low interrupt latency, and enhanced fault-
handling features make it a strong candidate in this area.

• Consumer products: In many consumer products, a high-performance microprocessor (or several of

them) is used. The Cortex-M3 processor, being a small processor, is highly efficient and low in power and
supports an MPU enabling complex software to execute while providing robust memory protection.
Architecture of Cortex-M3
 Architecture of Cortex-M3
• It has a 32-bit data path, a 32-bit register bank, and 32-bit memory
interfaces.

• The processor has a Harvard architecture, a separate instruction bus and

data bus.

• However, the instruction and data buses share the same memory space (a
unified memory system). In other words, you cannot get 8 GB of memory
space just because you have separate bus interfaces.

• The Cortex-M3 processor has an optional Memory Protection Unit (MPU),

and it is possible to use an external cache if it’s required.

• Both little endian and big endian memory systems are supported.
 Architecture of Cortex-M3
• The Cortex-M3 processor includes a number
of fixed internal debugging components such
as breakpoints and watch points.

• In addition, optional components provide

debugging features, such as instruction trace,
and various types of debugging interfaces.
Registers in the Cortex-M3.
 Registers
• The Cortex-M3 processor has registers R0 through R15. R13 (the stack
pointer) is banked, with only one copy of the R13 visible at a time.

• R0–R12: General-Purpose Registers

• R0–R12 are 32-bit general-purpose registers for data operations. Some 16-
bit Thumb® instructions can only access a subset of these registers (low
registers, R0–R7).

• R14: The Link Register

• When a subroutine is called, the return address is stored in the link register.

• R15: The Program Counter

• The program counter is the current program address. This register can be
written to control the Program flow.
 Stack Pointers
• R13: Stack Pointers
• The Cortex-M3 contains two stack pointers (R13). They are
banked so that only one is visible at a time.

• The two stack pointers are as follows:

• Main Stack Pointer (MSP): The default stack pointer, used by
the operating system (OS) kernel and exception handlers

• Process Stack Pointer (PSP): Used by user application code

The lowest 2 bits of the stack pointers are always 0, which
means they are always word aligned.
Special Registers in the Cortex-M3

Special Registers and Their Functions

 Special Registers
• Program Status registers (PSRs)

• Interrupt Mask registers (PRIMASK, FAULTMASK,

and BASEPRI)

• Control register (CONTROL)

• These registers have special functions and can be

accessed only by special instructions. They cannot
be used for normal data processing
 Operation Modes and Privilege Levels in
Cortex-M3.
• The Cortex-M3 processor has two modes and two privilege levels.

• The operation modes (thread mode and handler mode) determine

whether the processor is running a normal program or running an
exception handler like an interrupt handler or system exception handler.

• The privilege levels (privileged level and user level) provide a

mechanism for safeguarding memory accesses to critical regions as well
as providing a basic security model.

• When the processor is running a main program (thread mode), it can be

either in a privileged state or a user state, but exception handlers can
only be in a privileged state.
 Operation Modes and Privilege Levels in
Cortex-M3.
• The separation of privilege and user levels improves system
reliability by preventing system configuration registers from being
accessed or changed by some untrusted programs.

• If an MPU is available, it can be used in conjunction with privilege

levels to protect critical memory locations, such as programs and
data for OSs.

• For example, with privileged accesses, usually used by the OS kernel,

all memory locations can be accessed (unless prohibited by MPU
setup). When the OS launches a user application, it is likely to be
executed in the user access level to protect the system from failing
due to a crash of untrusted user programs.
Operation Modes and Privilege Levels in Cortex-M3.

Allowed Operation Mode Transitions.

 The Cortex-M3 Memory Map.
• A predefined memory map. This allows the built-in peripherals, such as the
interrupt controller and the debug components, to be accessed by simple
memory access instructions.

• Thus, most system features are accessible in C program code.

• The predefined memory map also allows the Cortex-M3 processor to be highly
optimized for speed and ease of integration in system-on-a-chip (SoC) designs.

• Overall, the 4 GB memory space can be divided into ranges as shown .

• The Cortex-M3 design has an internal bus infrastructure optimized for this
memory usage. In addition, the design allows these regions to be used
differently.

• For example, data memory can still be put into the CODE region, and program
code can be executed from an external Random Access Memory
(RAM) region.
The Cortex-M3 Memory Map.
 Program Status registers
• Application Program Status register (APSR)
• Interrupt Program Status register (IPSR)
• Execution Program Status register (EPSR)
• You can read the PSRs using the MRS instruction. You can
also change the APSR using the MSR instruction, but
EPSR and IPSR are read-only.
• For example:

• MRS r0, APSR ; Read Flag state into R0

• MRS r0, IPSR ; Read Exception/Interrupt state
• MRS r0, EPSR ; Read Execution state
• MSR APSR, r0 ; Write Flag state
Program Status Registers in the Cortex- M3.

Combined Program Status Registers (xPSR) in the Cortex-M3.

Bit Fields in Cortex-M3 Program Status Registers

Current Program Status Registers in Traditional ARM Processors.

 Interrupts and Exceptions
• There is no fast interrupt (FIQ) (fast interrupt in
ARM7/ARM9/ARM10/ARM11) in the Cortex-M3

• The interrupt features in the Cortex-M3 are

implemented in the NVIC- Nested Vectored Interrupt
Controller.

• That behaves just like the FIQ in traditional ARM

processors.

• The Cortex-M3 also supports a number of internal

exception sources, such as system fault handling.
Cortex-M3 Exception Types
 The Built -In Nested Vectored Interrupt
Controller (NVIC).
• It is closely coupled to the processor core and provides a
number of features as follows:
• Nested interrupt support
• Vectored interrupt support
• Dynamic priority changes support
• Reduction of interrupt latency
• Interrupt masking
 NVIC
• All the external interrupts and most of the system
exceptions can be programmed to different priority
levels.

• When an interrupt occurs, the NVIC compares the

priority of this interrupt to the current running priority
level.

• If the priority of the new interrupt is higher than the

current level, the interrupt handler of the new
interrupt will override the current running task.
 Vectored interrupt support

• When an interrupt is accepted, the starting

address of the interrupt service routine (ISR) is
located from a vector table in memory.

• There is no need to use software to determine

and branch to the starting address of the ISR.

• Thus, it takes less time to process the

interrupt request.
 Dynamic priority changes support
• Priority levels of interrupts can be changed by
software during run time.
•
• Interrupts that are being serviced are blocked
from further activation until the ISR is
completed, so their priority can be changed
without risk of accidental reentry.
 Reduction of interrupt latency

• The Cortex-M3 processor also includes a

number of advanced features to lower the
interrupt latency.

• These include automatic saving and restoring

some register contents, reducing delay in
switching from one ISR to another, and
handling of late arrival interrupts.
 Interrupt masking
• Interrupts and system exceptions can be masked
based on their priority level or

• Masked completely using the interrupt masking

registers BASEPRI, PRIMASK, and FAULTMASK.

• They can be used to ensure that time-critical tasks

can be finished on time without being interrupted.
 Other Cortex-M3 Features
• The SYSTICK Timer
• Power Management
• Sleep Modes