MP and MC 2015

PSNCET
MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL
PSN COLLEGE OF ENGINEERING AND TECHNOLOGY

Melathediyoor, Tirunelveli
(Approved by AICTE and Recognized by UGC Section 2 (f)
An ISO 9001:2008 Certified Institution
(Accredited by NBA and NAAC, Affiliated to Anna University of Technology,
Tirunelveli)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
MICROPROCESSOR
AND
MICROCONTROLLER
LABORATORY
MANUAL
Prepared by
T.Rajesh M.E.,(Ph.D) AP/ECE
K.Manikandan M.E., AP/ECE
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SYLLABUS
MICROPROCESSOR AND MICROCONTROLLER LABORATORY
LIST OF EXPERIMENTS
L T P C
0 0 3 2
Microprocessor (8085/8086):
1. Program for 8 bit Arithmetic operation using 8085/86
2. Program for 16 bit Arithmetic operation using 8085/86
3. Program for sorting and searching using 8085/86
4. Program for String manipulation operation using 8085/86
Microcontroller:
1. Programming using Arithmetic, Logical and bit manipulation instructions of 8051
2. Program for sorting and searching using 8051
3. Code conversion using 8051.
Interfacing:
1.
2.
3.
4.
5.
Analog to Digital/ Digital to Analog

Interfacing and programming of stepper motor control
Communication between 8051 Microcontroller and PC
Interfacing and programming 8279, 8259, 8255 and 8253.
Traffic Light Controller.
TOTAL : 45 PERIODS
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MICROPROCESSOR AND MICROCONTROLLER LABORATORY
Sl.No
Cycle I
1.
Program for 8 bit Arithmetic operation using 8085
2.
(a) Program for 16 bit Arithmetic operation using 8085
2.
(b) Program for 16 bit Arithmetic operation using 8086
3.
(a) Program for sorting and searching using 8085
3.
(b) Program for sorting and searching using 8086
4.
Program for String manipulation operation using 8086
5.
Programming using Arithmetic, Logical and bit manipulation instructions of
Page No.
8051
Cycle II
6.
Program for sorting and searching using 8051
7.
Code conversion using 8051.
8.
Analog to Digital/ Digital to Analog
9.
Interfacing and programming of stepper motor control
10. Communication between 8051 Microcontroller and PC

11. Interfacing and programming 8279, 8259, 8255 and 8253.
12. Traffic Light Controller.
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EXP. NO.
Date: _________
STUDY OF INTEL 8085 MICROPROCESSOR KIT
TITLE:
Aim: To study the working of Intel 8085 Microprocessor trainer kit.
Figure 1.1 Vimicros Micro-85 Microprocessor kit
1.1 INTRODUCTION
This section briefs the hardware and software facilities available in both the trainers
Micro-85 EBl and Micro-85 EB2. Micro-85 EBl is a powerful Microprocessor Trainer
with basic features such as 24 TTL lines using 8255, Hardware Single Stepping and
Software Single Stepping of user programs.
In addition to the above features, Micro-85 EB2 has RS232C compatible serial port,
Bus Expansion for interfacing VBMB series of add-on cards and 24 TTL I/O lines. A
separate switch is provided for learning more about hardware. interrupts. There is
also provision to add multi output power supply for interfacing experiment boards.
Most of the control signals are terminated .at test points for easy analysis on CRO or
logic probe.
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The differences in the specification of Micro-85 EBl and Micro-85 EB2 are highlighted
in this manual. The users are therefore requested to go through the Hardware
specification carefully.
1.2 SPECIFICATIONS
1.2.1 HARDWARE SPECIFICATIONS
1) PROCESSOR, CLOCK FREQUENCY: Intel 8085A at 6.144 MHz clock. .
2) MEMORY:
Monitor EPROM
: 0000 - 1FFF
EPROM- Expansion
: 2000 - 3FFF & COOO - FFFF
System RAM
: 4000 - 5FFF
Monitor Data Area
: 4000 - 40FF (Reserved)
User RAM Area
: 4100 - 5FFF
RAM- Expansion
: 6000 - BFFF
Note: The RAM area from 4000 - 40FF should not be accessed by the
user since it is used as scratch pad by the Monitor program.
3) INPUT/OUTPUT:
Parallel: 48 TTL :I/O lines using two number of 8255
(only 24 :I/O line. available in micro-85 EB1).
Serial
: One number of RS232C compatible Serial interface

using 8251A - USART.
Timer : Three channel 16-bit Programmable Timer using 8253.

- Channel 0 is used as baud rate clock generator for 8251A USART.
- Channel 1 is used for in single stepping user programs.
- Channel 2 is used for Hardware Single Stepping user programs.
4) DISPLAY:
- 6 digit, 0.3", 7 Segment Red LED Display with filter.
- 4 digits for address display and 2 digits for data display.
5) KEYBOARD :
- 21 Keys soft keyboard including command keys and hexa-decimal keys.
6) AUDIO CASSETTE INTERFACE with file management.
7) BATTERY BACKUP:
- Onboard Battery backup facility is provided for the available RAM.
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8) HARDWARE SINGLE STEP:

This facility allows the user to execute programs at machine cycle level
using a separate switch.
9) SYSTEM POWER CONSUMPTION:

Micro-85 EB2
Micro-85 EBl
+ 5 V @ 1 Amp
+ 12 V@ 200 mA
- 12 V @ l00 mA
+5V @ 500 mA
10) POWER SUPPLY SPECIFICATIONS: [External ]

Micro-85 EB2
Input:
230 V AC @ 50, Hz
Output: + 5 V @ 1.5 A
+ 12 V @ 150 mA
- 12 V @ 150 mA
+ 30 V @ 250 mA
(Unregulated)
Micro-85 EB1
230V AC @ 50 Hz
+ 5 V @ 600 mA
11) PHYSICAL CHARACTERISTICS:

Micro-85 EB
PCB
: 230mm x 170mm [L x B]
Weight
: 1 Kg.
12) TEST POINTS: Test points provided

for MR*, MW*, INTA*, IO/M*, IOR*, IOW*, S0, S1, INTA.
This enables the user to study the hardware timing easily.
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1.2.2 SOFTWARE SPECIFICATIONS

Micro-S5 EB contains a high performance 8K bytes monitor program. It is designed
to respond to user input, RS232C serial communications, tape interface etc. The
following is a simple description of the key functions. Out of the 21 keys in the
keyboard 16 are hexadecimal, command and register keys and the remaining are
stand-alone keys.
KEY
RES
FUNCTION SUMMARY
This RES key allows you to terminate any present activity and to return
your Micro-85 EB to an initialized state. When pressed, the ..85 signon message appears in the display for a few seconds and the monitor
will display command prompt - in the left most digit.
Maskable interrupt connected to CPU's RST 7.5 interrupt.
INT
DEC
EXEC
DEC
Decrement the address by one and display it contents

(or)
Display the previous register contents.
Execute a particular program after selecting the address

through GO command.
Increment address by one and display its contents

(or)
Display the next register content.
The 16 Hexa decimal keys have either a dual or a triple role to play.
i) It functions as a Hex key entry when a address or data entry is required.
ii) It functions as the Register key entry during Register command.
iii) It functions as command key when pressed directly after command prompt.
NOTE: The Hex-key function summary below is in the order:

i) Hex key.
ii) Command key
iii) Register key.
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KEY
FUNCTION SUMMARY
i.
0
E
SUB
Hex key entry "0"
ii. This key is for substituting memory contents When NEXT key is
pressed immediate1y after this it takes the user to the start
address for entering user programs, 4100 Hex (User RAM).
iii. Register key "E"
i. Hex key entry "1"

D
REG
ii. Examine the 8085A registers and modify the same.

iii. Register key "D"
i. Hex key entry "2"
C
TW
ii. Writes data from memory on to audiotape.
i.
B
TR
ii. Retrieve data from an audiotape to memory.
iii. Register key "C"
Hex key entry 3
iii. Register key B
Hex key entry 4.
i.
F
BLOC
ii. Block search for a byte.

iii. Register key F.
i.
Hex key entry 5.
A
FILL
ii. Fill a block of RAM memory with desired data.
i.
L
SER
ii. Transmit/Receive data to/from the serial port.
iii. Register key A.
Hex key entry "6"
The TW/TR keys are used for sending/receiving respectively.

iii. Register key L.
i.
H
F2
Hex key entry "7"
ii. Register key "H"
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8
I
GO
i.
Hex key entry "8"
ii. Start running a particular program

iii. Register key "I"
9
PL
SNG
i.
ii. Single step a program instruction by instruction.

iii. Register key PCL.
i
A
PH
F3
Hex key entry "9"
Hex key entry "A"
ii. Function key F3

F3 [0] = Input a byte from a port
P3 [1] = Output a byte to a port
iii. Register key PCH"
iv. Used with SNG key for hardware single stepping.
Hex key entry "B"
SL
BC
ii. Check a particular block for blank.

iii. Register key "SPL"
i.
Hex key entry "C"
SH
MOV
ii.
Move block of memory to another block
iii. Register key SPH
D
CMP
E
INS
i.
Hex key entry "D"
ii. Compare two memory blocks.
i.
Hex key entry "E"
ii. Insert bytes into memory (RAM) .
i. Hex key entry "F"
DEL
ii. Delete bytes from memory (RAM).
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EXP. NO.
TITLE:
Date: _________
STUDY OF INTEL 8086 MICROPROCESSOR
FEATURES:
1. 16-bit Data bus
2. Computes 16 bit / 32 bit data.
3. 20-bit address bus.
20
4. More memory addressing capability (2 = 1MB)
5. 16 bit Flag register with 9 Flags
6. Can be operated in Minimum mode and Maximum mode
7. Has two stage pipelined architecture
8. No internal clock generation
9. 40 pin DIP IC - HMOS technology
10. Operates on +5V supply voltage
11. Has more powerful instruction set
Memory:
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 1MB KB. As the most of the processor instructions use
16-bit pointers the processor can effectively address only 64 KB of memory. To
access memory outside of 64 KB the CPU uses special segment registers to specify
where the code, stack and data 64 KB segments are positioned within 1 MB of
memory (see the "Registers" section below).
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16-bit pointers and data are stored as:

address
: low-order byte
address+1
: high-order byte
32-bit addresses are stored in "segment:offset" format as:

address
: low-order byte of segment
address+1
: high-order byte of segment
address+2
: low-order byte of offset
address+3
: high-order byte of offset
Physical memory address pointed by SEGMENT:OFFSET pair is calculated as:

Physical address = (<Segment Addr> * 16) + <Offset Addr>
Program memory - program can be located anywhere in memory. Jump and

call instructions can be used for short jumps within currently selected 64 KB
code segment, as well as for far jumps anywhere within 1 MB of memory. All
conditional jump instructions can be used to jump within approximately +127 -127 bytes from current instruction.
Data
memory
the
processor
can
access
data
in
any
one
out
of
available segments, which limits the size of accessible memory to 256 KB (if
all
four segments point to different 64 KB blocks). Accessing data from the
Data, Code, Stack or Extra segments can be usually done by prefixing instructions
with the DS:, CS:, SS: or ES: (some registers and instructions by default may use
the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two
memory accesses to read 16-bit word located at odd byte boundaries. Reading
word data from even byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at
odd memory addresses, but it is not recommended for performance reasons (see
"Data Memory" above).
Reserved locations:
0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a
32-bit pointer in format SEGMENT:OFFSET.
FFFF0h - FFFFFh - after RESET the processor always starts program execution
at the FFFF0h address.
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Interrupts:
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled
using STI/CLI instructions or using more complicated method of updating the
FLAGS register with the help of the POPF instruction. When an interrupt occurs, the
processor stores FLAGS register into stack, disables further interrupts, fetches from
the bus one byte representing interrupt type, and jumps to interrupt processing
routine address of which is stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the
INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI
processing routine is stored in location 0008h. This interrupt has higher priority
then the maskable interrupt.
Software interrupts can be caused by:
INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256
interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1

interrupt. When the CPU processes this interrupt it clears TF flag before calling
the interrupt processing routine.
Processor exceptions: divide error (type 0), unused opcode (type 6) and
escape opcode (type 7).
Software interrupt processing is the same as for the hardware interrupts.
I/O ports:
8086 can interface maximum of 65536 nos of 8-bit I/O ports. These ports can be
also addressed as 32768 16-bit I/O ports.
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Registers:
Most of the registers contain data/instruction offsets within 64 KB memory
segment. There are four different 64 KB segments for instructions, stack, data and
extra data. To specify where in 1 MB of processor memory these 4 segments are
located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions.
The processor uses
CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot be

changed directly. The CS register is automatically updated during far jump, far call
and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the
stack pointer (SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data
segment. DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions. ES register can be
changed directly using POP and LES instructions.
It is possible to change default segments used by general and index registers by
prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and
logic operations. The general registers are:
Accumulator (AX) register consists of 2 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX. AL in this case contains the
low-order byte of the word, and AH contains the high-order byte. Accumulator can
be used for I/O operations and string manipulation.
Base (BX) register consists of 2 8-bit registers BL and BH, which can be combined
together and used as a 16-bit register BX. BL in this case contains the low-order
byte of the word, and BH contains the high-order byte. BX register usually contains
a data pointer used for based, based indexed or register indirect addressing.
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Count (CX) register consists of 2 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL register
contains the low-order byte of the word, and CH contains the high-order byte.
Count register can be used as a counter in string manipulation and shift/rotate
instructions.
Data (DX) register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the high-order byte. Data register can
be used as a port number in I/O operations. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting
number.
The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment.
BP register is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed
and register indirect addressing, as well as a source data address in string
manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based
indexed and register indirect addressing, as well as a destination data address
in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flag Register is a 16-bit register containing 9 nos of one bit flags:
Overflow Flag (OF) - set if the result is too large positive number, or is too
small negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will autodecrement index registers. If cleared then the index registers will be autoincremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
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Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3
in the AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of
the result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most
significant bit during last result calculation.
Instruction Set:
8086 instruction set consists of the following instructions:
Data moving instructions.
Arithmetic - add, subtract, increment, decrement, convert byte/word and

compare.
Logic - AND, OR, exclusive OR, shift/rotate and test.
String manipulation - load, store, move, compare and scan for byte/word.
Control transfer - conditional, unconditional, call subroutine and return from

subroutine.
Input/Output instructions.
Other - setting/clearing flag bits, stack operations, software interrupts, etc.
Addressing modes:
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is
located.
Register indirect - instruction specifies a register containing an address, where
data is located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base
register (BX or BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index
register (SI or DI), the resulting value is a pointer to location where data resides.
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Based Indexed - the contents of a base register (BX or BP) is added to the
contents of an index register (SI or DI), the resulting value is a pointer to location
where data resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added
to the contents of a base register (BX or BP) and index register (SI or DI), the
resulting value is a pointer to location where data resides.
Result:
The features of the Intel 8085 & 8086 microprocessors were studied and operations
of the corresponding kits were understood.
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Fig. Flow chart for 8-bit Addition with carry
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EXP. NO.
TITLE:
Date: _________
8-BIT ARITHMETIC OPERATIONS (8-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 8-bit numbers.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8085-microprocessor kit.
Power supply unit
THEORY:
The two operands (i.e., 8-bit numbers) are loaded into two registers A & B, using
immediate addressing mode instructions and then added using ADD instruction. The
result is stored in the desired memory location. The overflow in addition is checked
by verifying the status of Carry (Cy) flag and accordingly either 00 or 01 is stored
in the location next to the result.
ALGORITHM:
1. Start the program
2. Initialize the C register as 00H.
3. Move the data1 and data2 to Accumulator and B register respectively.
4. Add B register to the content of accumulator
5. If there is no carry, go to step 6, else increment C register.
6. Store the content of accumulator to the memory location 4500H.
7. Move the content of C register to accumulator.
8. Store the content of accumulator to the memory location 4501H.
9. Stop the program.
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PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
0E, 00
MVI C, 00
Clear c register
4102
3E, Data1
MVI A, Data1
Move data1 to
accumulator
4104
06, Data2
MVI B, Data2
Move data2 to B Register
4106
80
ADD B
Add B Reg to accumulator
4107
D2, 0B,41
JNC GO
Jump on No carry to
location GO
410A
0C
INR C
Increment C Register
410B
32,00,45
STA 4500
Store the result
410E
79
MOV A,C
Move carry to Acc
410F
32,01,45
STA 4501
Store the carry
4112
76
HLT
Stop the program
GO:
MANUAL CALCULATION:
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SAMPLE DATA:
Result of 8-bit addition without carry:

INPUT
Address
OUTPUT
Data
4103
05H
4105
06H
Address
4500
(Result)
4501
(Carry)
Data
0BH
00H
Result of 8-bit addition with carry:

INPUT
OUTPUT
Address
Data
4103
51H
4105
EBH
Address
4500
(Result)
4501
(Carry)
Data
3CH
01H
EXERCISE:
Execute the program with your own data and observe the results. Check the result
with your manual calculation.
INPUT
Address
4103
4105
OUTPUT
Data
Address
Data
4500
(Result)
4501
(Carry)
RESULT:
Thus the assembly language program for 8-bit addition is executed and the results
are verified.
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Fig. Flow chart for 8-bit subtraction
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EXP. NO.
TITLE:
Date: _________
8-BIT ARITHMETIC OPERATION (8-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 8-bit
numbers, using 8085.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
Out of the two operands for subtraction, the first operand is loaded into Accumulator
and the second operand is subtracted directly from memory, using register indirect
addressing mode instructions. The result is stored in desired memory location and
the borrow in subtraction is checked by verifying the status of Carry (Cy) flag and
accordingly either 00 or 01 is stored in the location next to result.
ALGORITHM:
1. Start the program.
2. Load the HL pair with 16-bit address of data location.
3. Move the content of memory address in HL to accumulator.
4. Increment the address in HL pair.
5. Subtract the content of memory from accumulator.
6. Jump on No-carry to step 8.
7. Increment the C-register.
8. Store the content of accumulator and C-register.
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PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
21, 50, 41
LXI H,4150
Load data to HL Register
4103
7E
MOV A, M
Move Data1 to Acc
4104
0E, 00
MVI C, 00
Clear C-register.
4106
23
INX H
Increment address.
4107
96
SUB M
Subtract Data2 from Acc
4108
D2, 0C, 41
JNC NEXT
Jump on No-carry
to the location NEXT.
410B
0C
INR C
Increment C register
410C
32, 52, 41
STA 4152
Store the result
410F
79
MOV A,C
Move carry to acc
4110
32, 53, 41
STA 4153
Store the carry
4113
76
HLT
Stop the program
NEXT:
MANUAL CALCULATION:
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SAMPLE DATA:
Result of 8 bit subtraction without carry:

INPUT
Address
OUTPUT
Data
4150
68H
4151
54H
Address
4152
(Result)
4153
(Borrow)
Data
14H
00H
Result of 8 bit subtraction with carry:

INPUT
OUTPUT
Address
Data
4150
57H
4151
66H
Address
4152
(Result)
4153
(Borrow)
Data
F1H
01H
EXERCISE:
INPUT
Address
OUTPUT
Data
4150
4151
Address
Data
4152
(Result)
4153
(Borrow)
RESULT:
Thus the assembly language program for 8-bit subtraction is executed and the
results are verified.
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Fig. Flow chart for 8-bit Multiplication
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EXP. NO.
TITLE:
Date: _________
8-BIT ARITHMETIC OPERATION (8-BIT MULTIPLICATION)
AIM: To write an assembly language program for the multiplication of two 8-bit
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
Using the immediate addressing mode instructions, the two operands to be multiplied
are loaded into two registers say, B and C. By the method of repeated addition, the
multiplication operation is performed (i.e., first number is repeatedly added to
accumulator as per the second number Eg. 03 x 04 => Acc + 03 (04 times) ). The
overflow in multiplication is checked every time after each addition, by verifying the
status of Carry (Cy) flag and accordingly a register, say D is incremented. The result
in accumulator is stored in the desired memory location and the content of D register
is stored in the location next to result.
ALGORITHM:
2. Clear the Accumulator and D Register.
3. Load the Data1 to B register and Data2 to C register.
4. Add the content of B to accumulator until C becomes zero.
5. If No-carry, go to step 6.
6. Increment the D-register.
7. Decrement the C register.
8. If C register is Non-zero, Jump to step 4.
9. Store the content of accumulator to 5000H.
10. Move the content of D-register to Accumulator.
11. Store the content of accumulator to 5001H.
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PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4500
3E, 00
MVI A,00
4502
06, Data1
MVI B, Data1
4504
0E, Data2
MVI C, Data2
4506
16,00
MVI D, 00
Clear D-reg for carry
4508
80
ADD B
repetitive addition
4509
D2, 0D, 45
JNC LOOP1
450C
14
INR D
450D
0D
450E
LOOP2:
LOOP1:
Move data to accumulator

Move multiplicand to b
register
Move the multiplier to c
register
Jump on no carry to an
location LOOP1
Increment the D-register,
if carry occurs.
DCR C
Decrement C-register
C2, 08,45
JNZ LOOP2
Jump on no zero to
Location LOOP2
4511
32,00,50
STA 5000
Store resultant product
4514
7A
MOV A,D
Move carry to
accumulator
4515
32,01,50
STA 5001
Store the carry.
4518
76
HLT
Stop the program.
MANUAL CALCULATION
Page 27
PSNCET
SAMPLE DATA:
Result of 8 bit multiplication without carry:

INPUT
Address
OUTPUT
Data
4503
05H
4505
05H
Address
5000
(Result)
5001
(Carry)
Data
19H
00H
Result of 8 bit multiplication with carry:

INPUT
Address
OUTPUT
Data
4503
41H
4505
25H
Address
5000
(Result)
5001
(Carry)
Data
45H
01H
EXERCISE:
INPUT
Address
OUTPUT
Data
4503
4505
Address
Data
5000
(Result)
5001
(Carry)
RESULT:
Thus the assembly language program for 8-bit multiplication is executed and the
Page 28
PSNCET
Fig. Flow chart for 8-bit Division
Page 29
PSNCET
EXP. NO.
TITLE:
Date: _________
8-BIT ARITHMETIC OPERATION (8-BIT DIVISION)
AIM: To write an assembly language program for the division of two 8 bit
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
Using the immediate addressing mode instructions, the Divisor and Dividend are
loaded directly into Accumulator and B register. By the method of successive
subtraction, the division is carried out (i.e., Divisor is repeatedly subtracted from
Dividend, until the dividend becomes smaller than divisor Eg. 09 / 02 => 09 02 (4
times) => Remainder=01 and Quotient=04). The C register is incremented every
time after each subtraction, to keep count of the quotient. The final content in
accumulator will be remainder of the division and it is stored in the desired memory
location and the content of C register containing the quotient is stored in the location
next to result.
ALGORITHM:
2. Clear C Register.
3. Load the Divisor to Accumulator.
4. Load the Dividend to B-register.
5. Compare the B-register value with the accumulator.
6. If Accumulator content is smaller to B reg., then Jump to step 10.
7. Subtract B-register value with accumulator.
8. Increment the C-register.
9. Jump to step 4.
10. Store the contents of accumulator and C-register into memory.
Page 30
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4500
3E, Divisor
MVI A, Divisor
Move Divisor to Acc
4502
06, Dividend
MVI B, Dividend
Move Dividend to B reg.
4504
0E, 00
MVI C, 00
Clear C register
4506
B8
CMP B
Compare Acc and B reg.
4507
DA, 0F, 45
JC LOOP1
450A
90
SUB B
450B
0C
INR C
Increment C register
450C
C3, 06,45
JMP LOOP2
Jump to location LOOP2
450F
32,00,50
STA 5000
Store the Remainder
4512
79
MOV A,C
Move C reg. to Acc
4513
32,01,50
STA 5001
Store the Quotient.
4516
76
HLT
Stop the program.
LOOP2:
LOOP1:
Jump on Carry
to location LOOP1
Repetitive subtraction
for division
MANUAL CALCULATION:
Page 31
PSNCET
SAMPLE DATA:
Result of 8-bit Division without remainder:
INPUT
OUTPUT
Address
Data
Address
Data
4501
06H
5000 (R)
00H
4503
03H
5001 (Q)
02H
Result of 8 bit division with remainder:

INPUT
OUTPUT
Address
Data
Address
Data
4501
25H
5000 (R)
02H
4503
05H
5001 (Q)
07H
EXERCISE:
INPUT
Address
OUTPUT
Data
Address
4501
5000 (R)
4503
5001 (Q)
Data
RESULT:
Thus the assembly language program for 8-bit division is executed and the results
are verified.
Page 32
PSNCET
Fig. Flow chart for 16-bit Addition
Page 33
PSNCET
EXP. NO.
TITLE:
Date: _________
16-BIT ARITHMETIC OPERATION (16-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 16-bit
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
Using the direct addressing mode instructions, the two 16-bit numbers are loaded
into HL and DE register pairs from memory. Using the double addition instruction
(DAD rp), the contents of HL and DE are added together and the results are stored in
the HL register pair again. The B register is used to check the overflow of the above
addition, by verifying the carry flag. The result in the HL register pair is stored in the
desired memory location and the content of B register is stored in the location next
to result.
ALGORITHM:
2. Clear the B-register.
3. Load the Data1 to HL register pair.
4. Exchange the content of HL to the DE register pair.
5. Load the Data2 to HL pair register.
6. Add the content of HL and DE pair.
7. If no overflow in addition (no carry), go to step 9.
8. Increment the content of B-register.
9. Store the content of HL pair to the address 5504H.
10. Store the content of B-register to the address 5506H.
Page 34
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4500
06,00
MVI B,00
Clear B register
4502
2A, 00,55
LHLD 5500
Load Data1 to HL register
4505
EB
XCHG
Shift the data in HL

to DE register
4506
2A, 02,55
LHLD 5502
Load the Data2 to HL pair
4509
19
DAD D
450A
D2, 0E, 45
JNC LOOP
450D
04
INR B
Increment the B register
450E
22,04,55
SHLD 5504
Store the result
4511
78
MOV A,B
Move carry to B register.
4512
32,06,55
STA 5506
Store the carry.
4515
76
HLT
Stop the program.
LOOP
Add the content of the HL

and DE pair
Jump on no carry to an
address
MANUAL CALCULATION:
Page 35
PSNCET
SAMPLE DATA:
Result of 16-bit Addition without carry:
INPUT
Address
OUTPUT
Data
5500, 01
7167H
5502, 03
8685H
Address
5504, 05
(Result)
5506
(Carry)
Data
F7ECH
00H
Result of 16-bit Addition with carry:

INPUT
OUTPUT
Address
Data
5500, 01
FF03H
5502, 03
EF03H
Address
5504, 05
(Result)
5506
(Carry)
Data
06FEH
01H
Exercise:
INPUT
Address
5500, 01
5502, 03
OUTPUT
Data
Address
Data
5504, 05
(Result)
5506
(Carry)
RESULT:
Thus the assembly language program for 16-bit addition is executed and the results
are verified.
Page 36
PSNCET
Fig. Flow chart for 16-bit Subtraction
Page 37
PSNCET
EXP. NO.
TITLE:
Date: _________
16-BIT ARITHMETIC OPERATION (16-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 16-bit
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
Using the direct addressing mode instructions, the two 16-bit numbers are loaded
into HL and DE register pairs. The lower bytes of the two numbers are subtracted
first using SUB instruction and the higher bytes of the same two numbers are
subtracted along with borrow using SBB instruction. The result in the accumulator
after each subtraction is stored in the two subsequent desired memory locations.
ALGORITHM:
3. Exchange the content of HL to the DE register pair.
5. Move the content of L register to Accumulator.
6. Subtract the content of E register from the Accumulator.
7. Store the result in accumulator to the memory location, 5100H.
8. Move the content of H register to Accumulator.
9. Subtract the content of D register from the Accumulator, along with borrow.
10. Store the result in Accumulator to the memory location, 5101H.
Page 38
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
Load the Data2 to HL
register.
Transfer the content
of HL to DE register pair.
Load the Data2
to HL pair register.
Move the content of L
register to accumulator
Subtract E register and
accumulator
4500
2A, 00,55
LHLD 5500
4503
EB
XCHG
4504
2A, 02,55
LHLD 5002
4507
7D
MOV A,L
4508
93
SUB E
4509
32,00,51
STA 5100
450C
7C
MOV A,H
450D
9A
SBB D
450E
32,01,51
STA 5101
Store the result.
4511
76
HLT
Stop the program.
Store the result

Move H register to
accumulator
Subtract D register and
accumulator
MANUAL CALCULATION:
Page 39
PSNCET
SAMPLE DATA:
Result of 16-bit Subtraction:
INPUT
Address
5500, 01
(Data2)
5502, 03
(Data1)
OUTPUT
Data
Address
Data
6677H
5100
(Result)
1111H
7788H
EXERCISE:
INPUT
Address
OUTPUT
Data
5500, 01
(Data2)
5502, 03
(Data1)
Address
Data
5100
(Result)
-
RESULT:
Thus the assembly language program for 16-bit subtraction is executed and the
Page 40
PSNCET
EXPT NO: 2(b)
Program for 16 bit Arithmetic operation using 8086
DATE:
AIM:
To perform basic 16 bit arithmetic operations in 8086 Microprocessor.
APPARATUS REQUIRED:
Sl.No.
Apparatus required
Quantity
8086 Microprocessor Kit
DC Power Supply 5V
ALGORITHM:
ADDITION:
1. Set SI register as pointer for data
2. Get the first data in AX register
3. Get the second data in BX register
4. Clear CL register
5. Get the sum in AX register
6. Store the sum in memory
7. Check for carry .If carry flag is set then go to next step,otherwise go to step-9
8. Increment CL register
9. Store the carry in memory
10. Stop
SUBTRACTION:
1. Set SI register as pointer for data
2. Get the minuend in AX register
3. Get the subtrahend in BX register
4. Clear CL register to account for sign
5. Subtract the content of BX from AX ,the difference will be in AX
6. Check for carry .If carry flag is set then go to next step,otherwise go to step 9
7. Increment CL retgister by one
8. Take 2s Complement of the difference in AX register(For this complement Ax and add one.
9. Store the magnitude of difference in memory
10. Store the sign bit in memory
11. Stop
Page 41
PSNCET
MULTIPLICATION:
1. Load the address of data in SI register
2. Get the first data in AX register
3. Get the second data in BX register
4. Multiply the content of AX and BX .The product will be in AX and DX
5. Save the product (AX and DX) in memory
6. Stop
DIVISION:
1. Load the address of data in SI register
2. Get the lower word of dividend in AX register
3. Get the upper word of dividend in DX register
4. Perform division to get quotient in AX and remainder in DX
5. Save the quotient (AX) and the remainder (DX) in memory
RESULT:
Thus the Basic 16 bit arithmetic operations have been performed successfully on 8086
microprocessor by Assembly Language Programming (ALP).
Page 42
PSNCET
Program: Add two 16-bit numbers with considering the carry.

Flow Chart
START
Load the address of data in SI register
Get the 1 st data in AX register
Get the 2nd data in BX register
Clear CL register
Get the sum (in AX register)
Store the sum in memory
YES
Is
CF=1?
NO
Increment CL register
Store carry (CL register) in memory
Stop
Page 43
PSNCET
Program
Address Label
Mnemonics
Opcode
Comments
8000
MOV SI,1100H
BE 81 00
Set SI register as
pointer for data
8003
MOV AX,[SI]
8B 04
Get the first data

in AX register
8005
MOV BX,[SI+2]
8B 5C 02
Get the second

data in BX
register
8008
MOV CL,00H
B1 00
Clear the CL
register for carry
800A
MOV AX,BX
03 C3
Add the two

data,sum will be
in AX register
800C
MOV [SI+4],AX
89 44 04
Store the sum in

memory
location(1104H)
800F
JNC AHEAD
73 02
Check the status

of carry flag
8011
INC CL
FE C1
If carry flag is
set,increment CL
b one
MOV [SI+6],CL
88 4C 06
Store carry in
memory location
(1106H)
INT 3
CC
8013
8016
AHEAD
Page 44
PSNCET
Program:Subtract two 16-bit numbers along with considering the borrow.

Flow Chart
START
Get the minuend in AX register
Get the subtrahend in BX register
Clear CL register
Subtract BX from AX
YES
Is
CF=1?
NO
Increment CL register by one
Store the difference in memory

Complement the content of AX
register
Store the sign bit

Add 01H to AX register
Stop
Page 45
PSNCET
Program:
Address Label
8000
Mnemonics
MOV SI,1100H
Opcode
BE 81 00
8003
MOV AX,[SI]
8B 04
8005
MOV BX,[SI+2]
8B 5C 02
8008
MOV CL,00H
B1 00
800A
SUB AX,BX
2B C3
800C
JNC STORE
73 07
800E
INC CL
FE C1
8010
NOT AX
F7 D0
8012
ADD AX,0001H
05 00 01
MOV[SI +4],AX
89 44 04
8018
MOV [SI+6],CL
88 4C 06
801B
INT 3
CC
8015
STORE
Comments
Load the address
of data in SI
register
Get the minuend
in AX register
Get the
subtrahend in BX
register
Clear the CL
register to
account for sign
Get the
difference in AX
register
Check the status
of carry flag
If carry flag is set
,increment by
one
Take 2s
complement of
the difference
Add 01H to AX
register
Store difference
in memory
location (1104H)
Store sign bit in
memory location
(1106H)
Page 46
PSNCET
Program:Multiply two 16-bit numbers.

Flow Chart
Start

Get the first data in AX register
Get the second data in BX register
Multiply the content of AX and BX
Save the lower word (AX) of product in memory
Save the upper word (DX) of product in memory
Stop
Program:
Address Label
8000
Mnemonics
MOV SI,1100H
Opcode
BE 81 00
8003
MOV AX,[SI]
8B 04
8005
MOV BX,[SI+2]
8B 5C 02
8008
800A
MUL BX
MOV[SI +4],AX
F7 E3
89 44 04
800D
MOV [SI+6],DX
89 54 06
8010
INT 3
CC
STORE
Comments
Load the address
of data in SI
register
Get the minuend
in AX register
Get the
subtrahend in BX
register
Store difference
in memory
location (1104H)
Store sign bit in
memory location
(1106H)
Page 47
PSNCET
Program:Division two 16-bit numbers.

Flow Chart
Start
Get the lower word of dividend in AX register
Get the upper word of dividend in DX register
Divide AX and DX with BX
Save the quotient (Ax) in memory
Save the remainder (DX) in memory
Stop
Program
Address
8000
Label
Mnemonics
MOV SI,1100H
Opcode
BE 81 00
Comments
Load the address of
data in SI register
8003
MOV AX,[SI]
8B 04
8005
MOV DX,[SI+2]
8B 54 02
Get the minuend in

AX register
Get the subtrahend in
BX register
8008
800B
MOVBX ,[SI +4]

DIV BX
8B 5C 04
F7 F3
800D
8010
MOV [SI+6],AX
MOV [SI+8],DX
89 44 06
89 54 08
8013
INT 3
CC
STORE
Store difference in
memory location
(1104H)
Store sign bit in
memory location
(1106H)
Page 48
PSNCET
Result:
Addition
Sample Data
Memory Address
8100
8101
8102
8103
Input Data: Data =F048H ----Output Data:Sum=009AH, Carry=01H

INPUT
OUTPUT
Content
Memory Address
Content
48
8104
9A
F0
8105
00
52
8106
01
10
Subtraction
Sample Data: Input Data:Minuend =840CH-----Output Data:Difference=2EBEH ,
INPUT
OUTPUT
Memory Address
Content
Memory Address
Content
8100
0C
1104
BE
8101
84
1105
2E
8102
CA
1106
01
8103
B2
Sign Bit =01H
Multiplication:
Sample Data: Input Data:Data 1=EF1AH----Output Data:BFC28A20H, Data 2 =CD50H
Memory Address
8100
8101
8102
8103
INPUT
Content
1A
EF
50
CD
OUTPUT
Memory Address
Content
8104
20
8105
8A
8106
C2
8107
BF
Division:
Sample Data: Input Data:Divident=71C2580AH,Divisor=F6F2H ,Output Data:Quotient=75EEH
Remainder=290EH
INPUT
OUTPUT
Memory Address
Content
Memory Address
Content
8100
0A
8106
EE
8101
58
8107
75
8102
C2
8103
71
8104
F2
8108
0E
8105
F6
8109
29
Page 49
PSNCET
Fig. 3.1a Flow chart for Sorting in Ascending order
Page 50
PSNCET
EXP. NO.
TITLE :
Date: _________
SORTING AND SEARCHING USING 8085 -
SORTING PROGRAM
AIM: To write an assembly language program for arrange an array of 8-bit numbers
in ascending and descending order, using 8085.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
This program uses the register indirect addressing mode instructions, to access the
data during sorting. The Bubble-Sort technique is used to sort the numbers in either
ascending order or descending order. The numbers to be sorted is stored in the
memory as a array with the first location containing the count of the data in the
array. The sorted numbers are stored back again in the same source location of the
array.
(I) ALGORITHM : ASENDING ORDER:

2. Load the data address to HL register pair and Initialize B register with 00
3. Move the array size count into C-register, then decrement the C-register
by 1 and increment HL register pair by 1.
4. Load the first data in the memory to Accumulator.
5. Compare the subsequent memory with Accumulator.
6. Jump on Carry, when M is greater A and go to Step 9.
7. Move the memory M to D register
8. Decrement the address of HL pair and move the D register content to M
and increment the value by HL by 1.
9. Move 01 to B register and decrement the C-register.
10. If C is Non-zero, Jump to comparison of next data.
11. If B becomes zero after decrement, go to step1.
Page 51
PSNCET
PROGRAM:
Address
Opcode &
Operand
4100
06,00
4102
Label
Comments
MVI B,00
Clear the counter
21,50,41
LXI H, 4150
Load Data addr to HL

pair.
4105
4E
MOV C,M
Move Array size to C-reg
4106
0D
DCR C
Decrement C reg
4107
23
INX H
Increment addr in HL
4108
7E
MOV A,M
Move data-I in HL to A
4109
23
INX H
410A
BE
CMP M
Compare data-II of
Memory (HL) with A
410B
DA, 15,41
JC LOOP1
Jump on cy to add
410E
56
MOV D,M
410F
77
MOV M,A
4110
2B
DCX H
4111
72
MOV M,D
23
INX H
4113
06,01
MVI B,01
Move data to B reg
4115
0D
DCR C
Decrement C reg
4116
C2, 08,41
JNZ LOOP2
Jump on no zero
4119
05
DCR B
Decrement B reg
411A
CA, 00,41
JZ AHEAD
Jump on zero to ahead
411D
76
HLT
Stop the program
4112
AHEAD:
Mnemonics
LOOP2:
LOOP1:
Move the data in HL to D

reg
Move content of acc to
HL.
Decrement address in HL
register.
Move content of D to M
reg
Increment address of HL
register
Page 52
PSNCET
SAMPLE DATA:
Result of the Sorting in Ascending Order

INPUT
Address
OUTPUT
Data
Address
Data
4150
(Array Size)
05H
4150
(Array Size)
05H
4151
78H
4151
25H
4152
A6H
4152
37H
4153
42H
4153
42H
4154
25H
4154
78H
4155
37H
4155
A6H
EXERCISE:
INPUT
Address
OUTPUT
Data
Address
4150
(Array Size)
4150
(Array Size)
4151
4151
4152
4152
4153
4153
4154
4154
4155
4155
4156
4156
4157
4157
Data
Page 53
PSNCET
Fig. Flow chart for Sorting in Descending order
Page 54
PSNCET
(II) ALGORITHM: DESENDING ORDER:

2. Load the data address to HL and initialize B register with 00
3. Move the Array size count into C-register then decrement the C-register by
1 and increment HL by 1.
4. Load the data-I in the memory to A.
5. Compare the subsequent memory content with A.
6. Jump on No-carry (when M is greater A), go to Step 9.
7. Move the memory M to D register
8. Decrement the value of HL pair and move the D register content to M and
increment the value by HL by 1.
9. Move B register and decrement the C-register.
10. Jump on Non-Zero to the next comparison. If zero, then decrement B and
go to step1.
Page 55
PSNCET
PROGRAM:
Address
Opcode &
Operand
4100
06, 00
4102
Label
Comments
MVI B,00
Clear the counter
21, 50, 41
LXI H,4150
Load Data addr to HL pair.
4105
4E
MOV C,M
Move Array size to C-reg
4106
0D
DCR C
Decrement C reg
4107
23
INX H
4108
7E
MOV A,M
Move data-I in HL to A
4109
23
INX H
410A
BE
CMP M
Compare data-II of Memory

(HL) with A
410B
D2, 15, 41
JNC LOOP1
Jump on No-Carry to Loop1
410E
56
MOV D,M
Move the data in M to D reg
410F
77
MOV M,A
Move content of A to M.
4110
2B
DCX H
Decrement address in HL reg.
4111
72
MOV M,D
Move content of D reg. to M
23
INX H
Increment Addr in HL reg
4113
06, 01
MVI B,01
Move data to B reg
4115
0D
DCR C
Decrement C reg
4116
C2, 08, 41
JNZ LOOP2
Jump on Non-zero to LOOP2
4119
05
DCR B
Decrement B reg
411A
CA, 00,41
JZ AHEAD
Jump on Zero to AHEAD
411D
76
HLT
Stop the program
4112
AHEAD:
Mnemonics
LOOP2:
LOOP1:
Page 56
PSNCET
SAMPLE DATA:
Result of the Sorting in Descending order:

INPUT
Address
OUTPUT
Data
Address
Data
4150
(Array Size)
05H
4150
(Array Size)
05H
4151
78H
4151
A6H
4152
A6H
4152
78H
4153
42H
4153
42H
4154
25H
4154
37H
4155
37H
4155
25H
EXERCISE:
INPUT
Address
OUTPUT
Data
Address
4150
(Array Size)
4150
(Array Size)
4151
4151
4152
4152
4153
4153
4154
4154
4155
4155
4156
4156
4157
4157
Data
RESULT:
Thus the assembly language program for sorting Ascending & Descending order is
executed and the results are verified.
Page 57
PSNCET
Fig. Flow Chart for Searching
Page 58
PSNCET
EXP. NO.
TITLE :
Date: __________
SEARCHING PROGRAM
AIM: To write an assembly language program to search the given data in an array.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
This program uses the register indirect addressing mode instructions, to access the
data for searching a number from the array stored in the memory. The numbers to
be searched is loaded into the Accumulator and compared with the numbers of the
given array. Here again, the array has the data count stored in its first location. At
the end of searching, this program provides the information about the number of
times the given number is found in the array. The result is stored in the desired
memory location.
ALGORITHM:
2. Load the data address to the HL register pair.
3. Load the data to be searched in Accumulator.
4. Load the data count of array in the C register.
5. Initialize the B register with 00.
6. Compare the memory content addressed by HL pair with Accumulator.
7. If not equal (zero flag is set); go to step 9.
8. Increment the B register.
9. Increment the HL register pair.
10. Decrement the C register by 1 and if not zero, go to step 6.
11. Store the content of B register in memory.
Page 59
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
3A, 50, 42
LDA 4250H
Load data to be searched

into Acc from memory
4103
21, 51, 42
LXI H, 4251H
Set pointer for data array
4106
06, 00
MVI B,00H
Clear B register
4108
4E
MOV C, M
Load data count to C reg.
4109
23
410A
BE
410B
C2, 0F, 41
410E
04
410F
0D
4110
C2, 09, 41
JNZ LOOP
If not zero,
go to location LOOP
4113
78
MOV A, B
Move the data from B to Acc
4114
32, 00, 42
STA 4200
Store the result
4117
76
LOOP:
INX H
Increment HL reg. pair
CMP M
Compare Acc & memory
JNZ NEXT
NEXT:
If Not equal, go to location

NEXT
INR B
Increment B register
DCR C
Decrement C register
HLT
Stop the program
Page 60
PSNCET
SAMPLE DATA:
Result of the Searching:

INPUT
Address
4250
(Data to be searched)
4251
(Array size)
OUTPUT
Data
Address
Data
75H
4200
(Result)
02H
06H
4252
23H
4253
75H
4254
C1H
4255
A7H
4256
75H
4257
12H
The result shows the number of times,

the given number that was found in
the array.
EXERCISE:
INPUT
Address
OUTPUT
Data
4250
(Data to be searched)
4251
(Array size)
Address
Data
4200
(Result)
4252
4253
4254
The result shows the number of times,

the given number that was found in
the array.
4255
4256
RESULT:
Thus the assembly language program for searching the given data from an array is
executed and the result is verified
Page 61
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Fig. Flow chart for Sorting in Ascending order on 8086.
Page 62
PSNCET
EXP. NO.
Date: _________
TITLE:
SORTING PROGRAM
AIM: To write an assembly language program for the sorting in ascending and
Descending order, using 8086.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
The Bubble-Sort technique is used to sort the numbers in either ascending order or
descending order. The numbers to be sorted is stored in the memory as a array with
the first location containing the count of the data in the array. The sorted numbers
are stored back again in the same source location of the array.
(I) ALGORITHM: ASCENDING ORDER:

2. Move data to CX register and move CX data to DI register
3. Move 1200 to the BX register and move the content of 1200 to memory of AX
4. Compare the content of AX with 1202
5. Jump on borrow to rep
6. Move the data in memory to AX and move Data from AX to AI
7. Add Data to BX register and go to loop2
8. Perform no operation and move data & DI to CX
9. Go to the loop
10. Stop the program
Page 63
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
1000
B9, 07, 00
1003
89 CF
1005
BB, 00, 12
1008
8B, 07
100A
3B, 47, 02
CMP
AX,AI[BX+2]
Move the content of 1200 to

memory of AX
Compare the content of AX
with 1202H
100D
72, 05
JB REP
Jump on borrow to rep
100F
87, 47, 02
XCHG
AX,AI[BX+2]
Move the data in memory to

AX
1012
89, 07
MOV AI[BX],AX
Move data from AX to AI
101A
83, C3, 02
ADD BX,02
Add data to BX register
1017
F2, EF
LOOP LOOP2
Go to loop2
1019
90
NOP
No operation
101A
89, F9
MOV CX,DI
Move data of DI to CX
101C
E2, E5
LOOP LOOP1
Go to loop1
101E
F4
HLT
Stop the process
LOOP1:
LOOP2:
REP:
MOV CX,07
Move data to CX reg
MOV DI,CX
Move CX data to DI
MOV BX,1200
Move 1200 to the BX reg
MOV AX,AI[BX]
Page 64
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SAMPLE DATA:
Result of Sorting in Ascending order:
INPUT
OUTPUT
Address
Data
Address
Data
1100
00FFH
1100
00CCH
1102
0100H
1102
00FEH
1104
1101H
1104
00FFH
1106
00FEH
1106
0100H
1108
00CCH
1108
1101H
110A
CDEFH
110A
1234H
110C
ABCDH
110C
ABCDH
110E
1234H
110E
CDEFH
EXERCISE:
INPUT
Address
OUTPUT
Data
Address
1100
1100
1102
1102
1104
1104
1106
1106
1108
1108
110A
110A
110C
110C
110E
110E
Data
Page 65
PSNCET
Fig. Flow chart for Sorting in Descending order on 8086.
Page 66
PSNCET
(II) ALGORITHM : DESCENDING ORDER

2. Move the data to CX register and move CX content to D1 register.
3. Move the address to BX register and move the count of 1200 to AX.
4. Compare the content of AX with 1202.
5. Jump on no borrow to REP.
6. Exchange AX and A1 register and move AX register to BX.
7. Add BX register to 2 and continue the loop up to CX is zero.
8. Perform no operation and move D1 register to CX register and continue
the loop up to CX is zero.
Page 67
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
1000
B9, 07, 00
1003
89 CF
1005
BB, 00, 12
1008
8B, 07
100A
3B, 47, 02
CMP
AX,AI[BX+2]
Move the content of 1200 to

memory of AX
Compare the content of AX
with 1202H
100D
72, 05
JNB REP
Jump on No-borrow to REP
100F
87, 47, 02
XCHG
AX,AI[BX+2]
Move the data in memory to

AX
1012
89, 07
MOV AI[BX],AX
Move data from AX to AI
101A
83, C3, 02
ADD BX,02
Add data to BX register
1017
F2, EF
LOOP LOOP2
Go to LOOP2
1019
90
NOP
No operation
101A
89, F9
MOV CX,DI
Move data of DI to CX
101C
E2, E5
LOOP LOOP1
Go to LOOP1
101E
F4
HLT
Stop the process
LOOP1:
LOOP2:
REP:
MOV CX,07
Move data to CX reg
MOV DI,CX
Move CX data to DI
MOV BX,1200
Move 1200 to the BX reg
MOV AX,AI[BX]
Page 68
PSNCET
SAMPLE DATA:
Result of Sorting in Descending order:
INPUT
OUTPUT
Address
Data
Address
Data
1100
00FFH
1100
CDEFH
1102
0100H
1102
ABCDH
1104
1101H
1104
1234H
1106
00FEH
1106
1101H
1108
00CCH
1108
0100H
110A
CDEFH
110A
00FFH
110C
ABCDH
110C
00FEH
110E
1234H
110E
00CCH
EXERCISE:
INPUT
Address
OUTPUT
Data
Address
1100
1100
1102
1102
1104
1104
1106
1106
1108
1108
110A
110A
110C
110C
110E
110E
Data
RESULT:
Thus the assembly language programs for sorting- ascending & descending order was
executed are verified.
Page 69
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EXPT NO: 3(b)
Program for sorting and searching using 8086
DATE:
AIM
To search a number (largest, smallest) and Sorting (Ascending and Descending) of an array
using 8086.
APPARATUS REQUIRED:
Sl.No.
1
2
Apparatus required
8086 Microprocessor Kit
DC Power Supply 5V
Quantity
1
1
ALGORITHM
SEARCHING
SMALLEST ELEMENT IN AN ARRAY
1. Load the starting address of the array in SI register
2. Load the address of the result in DI register
3. Load the number of bytes in the array in CL register
4. Increment the array pointer(SI register)
5. Get the first byte of the array in AL register.
6. Decrement the byte count(CL register)
8. Get next byte of the array in BL register.
9. Compare current smallest (AL) and next byte (BL) of the array.
10. Move BL to AL
11. Decrement the byte count (CL register)
12. Check zero flag.If zero flag is reset then go to step-7,otherwise go to next step.
13. Save the smallest data in memory pointed by DI
14. Stop
LARGEST ELEMENT IN AN ARRAY
1. Load the starting address of the array in SI register
2. Load the address of the result in DI register
3. Load the number of bytes in the array in CL register
5. Get the first byte of the array in AL register.
6. Decrement the byte count(CL register)
8. Get next byte of the array in BL register.
9. Compare current largest (AL) and next byte (BL) of the array.
10. Move BL to AL
11. Decrement the byte count (CL register)
Page 70
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12. Check zero flag.If zero flag is reset then go to step-7,otherwise go to next step.
13. Save the largest data in memory pointed by DI
14. Stop
ASCENDING ORDER IN AN ARRAY
1. Set SI register as pointer for array
2. Set CL register as count for N-1 repeatitions
3. Initialize array pointer
4. Set CH as count for N-1 comparisions
5. Increment the array pointer
6. Get an element of array in AL register
8. Compare the next element of the array with AL.
9. Check carry flag.If carry flag is set then go to step-12,otherwise go to next step.
10. Exchange the content of memory pointed by SI and the content of previous memory location
for this,exchange AL and memory pointed by SI,and then exchange AL and memory pointed
by SI-1
11. Decrement the count for comparisions(CH register)
12. Check zero flag .If zero flag is reset then go to step-6,otherwise go to next step
13. Decrement the count for repeatitions (CL register)
15. Stop
DESCENDING ORDER IN AN ARRAY
1. Set SI register as pointer for array
2. Set CL register as count for N-1 repetitions
3. Initialize array pointer
4. Set CH as count for N-1 comparisions
6. Get an element of array in AL register
8. Compare the next element of the array with AL.
9. Check carry flag.If carry flag is reset then go to step-12,otherwise go to next step.
10. Exchange the content of memory pointed by SI and the content of previous memory location
(for this,exchange AL and memory pointed by SI,and then exchange AL and memory
pointed by SI-1
11. Decrement the count for comparisions(CH register)
13. Decrement the count for repetitions (CL register)
15. Stop
Page 71
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SMALLEST ELEMENT IN AN ARRAY
Flow Chart
Start
Load the address of array in SI register

and address of given data in DI register
Load the address of result in DI register
Set CL as byte count
Increment array pointer(SI)
Get the first byte of array in AL register

Decrement the byte count
Get the next byte of array in BL register
Compare AL and DL register

YES
Is
CF=1?
NO
Move BL to AL
Decrement byte count (CL)
Is
NO
ZF=1?
YES
Store AL in memory
Stop
Page 72
PSNCET
PROGRAM:
Address
8000
Mnemonics
MOV SI,1100
Opcode
BE 11 00
Comments
Set SI register as
pointer for array
8003
MOV DI,1200
BF 12 00
8006
MOV CL,[SI]
8A 0C
Set DI register as
pointer for result
Set CL as count for
elements in the array
INC SI
46
8009
MOV AL,[SI]
8A 04
800B
800D
DEC CL
INC SI
FE C9
46
Decrement the count

Make SI to point to
next data in array
800E
MOV BL,[SI]
8A 1C
8010
CMP AL,BL
3A C3
8012
JC AHEAD
72 02
8014
MOV AL,BL
8A C3
DEC CL
JNZ AGAIN
FE C9
75 F3
801A
MOV [DI],AL
88 05
Get the next data in

BL register
Compare current
smallest data in AL
with BL
If carry is set then AL
is less than BL hence
proceed to AHEAD
If carry is not set then
make BL as current
smallest
Decrement the count
If count is not zero
repeat search
Store the smallest data
in memory
801C
INT 3
F4
8008
8016
8018
Label
START
AGAIN
AHEAD
Increment the address

pointer
Set first data as
Smallest
Page 73
PSNCET

Start
LARGEST ELEMENT IN AN ARRAY

FLOW CHART
Set SI register as array pointer
Set DI register as array pointer

Set CL as byte count
Get the first byte of array in AL register
Decrement the byte count
Get the next byte of array in BL register
Compare AL and DL register
Yes
Is
CF=0?
NO
Move BL to AL
Decrement byte count (CL)
NO
Is
ZF=1?
Yes
Store AL in memory
Stop
Page 74
PSNCET
PROGRAM:
Address
8000
Mnemonics
MOV SI,1100
Opcode
BE 11 00
Comments
Set SI register as
pointer for array
8003
MOV DI,1200
BF 12 00
8006
MOV CL,[SI]
8A 0C
Set DI register as
pointer for result
Set CL as count for
elements in the array
INC SI
46
8009
MOV AL,[SI]
8A 04
800B
800D
DEC CL
INC SI
FE C9
46
Decrement the count

Make SI to point to
next data in array
800E
MOV BL,[SI]
8A 1C
8010
CMP AL,BL
3A C3
8012
JNC AHEAD
73 02
8014
MOV AL,BL
8A C3
DEC CL
JNZ AGAIN
FE C9
75 F3
801A
MOV [DI],AL
88 05
Get the next data in

BL register
Compare current
largest data in AL
with BL
If carry is set then AL
is greater than BL
hence proceed to
AHEAD
If carry is not set then
make BL as current
largest
Decrement the count
If count is not zero
repeat search
Store the largest data
in memory
801C
INT 3
F4
8008
8016
8018
Label
START
AGAIN
AHEAD
Increment the address

pointer
Set first data as largest
Page 75
PSNCET
ASCENDING ORDER IN AN ARRAY

FLOW CHART
Start
Load the address of the array in SI register

Load the count in CL register and decrement by one
Load the count in CH register and decrement by one
Increment the array pointer (SI)
Get an element of array pointer(SI)
Compare next element of array with AL

No
Is
CF=1?
Yes
Exchange AL and memory pointed by SI
Exchange AL and memory pointed by (SI-1)
Decrement CH count
Is
ZF=1?
Decrement CL count
No
Is
ZF=1?
Yes
Stop
Page 76
PSNCET
PROGRAM:
Address
8000
Mnemonics
MOV SI,1100
Opcode
BE 11 00
Comments
Set SI register as
pointer for array
8003
MOV CL,[SI]
8A 0C
8005
DEC CL
FE C9
Set CL as count for N-1

repeatitions
Decrement the count
MOV SI,1100
MOV CH,[SI]
BE 11 00
8A 2C
DEC CH
INC SI
FE CD
46
MOV AL,[SI]
8A 04
8011
8012
INC SI
CMP AL,[SI]
46
3A 04
8014
JC AHEAD
72 05
8016
XCHG AL,[SI]
86 04
8018
801B
XCHG AL,[SI-1]
DCE CH
86 44 FF
FE CD
801D
JNZ REPCOM
75 F0
DEC CH
FE C9
8021
JNZ REPEAT
75 E4
8023
INT 3
F4
8007
800A
Label
START
REPEAT
800C
800E
800F
801F
REPCOM
AHEAD
Intialize pointer
Set Ch as count for N-1
comparisions
Increment the pointer
Get an element of array
in AL register
Compare with next
element of array in
memory
If AL is less than
memory ,then go to
AHEAD
If AL is lesser than
memory then exchange
the content of memory
pointed by SI and the
previous memory
location
Decrement the count for
comparisions
Repeat comparision
until CH count is zero
repeatitions
Repeat N-1
comparisions until CL
count is zero
Page 77
PSNCET

Start
DESCENDING ORDER IN AN ARRAY

FLOW CHART
Load the address of the array in SI register
Load the count in CL register and decrement by one

Load the count in CH register and decrement by one
Get an element of array pointer(SI)
Compare next element of array with AL
No
Is
CF=0?
Yes
Exchange AL and memory pointed by SI
Exchange AL and memory pointed by (SI-1)

Decrement CH count
No
Is
ZF=1?
Yes
Decrement CL count
Yes
Is
ZF=1?
No
Stop
Page 78
PSNCET
PROGRAM:
Address
8000
Mnemonics
MOV SI,1100
Opcode
BE 11 00
Comments
Set SI register as
pointer for array
8003
MOV CL,[SI]
8A 0C
8005
DEC CL
FE C9
Set CL as count for N-1

repeatitions
Decrement the count
MOV SI,1100
MOV CH,[SI]
BE 11 00
8A 2C
DEC CH
INC SI
FE CD
46
MOV AL,[SI]
8A 04
8011
8012
INC SI
CMP AL,[SI]
46
3A 04
8014
JNC AHEAD
73 05
8016
XCHG AL,[SI]
86 04
8018
801B
XCHG AL,[SI-1]
DCE CH
86 44 FF
FE CD
801D
JNZ REPCOM
75 F0
DEC CL
FE C9
8021
JNZ REPEAT
75 E4
8023
INT 3
F4
8007
800A
Label
START
REPEAT
800C
800E
800F
801F
REPCOM
AHEAD
Intialize pointer
Set Ch as count for N-1
comparisions
Increment the pointer
Get an element of array
in AL register
Compare with next
element of array in
memory
If AL is less than
memory ,then go to
AHEAD
If AL is lesser than
memory then exchange
the content of memory
pointed by SI and the
previous memory
location
comparisions
Repeat comparision
until CH count is zero
repeatitions
Repeat N-1
comparisions until CL
count is zero
Page 79
PSNCET
Result:
Smallest from an array
INPUT
Address
8100 H:
8101 H:
8102 H:
8103 H:
8104 H:
8105 H:
8106 H:
Data
OUTPUT
Address
Data
8200 H:
Largest from an array

INPUT
Address
8100 H:
8101 H:
8102 H:
8103 H:
8104 H:
8105 H:
8106 H:
Data
OUTPUT
Address
Data
8200 H:
Sort the array in ascending order

INPUT
Address
1100 H:
1101 H:
1102 H:
1103 H:
1104 H:
1105 H:
1106 H:
1107 H:
Data
OUTPUT
Address
Data
1101 H:
1102 H:
1103 H:
1104 H:
1105 H:
1106 H:
1107 H:
Sort the array in descending order

INPUT
Address
1100 H:
1101 H:
1102 H:
1103 H:
1104 H:
1105 H:
1106 H:
1107 H:
Data
OUTPUT
Address
Data
1101 H:
1102 H:
1103 H:
1104 H:
1105 H:
1106 H:
1107 H:
Page 80
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Fig. Flow chart for String Manipulation
Page 81
PSNCET
EXP. NO.
Date: _________
STRING MANIPULATION USING 8086
TITLE:
AIM: To write an assembly language program to move a byte of string of length FF

from a source to a destination.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
Power supply unit
THEORY:
A group of similar data stored in consecutive memory locations, representing a
variable can be celled as a String. Various operations can be performed on the string
data like, string copy, string compare, string store, string load, etc. The following
program helps to copy a string data from a source location to a destination location.
ALGORITHM:
2. Set the SI to point the source array and DI at destination location.
3. Move the string size to CX register.
4. Direction Flag is cleared so that SI & DI will auto increment after each loop.
5. Move the bytes of the string using MOVSB instruction.
6. Stop
Page 82
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
1000
BE, 00, 11
MOV SI, Source
1003
BF, 00, 12
MOV DI, Destination
1006
B9, FF, 00
MOV CX, 00FFH
1009
FC
100A
A4
100B
E2, FD
100D
F4
CLD
NEXT:
MOV SB
LOOP NEXT
HLT
Comments
Load offset address of
Source to SI register
Load offset address of
destination to DI register
Number of array elements
in CX register
Clear Direction Flag (D)
Move string byte
Decrement CX and Check
for Zero. If not zero,
go to location NEXT
Stop the program
Page 83
PSNCET
SAMPLE DATA:
Result of String manipulation:
INPUT (Source)
OUTPUT (Destination)
Address
Data
Address
Data
1100
xx
1200
xx
To
xx
To
xx
11FF
xx
12FF
xx
As CX Register is loaded with string size FF

256 bytes of data at source location
(starting from 1100H)
will be copied to destination location
(at address 1200H)
EXERCISE:
Result of String manipulation:
INPUT (Source)
Address
Data
OUTPUT (Destination)
Address
1100
1200
1101
1201
1102
1202
1103
1203
1104
1204
1105
1205
1106
1206
1107
1207
1108
1208
Data
Execute the program with following modifications.

a) Move smaller sized string data, by changing the string size stored in CX
register.
b) Change the auto-increment of SI & DI registers to auto-decrement by setting
the direction flag to 1. Also store the last address of the string in SI & DI
register instead of starting address of the string.
RESULT:
Thus the string was moved from source to destination using the assembly language
of 8086.
Page 84
PSNCET
Flow Chart:
PROGRAM (16-bit Addition):

Address
Opcode &
Operand
Label
Mnemonics
CLR C
Comments
4100
C3
4101
74, Data1L
MOV A, #DATA1
Move Data1L to Acc
4103
24, Data2L
ADD A, #DATA2
Add Data2L with Acc
4105
90, 41, 50
MOV DPTR,
#4150h
4108
F0
MOVX @DPTR, A
4109
A3
INC DPTR
410A
74, Data1H
MOV A, #DATA1
410C
34, Data2H
ADDC A,
#DATA2
410E
F0
410F
80, FE
MOVX @DPTR, A
HERE:
SJMP HERE
Clear carry
Move content in 4500 to

DPTR.
Move data to DPTR location
Increment DPTR
Move Data1H to Acc
Add Acc with Data2H & Carry
Move from Acc
to DPTR location
End
Page 85
PSNCET
EXP. NO:
TITLE:
Date: _________
PROGRAMMING ARITHMETIC, LOGICAL AND
BIT MANIPULATION USING 8051
AIM: To write an assembly language program for the arithmetic, logical and bit
manipulation using 8051.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8051Micro Controller kit.
Power Supply unit
(A) ARITHMETIC OPERATION:
(I) 16 BIT ADDITION:

ALGORITHM:
st
2. Get the LSB of 1 and 2
nd
operands.
3. Add the LSB of the two operands and store it in memory.

st
4. Get the MSB of 1 and 2nd operands.

5. Add the MSB and store the result in memory
OUTPUT OF 16-BIT ADDITION:
INPUT
Address
OUTPUT
Data
Address
Data
4102
4500
4104
4501
410B
410D
Page 86
PSNCET
Flow Chart:
PROGRAM (8-bit Subtraction):

Address
Opcode &
Operand
Label
Mnemonics
CLR C
Comments
4100
C3
4101
74, Data1
MOV A, #DATA1
Move data1 to acc
4103
94, Data2
SUBB A, #DATA2
Add data2 with acc
4105
90, 45, 00
MOV DPTR,
#4500h
4108
FO
4109
80, FE
MOVX @DPTR, A
HERE:
SJMP HERE
Clear carry
Move 4500 to DPTR.

Move Acc value to DPTR
location
End
Page 87
PSNCET
(II) 8- BIT SUBTRACTION:

ALGORITHM:
2. Clear the carry flag and load the first operand in accumulator.
3. Get the 2
nd
operand and subtract it from accumulator.
4. Store the result in memory.

OUTPUT OF 8-BIT Subtraction without Carry:
INPUT
Address
OUTPUT
Data
Address
4102
4500
4104
Data
Page 88
PSNCET
Flow Chart:
PROGRAM (8-bit Multiplication):

Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
74, Data1
MOV A, #DATA1
Move Data1 to Acc
4102
75, F0, Data2
MOV B, #DATA2
Move Data2 to Acc
4105
A4
MUL AB
Multiply Acc and B
4106
90, 45, 00
MOV DPTR,
#4500h
Move 4500 to DPTR.
4109
FO
MOVX @DPTR, A

location
410A
A3
INC DPTR
INC DPTR
410B
E5, F0
MOV A, B
410D
FO
410E
80, FE
MOVX @DPTR, A
HERE:
SJMP HERE
Move B register value to

Acc
location
End
Page 89
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(III) 8-BIT MULTIPLICATION:

ALGORITHM:
st
2. Load the 1 operand in A and 2
nd
operand in B.
3. Multiply A and B contents using MUL instruction.

OUTPUT OF 8-BIT Multiplication:
INPUT
Address
OUTPUT
Data
Address
4101
4500
4104
4501
Data
Page 90
PSNCET
Flow Chart:
PROGRAM (8-Bit Division):

Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
74, Data1
MOV A, #DATA1
Move Dividend to Acc
4102
75, F0, Data2
MOV B, #DATA1
Move Divisor to B
4105
84
4106
90, 45, 00
4109
FO
MOVX @DPTR, A
410A
A3
INC DPTR
Increment DPTR
410B
E5, F0
MOV A, B
Move B-reg. value to Acc
410D
FO
410E
80, FE
DIV AB
MOV DPTR,
#4500h
MOVX @DPTR, A
HERE:
SJMP HERE
Divide A by B
Move 4500 to DPTR.
location
Store the result

End
Page 91
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(IV) 8 BIT DIVISION:

ALGORITHM:
st
nd
2. Get 1 operand in A and 2
in B.
3. Divide A by B contents using division instruction.

OUTPUT OF 8-BIT Division:

INPUT
Address
4101
4104
OUTPUT
Data
Address
Data
4500
(Quotient)
4501
(Remainder)
Page 92
PSNCET
Flow Chart:
PROGRAM (OR):
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
74, Data1
MOV A, #DATA1
Move Data1 to Acc
4102
44, Data2
ORL A, #DATA2
OR Acc and Data2
4104
90, 45, 00
MOV DPTR,
#4500H
4107
FO
4108
80, FE
MOVX @DPTR, A
HERE
SJMP HERE
Move 4500 to DPTR.

Store the result
End
Page 93
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(B) LOGICAL OPERATION:
(I) OR OPERATION:
ALGORITHM:
st
2. Load 1 operand in Accumulator.

3. Get 2
nd
operand and perform OR between Acc and 2
nd
Operand.

OUTPUT OF OR Operation:
INPUT
Address
OUTPUT
Data
Address
4101
4500
4103
Data
Page 94
PSNCET
Flow Chart:
PROGRAM (AND):
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
74, Data1
MOV A, #DATA1
Move Data1 to Acc
4102
54, Data2
ADL A, #DATA2
AND Acc and Data2
4104
90, 45, 00
MOV DPTR,
#4500H
Move 4500 to DPTR.
4107
FO
4108
80, FE
MOVX @DPTR, A
HERE:
SJMP HERE
Store the result

End
Page 95
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(II) AND OPERATION:

ALGORITHM:
st
2. Get 1 operand in Accumulator.

3. Get 2
nd
nd
operand and perform AND accumulator content & 2
operand

OUTPUT OF AND Operation:

INPUT
Address
OUTPUT
Data
Address
4101
4500
4103
Data
RESULT:
Thus the programs involving arithmetic, logical and bit manipulation using 8051 are
executed and its results are verified.
Page 96
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Fig. Block diagram of ADC conversion
Page 97
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EXP. NO.
INTERFACING ADC AND DAC USING 8085
Date: _________
TITLE:
AIM: To write an assembly language program to interface ADC and DAC with 8085
microprocessor kit.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
CRO
ADC & DAC interface board
Flat ribbon Cable
THEORY:
In a real time applications, processing of input data, conversion of data from digital
to analog and vice versa, are indispensable. The following program initiates the
analog to digital conversion process, checks the EOC pin of ADC 0809 as to whether
the conversion is over and then inputs the data to the processor. It also instructs the
processor to store the converted digital data in the memory.
ADC:
HARDWARE DETAILS:
ADC 0809 is a monolithic CMOS device, with an 8-bit analog-to-digital converter, 8
channel multiplexer and microprocessor compatible control logic.
Selected
Analog Channel
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
Address Lines in the Multiplexer of ADC 0809

Addr C
Addr B
Addr A
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A particular input channel is selected by using address decoding. The conversion

th
begins at the falling edge of the SOC pulse. The conversion will complete before 8
clock pulse from the rising edge of SOC pulse.
Page 98
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PROGRAM FOR ADC:

Address
Opcode &
Operand
Label
Mnemonics
START:
MVI A,10H
4100
3E, 10
4102
D3, C8
OUT C8H
4104
3E, 18
MVI A, 18H
4106
D3, C8
OUT C8H
4108
3E, 01
MVI A, 01H
410A
D3, D0
OUT D0H
410C
AF
XRA A
410D
AF
XRA A
410E
AF
XRA A
410F
3E, 00
MVI A, 00H
4111
D3, D0
OUT D0H
4113
DB, D8
4115
E6, 01
ANI 01H
4117
FE, 01
CPI 01H
4119
C2, 13, 41
411C
DB, C0
411E
32, 50, 41
4121
76
Comments
Select the input channel
LOOP:
Send HIGH in SOC signal of

ADC
Waste time to make A/D

conversion to complete
Send LOW in SOC signal of

ADC
IN D8H
Check for EOC signal
JNZ LOOP
IN C0H
Input the digital data from

ADC interface
STA 4150
Store the data in memory
HLT
Stop the program
Page 99
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ALGORITHM:
2. Give start of conversion pulse and set the data.
3. Check for the end of the pulse.
4. Store the digital data in the memory.
OBSERVATION:
Execute this program and compare the data displayed at the LEDs with that of the
stored data at location 4150H.
Vin Analog Voltage

Set at input of ADC
Digital Output
seen in LED
Digital Output Stored in

memory location 4150
Page 100
PSNCET
Fig. Block diagram of the DAC interface with 8085 Kit.
Page 101
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DAC:
HARDWARE DETAILS:
Digital to analog converter can be classified as current output, voltage output,
multiplexing type. The electronic circuit that translates a digital to analog signal is
called as DAC. VBMB 002 contains two D/A converter using DAC 0800.
The basic microprocessor board VBMB 002 incorporates two 8-bit DAC0800.
DAC0800 is a monolithic high-speed current output type. Its unique features are
1. Typical setting of time loop

2. Complementary current o/p
3. Differential o/p voltage of 20 vpp with simple resistor loads
4. Two quadrant diode range multiplexing data
5. To decoding
6. D/A conversion circuit
SOFTWARE DETAILS:
ALGORITHM FOR GENERATION OF SQUARE WAVEFORM:
1. Load the data 00h to Acc and send it to DAC to produce analog output of -5v.
2. Call time delay routine
3. Load the data FFh to Acc and send it to DAC to produce analog output of +5v.
4. Time delay routine is called again
5. A square wave of amplitude 10v (p-p) is produced, when steps 1 to 4 is
repeated continuously.
Page 102
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PROGRAM FOR DAC:

Address
Opcode &
Operand
Label
Mnemonics
START:
MVI A,00H
Comments
4100
3E, 00
4102
D3, C8
4104
CD, 11, 41
4107
3E, FF
MVI A,FFH
4109
D3, C8
OUT C8H
410B
CD, 11, 41
CALL DELAY
Time delay is introduced
410E
C3, 00, 41
JMP START
Repeat from START again
OUT C8H
CALL DELAY
Output the data to DAC to

produce -5v
Time delay is introduced
Output of DAC to produce 5v
Delay Program
4111
06, 01
DELAY:
MVI B,05H
4113
0E, FF
L1:
MVI C,FFH
4115
0D
L2:
DCR C
4116
C2, 15, 41
JNZ L2
4119
05
DCR B
411A
C2, 13, 41
JNZ L1
410D
C9
RET
Return to Main program
Page 103
PSNCET
SAMPLE DATA:
Result observed in CRO for DAC

The amplitude and time period of Square wave form generated using DAC are
DESCRIPTION
OBSERVED OUTPUT
Amplitude (VP-P)
10
Time Period (ms)
17
EXERCISE:
Execute the program with different time delay and different input to DAC and
observe the results. Check the result with your manual calculation.
The amplitude and time period of Square wave form generated using DAC are
DESCRIPTION
OBSERVED OUTPUT
Amplitude (VP-P)
Time Period (ms)
RESULT:
Thus the interfacing of ADC and DAC are performed using 8085 microprocessor kit.
Page 104
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Fig. 12.1 movement of rotor for current in different windings
Fig. Bock diagram for stepper motor interface with 8085 kit
Page 105
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EXP. NO:
TITLE:
Date: __________
INTERFACING AND PROGRAMMING OF STEPPER MOTOR (8085)
AIM: To write a program to interface and program of stepper motor with 805.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8085Microprocessor kit.
Stepper Motor
Flat ribbon Cable
THEORY:
Stepper Motor:
A DC motor, in which the rotor makes only discrete angular movements in steps, is
called a Stepper Motor. The Stepper motor controlled by a microprocessor has variety
of applications in control system area and in process automations like, machine tools,
robotics, CNC lathes, etc.
Construction of stepper motor:

There are four windings in the Stator, named as A1, B1, A2, B2 and the Rotor has
three permanent magnets in it. The arrangement of stator and rotor can be seen in
figure 12.1. The movement occurs in the rotor in a stepwise manner, from one
equilibrium to the next.
Step size =
360__
Nr x Ns
Where, Nr is no. of pairs of poles in rotor and Ns is the no. of poles in stator
Note: With Ns=4 and Nr=3; Step size in the stepper motor will be 30
Page 106
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To make stepwise movement in the rotor of stepper motor, the coil windings in the
stator have to be energized appropriately.
The three different schemes for step movements in rotor of a stepper motor are,
a)
Wave scheme
b)
2-phase scheme
c)
Half or Mixed scheme
A. Wave Scheme:
In this scheme, the coil windings (A1, B2, A2, B1) of the stator of stepper motor are
cyclically excited with a DC current, to make clockwise movement in steps and in
reverse order for anti-clockwise movements.
Step
1
2
3
4
Anti Clockwise
A1 A2 B1
1
0
0
0
0
0
0
1
0
0
0
1
B2
0
1
0
0
Step
1
2
3
4
Clockwise
A1 A2 B1
0
0
1
0
1
0
0
0
0
1
0
0
B2
0
0
1
0
B. 2-Phase Scheme:
In this scheme, the two adjacent coil windings (A1-B2, B2-A2, A2-B1, B1-A1) of the
stator of stepper motor are cyclically excited with a DC current, to make clockwise
movement in steps and in reverse order for anti-clockwise movements.
Step
1
2
3
4
Anti Clockwise
A1 A2 B1
1
0
0
0
1
0
0
1
1
1
0
1
B2
1
1
0
0
Step
1
2
3
4
Clockwise
A1 A2 B1
1
0
1
0
1
1
0
1
0
1
0
0
B2
0
0
1
1
C. Half Scheme:
In this scheme, we obtain the movement of rotor in half of the original step size, by
interleaving these two schemes.
Note: 1 in the table indicates the supply of DC current to the stator coil winding.
Page 107
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Format of Data storage (in Lookup table) for DC current to the stator coil windings,
are as follows.
D7
D6
D5
D4
D3
D2
D2
D1
A1
A2
B1
B2
Example:
Data for step-1 in the 2-phase scheme (clockwise rotation) is 09
ALGORITHM:
2. Load the data (no. of steps) into B register
3. Load the address of the LOOKUP table memory to HL pair.
4. Load the data (containing current info in step-1) to Acc.
5. Send the data to Stepper motor interface.
6. Call a Delay routine.
7. Increment pointer to LOOKUP table (Address in HL pair).
8. Check whether all data have been taken from LOOKUP table
9. If not, Jump to step 4. Otherwise, Jump to step 2.
Page 108
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PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
START:
LXI H, 4150
Load Lookup table addr to HL
MVI B, 04H
Move no. of steps data to B
MOV A, M
Move data-I from Memory to

Acc and send it out
4100
21, 50, 41
4103
06, 04
4105
7E
4106
D3, C0
4108
11, 03, 03
410B
00
410C
1B
DCX D
410D
7B
MOV A, E
410E
B2
ORA D
410F
C2, 0B, 41
4112
23
INX H
Increment Data pointer
4113
05
DCR B
4114
C2, 05, 41
JNZ REPEAT
Check whether all 4 steps in

Lookup table is taken. If not,
Jump to Repeat.
4117
C3, 00, 41
JMP START
If Yes, Jump to Start.
REPEAT:
OUT C0H
LXI D, 0303H
DELAY:
NOP
Delay Program
JNZ DELAY
LOOKUP Table
4150
09, 05, 06, 0A
OUTPUT:
Execute the program and observe the movement of stepper motor.
Note:
1. To reverse the direction of rotation in stepper motor, Change the order of
stored data in LOOKUP table in reverse order.
2. To vary the speed of rotation, change the delay time in the program.
RESULT:
Thus the stepper motor is interfaced with 8085 processor and program for the control
of stepper motor is executed to verify the direction of rotation in both forward and
reverse direction and change in speed of rotation.
Page 109
PSNCET
EXP NO:
15
Date: _________
TITLE:
COMMUNICATION BETWEEN 8051 MICROCONTROLLER KIT AND PC
Aim: To communicate microcontroller kit and PC using the stepper motor in both
forward and reverse direction with delay program.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8051Micro Controller kit.
Stepper Motor
PC with Cross assembler software
Flat Ribbon Cable & RS232C Cable
1 Each
Theory:
The software which is used to compile (convert) the assembly language program into
a machine suitable for a particular processor, is called Cross Assembler. This
converted machine code is sent to the trainer kit through the serial cable (RS232)
and executed in the trainer kit.
CROSS ASSEMBLER:
You may use any text editor such as Notepad in Windows to edit your 8051 program.
Then you can assemble and link your program so as to make it loadable to the 8051
trainer kit for its execution.
ASSEMBLING:
Suppose your program is ready and is now stored in the working directory where the
8051 cross assembler and the 8051 linker are in, Run X8051.exe to activate the
cross assembler.
Page 110
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Figure C1 shows the user interface of the cross-assembler. In the interface, the cross
assembler will prompt for inputting listing destination, input filename and output
filename. You have to specify the input filename. As for others, you can skip them by
just entering ENTER key. If no error is detected by the cross-assembler, an object file
with extension .obj will be generated.
LINKING:
Run Link.exe to activate the linker. Figure C2 shows the user interface of the linker.
The linker will prompt for inputting parameters. All you need to do is to specify the
input filename. It should be an object file with extension .obj. As an example, Figure
C2 shows the case that the input file is Stepper.obj. You can skip all other prompts
by just entering ENTER key. If no error is detected, a binary file with extension .hex
will be generated.
The assembled program will be loaded into external memory of the 8051 trainer kit
through serial communication interface with PC and the same can be executed from
the trainer kit.
Page 111
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Algorithm:
1. Activate the assembler program.
2. Select the COM port for serial connection and Set the baud rate.
3. Open the stepper.asm program.
4. Assemble and link the opened assembly language program.
5. Initiate the transfer of generated Hex file to the trainer kit.
6. Execute the loaded program from trainer kit.
7. Observe the movement of stepper motor in desired direction & speed.
Page 112
PSNCET
PROGRAM (To be typed in TEXT editor for Assembling):

Address
Opcode &
Operand
Label
4100
Mnemonics
Comments
ORG 4100H
4100
90, 45, 00
START:
MOV DPTR, #4500H
4103
78, 04
4105
E0
4106
C0, 83
PUSH DPH
4108
C0, 82
PUSH DPL
410A
90, FF, C0
MOV DPTR, #FFC0H
410D
7A, 01
MOV R1,#04H
410F
79, 22
DLY1:
MOV R2, #FFH
4111
7B, FF
DLY2:
MOV R3, #FFH
4113
DB, FE
DLY3:
DJNZ R3, DLY3
4115
D9, FC
DJNZ R2, DLY2
4117
DA, FA
DJNZ R1, DLY1
4119
FO
MOVX @DPTR, A
411A
DO, 82
POP DPL
411C
D0, 83
POP DPH
411E
A3
INC DPTR
411F
D8, E4
DJNZ R0, REPEAT
4121
80, DD
SJMP START
MOV R0, #04H

REPEAT:
MOVX A, @DPTR
Load address to DPTR

Move 04 to Ro reg
Move Data
from DPTR location to Acc
Delay Program
4123
4500
Increment the DPTR

Decrement R0 and Jump to
REPEAT, until R0 = 00
Jump to Start
END
DB 09, 05,
06, 0A
TABLE
Look up table
Result:
Thus the program for stepper mot or interface with 8051-microcontroller kit through
PC was executed and its parameters like speed, direction was observed.
Page 113
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PIN DIAGRAM (8279):
CIRCUIT DIAGRAM (Keyboard and Display Interface)
Page 114
PSNCET
EXP. NO.
TITLE :
Date: _________
KEYBOARD AND DISPLAY INTERFACE 8279
AIM: To write a program to study 8279 Keyboard and display controller and also
initialize 8279 for rolling message in the display.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8279 Keyboard and display controller board
Flat ribbon Cable
THEORY:
Intel 8279 is responsible for key debouncing, coding of the keyboard matrix and
refreshing of the display elements in the microprocessor based system. Its main
functions are:
Simultaneous Keyboard and Display operation.
3 Input modes (Scanned Keyboard mode, Scanned sensor mode and Strobed
input entry mode.)
2 Output modes (8 character or 16 character display with left / right entry)
Clock Pre-scaler
Programmable scan timing
2-Key Lockout / N-Key Rollover mode selection
Auto increment facility for easy programming.
DESCRIPTION:
In the 8279 Keyboard and display interfacing, we adopt the mode in which we
want to operate the keyboard and display by initializing it. The clear display
command is executed to clear all the rows of the display RAM.
The data to be
displayed is fetched from Display RAM and displayed at first digit of display. A
counter is initialized and its value is decremented until all the values are displayed. A
delay is set such that the display is made for a period. The write display RAM
Command word is used it set the auto increment flag.
The various command words of 8279 are:
Page 115
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KEYBOARD AND DISPLAY MODE SET:

0
CF
CA
Where, DD is the display mode and KKK is the keyboard mode.
DD:
0
8 character display-left entry.
8 character display-right entry.
KKK:
0
Encoded scan keyboard-2 key lockout.
Decoded scan keyboard-2 key lockout.
Encoded scan keyboard-N key lockout.
Decoded scan keyboard-N key lockout.
Encoded scan sensor matrix.
Decoded scan sensor matrix.
Strobed input encoded scan display.
Strobed output decoded scan display.
CLEAR HISTORY:
1
CD
CD
0
0
1
1
CD
CD
x
0
0
1
A0-3
A0-3
A0-3
A0-3
CD
B0-3
B0-3
B0-3
B0-3
=
=
=
=
CD
00 (0000 0000)
00 (0000 0000)
20 (0010 0000)
FF (1111 1111)
Enables clear display when CD=1, the rows of display are cleared by the code set by
lower two CD bits
CF->
If CF=1, FIFO status is cleared, interrupt O/P line is reset sensor RAM
pointer is set to row 0.
CA-> Clear all bits has the combined effect of CD and CF. If uses the CD clearing
mode on display RAM and clears FIFO status. It also resynchronizes the
internal timing chain.
Page 116
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WRITE DISPLAY RAM:

1
AI
AI-> Auto Increment flag,

If the AI is 1; then row address selected will be incremented after each
read and write to the display RAM.
AAAA-> To select, 1 of the 16 rows of display RAM.
READ FIFO STATUS

DU
S/E
NNN -> Number of characters in the FIFO.

F
-> FIFO full.
-> Error under run (occurs when CPU read empty FIFO).
-> Error overrun (occurs when char try to enter the full FIFO).
S/E
-> Sensor closure/Error flag for multiple closures
DU
-> Display unavailable.
READ FIFO/SENSOR RAM:

0
AI
X -> dont care.

AI -> Auto increment flag irrelevant 16 scanned key mode. For the sensor matrix
mode. If AI=1 then each successive read will be from subsequent row of
sensor.
AAA->In the scanned Keyboard mode irrelevant in sensor matrix mode if select
one of the rows of sensor RAM.
Page 117
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SCANNED KEYBOARD SPECIAL ERROR MODE:

1
X=dont care
If during a single debounced cycle, two keys are found pressed, this is considered as
simultaneous multiple depression and sets error flag. This flag prevent any further
writing into FIFO and set interrupt. This error flag is rest by sending the normal clear
command CF=1.
PROGRAM CLOCK:
0
All timing and multiplexing signals for the 8279 are generated by an internal
Prescaler. This Prescaler divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer which ranges from 2 to 31.
Choosing a divisor that yield 100KHZ will give the specified scan and debounce times.
For instance if pin 3 of the 8279 is being cluched by 2MHZ signal, PPPPP should be
set to 10100 to divide the clock by 20 to yield the proper 100KHZ operating
frequency.
READ DISPLAY RAM:

0
AI
The CPU sets up the 8279 for a read of the display RAM by the first writing this
command. The address bits AAAA select one the 16 rows of the display RAM. If the
AI flag is set this row address will be incremented after each of the following read
and write operation of display RAM. Since the same counter is used for both reading
and writing this command sets the next read or write address and the sense of the
auto increment mode for both operations.
DISPLAY WRITE INHIBIT/BLANKING:

1
1W
1W
BL
BL
The 1W bits can be used to mask nibble A and nibble B in applications requiring
separate 4-bit display.
Page 118
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Segment Definition for 7-Segment Display:
8279 Output
A3
A2
A1
A0
B3
B2
B1
B0
Data Bus
D7
D6
D5
D4
D3
D2
D1
D0
Segments
dp
Note:
It must be noted that, 0 in segment makes it glow and 1 makes it blank.
PROGRAM:
TO ACCEPT A KEY AND DISPLAY IT:
The below program accepts the key pressed in the interface board which is connected
to the kit and displays the same in the display in the interface board.
ALGORITHM:
1.
Initialize 8279 by selecting display & keyboard mode
2.
Send the command word for clearing display
3.
Send command word to select row of display ram
4.
Clear display
5.
Check for key pressing
6.
Send read FIFO ram command
7.
Input the data from FIFO ram
8.
Get display code from lookup table
9.
Display character on LED display
10.
Go to step 5
Page 119
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PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
Load count for no. of char.
4100
06, 08
MVI B, 08H
4102
3E, 00
MVI A, 00H
4104
D3, C2
OUT C2
4106
3E, CC
MVI A, CC
4108
D3, C2
OUT C2
410A
3E, 90
MVI A, 90
410C
D3, C2
OUT C2
410E
3E, FF
MVI A,FF
4110
D3, C0
4112
05
4113
C2, 10, 41
4116
DB, C2
4118
E6, 07
411A
CA, 16, 41
411D
3E, 40
MVI A, 40
411F
D3, C2
OUT C2
4121
DB, C0
IN C0
4123
E6, 0F
ANI 0F
4125
6F
MOV L, A
4126
26, 42
MVI H,42
4128
7E
MOV A, M
4129
D3, C0
412B
C3, 16, 41
Mode and display set
Clear display RAM
BACK:
Write display
(select a row in display RAM)
Load data to clear display
OUT C0
DCR B
Clears 8 Characters
of the Display
JNZ BACK
LOOP:
IN C2
ANI 07
Look for pressing of a key
JZ LOOP
Set to send FIFO RAM
4200
to
420F
0C, 9F,
99, 29,
08, 09,
6C, 1A,
OUT C0
JMP LOOP
4A, 0B,
28, 8F,
88, 38,
68, E8.
Read FIFO RAM
Frame memory pointer by

joining 42 and Key no., from
FIFO RAM
Retrieve data from lookup
table in memory
Display data
in 8279 Interface
Repeat same for next key
LOOK UP TABLE
for the 7-segment display code
corresponding to each number
starting from 0 to F in HEX.
RESULT:
Thus the Program of Interfacing 8279 Keyboard and Display is executed and verified.
Page 120
PSNCET
Fig. 8 Pin Diagram & Architecture of 8259 (PIC)
Page 121
PSNCET
EXP. NO:
Date: _________
TITLE :
8259 - PROGRAMMABLE INTERRUPT CONTROLLER
AIM: To
write an
assembly program
to
study
the
Characteristics
of 8259
Programmable Interrupt Controller.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8085-Microprocessor kit.
8259Programmable interrupt controller board
Flat ribbon Cable
HARDWARE DESCRIPTION:
The 8259 interface board comprises of the programmable Interrupt Controller, Intel
8259. The 8259 serves as an interface between interrupt request sent from multiple
I/O devices and the 8085 processor which is connected to INTR interrupt pin. Thus, it
functions as a overall manager in an interrupt driven system environment.
The special features of 8259 are
Eight
level
priority
controller,
expandable
to
64
levels
and
programmable Interrupt modes. Individual request mask capability is

there.
The 8259 are designed to minimize the software and real time
overhead in handling multilevel priority interrupts.
It has several
modes permitting optimization for a variety of S/M requirements.
The 8259 consist of the following parts

- Interrupt Mask Register (IMR), Interrupt Request Register (IRR)
- Interrupt Service Register (ISR)
- Priority Resolver (PR)
- Data Bus Buffer
- R/W Control Logic
The 8259 can be easily interconnected in a system of one master with

up to eight slaves to handle up to 64 priority levels.
Page 122
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ICW1 (Initialization Command Word One)

D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
LTIM
ADI
SNGL
IC4
D0:
IC4: 0=no ICW4, 1=ICW4 required
D1:
SNGL: 1=Single PIC, 0=Cascaded PIC
D2:
ADI: Address interval. Used only in 8085, not 8086.

1=ISR's are 4 bytes apart (0200, 0204, etc)
0=ISR's are 8 bytes apart (0200, 0208, etc)
D3:
LTIM: level triggered interrupt mode:

1=All IR lines level triggered.
0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment.

A7 A6 A5 A4 A3 A2 A1 A0
The lower byte is
ICW2 (Initialization Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
ICW3 (Initialization Command Word Three)

D7
D6
D5
D4
D3
D2
D1
D0
Master
S7
S6
S5
S4
S3
S2
S1
S0
Slave
ID3
ID2
ID1
Master mode:
1 indicates slave is present on that interrupt, 0 indicates direct interrupt
Slave mode:
ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000
0100)
Page 123
PSNCET
ICW4 (Initialization Command Word Four)

D7
D6
D5
D4
D3
D2
D1
D0
SFNM
BUF
M/S
AEOI
Mode
SFNM: 1=Special Fully Nested Mode, 0=FNM
M/S:
AEOI: 1=Auto End of Interrupt, 0=Normal
Mode: 0=8085, 1=8086
1=Master, 0=Slave
OCW1 (Operational Command Word One)

D7
D6
D5
D4
D3
D2
D1
D0
M7
M6
M5
M4
M3
M2
M1
M0
IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)
OCW2 (Operational Command Word Two)

D7
D6
D5
D4
D3
D2
D1
D0
SL
EOI
L3
L2
L1
Details
SL
EOI
Non specific EOI (L3L2L1=000)
Specific EOI command (Interrupt to

clear given by L3L2L1)
Rotate priorities on non-specific EOI
Rotate priorities in auto EOI mode

set
Rotate priorities in auto EOI mode

clear
Rotate priority on specific EOI

command (resets current ISR bit)
Set priority
(does not reset current ISR bit)
No operation
EOI
Auto rotation of priorities

(L3L2L1=000)
Specific rotation of priorities

(Lowest priority ISR=L3L2L1)
Action
Page 124
PSNCET
OCW3 (Operational Command Word Three)

D7
D6
D5
D4
D3
D2
D1
D0
D7
ESMM
SMM
MODE
RIR
RIS
ESMM SMM
Effect
No effect
Reset special mask
Set special mask
Page 125
PSNCET
THEORY:
When one or more the Interrupt requests are received from I/O devices through the
interrupt Request lines (IR0-IR7), the corresponding (IRR bits) are set in IRR
register. The 8259 evaluates these requests and send an Interrupt signal to the CPU
through INTR. The CPU upon receiving the Interrupt request from 8259, it responds
back with an Interrupt Acknowledge signal through INTA. Upon receiving an INTA
from the CPU, the highest priority bit is set in Interrupt Service Register (ISR) and
the corresponding IRR bit is reset and 8259 also releases a CALL Instruction code
(1100 1101) onto the 8 bit data bus through its D7-D0 pins. On receiving the opcode
for CALL instruction from 8259, the processor (8085) initiates two more INTA signals
to the 8259. These two INTA signals allow the 8259 to release its preprogrammed
interrupt subroutine (ISR) address on to the data bus. The lower 8-bit address is
released at the first INTA signal and the higher 8-bit address is released at the
second INTR signal. In the AEOI (Automatic End of Interrupt) mode, the ISR bit is
reset of the end of the third INTA signal otherwise the ISR bit remains set until an
appropriate EOI command is issued at the end of interrupt sequence.
ALGORITHM:
2. Initialize 8259 with the following specifications
a) ICW4 needed
b) Single 8259
c) Address Interval of 4 bytes
d) Edge triggered mode
e) A7, A6, A5 = 0 0 0
f)
Set Interrupt Service Address for selected as 5000H
g) 8085 mode
h) Normal End of Interrupt (EOI)
i)
Non-buffered Mode (since we dont use buffers)
j)
No special fully nested mode
k) Mask all interrupts except desired interrupt (say IR0)

3. Press the selected interrupt in interface board
4. Execute ISR corresponding to selected interrupt at 5000H
5. stop the program
Page 126
PSNCET
PROGRAM:
Address
Opcode &
Operand
Label
Mnemonics
Comments
4100
3E, 17
MVI A, 17H
4102
D3, C0
OUT C0H
4104
3E, 50
MVI A, 50H
4106
D3, C2
OUT C2H
4108
3E, 00
MVI A, 00
410A
D3, C2
OUT C2H
410C
3E, FE
MVI A, FE
410E
D3, C2
OUT C2H
Load value in Acc for

selecting one of the eight
interrupts in 8259 interface
4110
76
HLT
Stop the program
Initialize 8259
as per the
set configuration
Program for ISR at 5000H

5000
3E, 20
MV1 A, 20H
5002
D3, C0
OUT C0H
5004
CF
RST1
Page 127
PSNCET
OBSERVATION:
If you press the switch IR0 (when Acc is loaded with data FE), the CPU jumps to the
location 5000H. The 8259 will not accept any more interrupt at IR0, since AEOI is not
set. The end of interrupt (EOI) should be given through OCW2 in ISR program at
5000H.
Upon pressing the IR0 switch in the 8259 interface board, the ISR program at 5000H
automatically makes the 8085 trainer kit to get resetted.
The value loaded into Acc for selecting the interrupt request switch in 8259 interface
board can be changed. Upon executing of the main program again, we can see the
kit getting resetted on pressing of selected interrupt switch at the 8259 interface
board.
RESULT:
Thus the 8259 Interface board is connected with 8085 and its operation is
understood.
Page 128
PSNCET
Page 129
PSNCET
Page 130
PSNCET
EXP. NO:
TITLE:
Date: _________
8255 PPI INTERFACE WITH 8085 FOR PARALLEL COMM.
AIM: To establish the parallel communication between two microprocessor kits using
8255 PPI interface.
APPARATUS REQUIRED:
S.No.
Item Description
Qty
8255PPI Interface board
Flat ribbon Cable
HARDWARE DESCRIPTION:
The Intel 8255A is a general purpose programmable I/O device which is designed for
parallel communication between microprocessors and peripheral devices. It provides
24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3
major modes of operation.
The 8255 allows the following three operating modes (Modes 0, 1 and 2):
Mode 0 - Simple I/O mode: Ports A and B operate as either inputs or

outputs and Port C is divided into two 4-bit groups either of which can be
operated as inputs or outputs.
Mode 1 Handshake I/O Mode: Same as Mode 0 but Port C is used for
handshaking and control.
Mode 2 Bidirectional I/O: Port A is bidirectional (both input and output)

and Port C is used for handshaking. Port B is not used.
In the given program, Port A is used for transmission and reception of parallel data
between the two microprocessor kits. Port A of 8255 interface in Tx end is selected in
Mode 0 Output mode and Port A of 8255 interface in Rx end is selected in Mode 0
Input mode.
Page 131
PSNCET
Page 132
PSNCET
The two microprocessor trainer kits are connected parallel through 8255 interface.
The Master program is stored in memory location 4100H of first trainer kit (TxTransmitter End) and Slave program is stored in the memory location 4100H of
second trainer kit (Rx-Receiver End).
Here Polling technique is used to send and receive the parallel data.
MASTER PROGRAM
ALGORITHM:
2. Initialize the mode format of 8255
3. Get the status to check whether transmitter is empty.
4. if not, Jump to step 3
5. Transmit the data stored in memory
6. Call delay routine
7. Check whether all data is transmitted. If not, jump to step 5
8. Stop the program
SLAVE PROGRAM
ALGORITHM:
2. Set the mode for 8255
3. Check whether the receiver is ready
4. Receive the data and store it in memory
5. Call delay routine
6. Check whether all data is received. If not, jump to step 4.
Page 133
PSNCET
MASTER PROGRAM (Tx):

Address
Opcode &
Operand
Label
Mnemonics
4100
3E, 82
MVI A, 82H
4102
D3, 0F
OUT 0FH
4104
3E, 3F
MVI A, 3FH
4106
D3, 0C
OUT 0CH
4108
DB, 0D
410A
D6, 3F
410C
C2, 08, 41
410F
0E, 08
4111
21, 00, 45
4114
7E
4115
D3, 0C
4117
CD, 50, 41
411A
23
INX H
411B
0D
DCR C
411C
C2, 14, 41
411F
CF
LOOP:
Comments
IN 0DH
SUI 3FH
JNZ LOOP
MVI C, 08H
LXI H, 4500H
TRANS:
MOV A, M
OUT 0CH
CALL DELAY
JNZ TRANS
RST1
DELAY Routine
4150
06, 05
MVI B, 05H
4152
1E, FF
LOOP2:
MVI E, FFH
4154
1D
LOOP1:
DCR E
4155
C2, 54, 41
4158
05
4159
C2, 52, 41
415C
C9
JNZ LOOP1
DCR B
JNZ LOOP2
RET
Page 134
PSNCET
PROCEDURE:
1. Load the master program in the transmitting end microprocessor kit.
2. Load the slave program in the receiver end microprocessor kit.
3. Load the block of data at memory location 4500H in the transmitting end kit.
4. Execute the slave program in the receiving end kit first.
5. Execute the master program in the transmitting end kit.
6. Check for the transfer of parallel data from Tx kit to Rx kit, by verifying the
data at location 4400H in the Rx kit.
OUTPUT:
MICROPROCESSOR KITS
Transmitter End (Tx)
Address
Data
Receiver End (Rx)

Address
4500
4400
4501
4401
4502
4402
4503
4403
4504
4404
4505
4405
4506
4406
4507
4407
Data
Page 135
PSNCET
SLAVE PROGRAM (Rx):
4100
Opcode &
Operand
3E, 90
4102
D3, 0F
4104
DB, 0C
4106
D6, 3F
4108
C2, 04, 41
JNZ CHECK
410A
3E, 3F
MVI A, 3FH
410C
D3, 0D
OUT 0DH
410F
0E, 08
MVI C, 08H
4111
CD, 50, 41
CALL DELAY
4114
21, 00, 44
LXI H, 4400H
4117
DB, 0C
4119
77
411A
CD, 50, 41
411D
23
INX H
411E
0D
DCR C
411F
C2, 17, 41
4122
CF
Address
Label
Mnemonics
Comments
MVI A, 90H
OUT 0FH
CHECK:
IN 0CH
SUI 3FH
RECV:
IN 0CH
MOV M, A
CALL DELAY
JNZ RECV
RST1
DELAY Routine:
4150
06, 05
MVI B, 05H
4152
1E, FF
LOOP2:
MVI E, FFH
4154
1D
LOOP1:
DCR E
4155
C2, 54, 41
4158
05
4159
C2, 52, 41
415C
C9
JNZ LOOP1
DCR B
JNZ LOOP2
RET
Note:
Remember to make the program in Rx end to get executed first and receiver end is
kept ready for reception of the parallel transmitted data.
RESULT:
Thus the program for parallel communication between two microprocessor kits using
8055 was executed and the results were verified.
Page 136
PSNCET
CONTROL FORMAT:
SC1
SC0
RL1
RL0
M2
M1
M0
BCD
Page 137
PSNCET
EX NO:
TITLE:
AIM:
Date: _________
PROGRAMMABLE INTERVAL TIMER - 8253
To write a program to study 8253 Timer and verify its modes of operation.
APPARATUS REQUIRED:
S.N o
Item Description
Qty
8253Programmable interval timer interface board
Flat ribbon Cable
CRO
Hardware Description:
The 8253 is a Programmable interval timer/counter. The 8253 includes three
identical 16-bit counters that can operate independently in any of the six modes. It
is PQC based in a 24 pin o/p and required a single +5v Power Supply. The 8254 is an
upgraded version of the 8253 and the pins are compatible.
The six different modes are:
MODE 0 - Interrupt on Terminal Count

When this mode is set, the output will be low. Loading the count register with a value
will cause the output to remain low and the counter will start counting down. When
the counter reaches 0 the output will go high and remain high until the counter is
reprogrammed. The counter will continue to count down after terminal count is
reached. Writing a value to the count register during counting will stop the counter,
writing a second byte starts the new count.
MODE 1 - Programmable One-Shot

The output will go low, once the counter has been loaded, and will go high once
terminal count has been reached. Once terminal count has been reached it can be
triggered again.
Page 138
PSNCET
MODE 2 - Rate Generator

It is a standard divide-by-N counter. The output will be low for one period of the
input clock then it will remain high for the time in the counter. This cycle will keep
repeating.
MODE 3 - Square Wave Rate Generator

Similar to mode 2, except the output will remain high until one half of the count has
been completed and then low for the other half.
MODE 4 - Software Triggered Strobe

After the mode is set the output will be high. Once the count is loaded it will start
counting, and will go low once terminal count is reached.
MODE 5 - Hardware Triggered Strobe

Hardware triggered strobe. Similar to mode 5, but it waits for a hardware trigger
signal before starting to count. Modes 1 and 5 require the 8253 gate pin to go high
in order to start counting.
----------------------------------------------------------------------------------------------MODE 0 - Interrupt on Terminal Count
Set the Channel 0 in Mode 0. Connect CLK0 to the debounce circuit and execute the
following program.
Address
Opcode &
Operand
Label
Mnemonics
4100
3E, 30
MVI A,30H
4102
D3, CE
OUT CEH
4104
3E, 05
MVI A,05H
4106
D3, C8
OUT C8H
4108
3E, 00
MVI A,00H
410A
D3, C8
OUT C8H
410C
76
Comments
Set Channel-0 in Mode-0
HLT
Load Lower byte of COUNT

to Counter
Load Higher byte of COUNT
to Counter
Stop the Program
Using a CRO, observe the output of Channel 0 is initially low. After giving six clock
pulses, we may notice that the output goes high.
Page 139
PSNCET
Mode-1 Programmable One Shot:

After loading the counter, the output will remain low following the rising edge of the
gate input. The output would go high on the terminal count. It is retriggered hence
the output will remain low for the full count after any rising edge of gate input.
Initialize channels of 8253 in mode 1 and also initiates triggering of gate-0 and 0
goes low clock pulse after triggering the gate and goes back to high level after file
clock pulses.
Address
Opcode &
Operand
Label
Mnemonics
START
MVI A, 32H
Comments
4100
3E, 32
4102
D3, CE
OUT CEH
4104
3E, 05
MVI A, 05H
4106
D3, C8
OUT C8H
4108
3E, 00
MVI A, 00H
410A
D3, C8
OUT C8H
Load MSB of Count

into Counter
41OC
D3, D0
OUT D0H
Triggers gate0
410E
76
HLT
Load LSB of Count

into Counter
Stop the program
Execute the grogram, give clock pulses through the denounce logic and verify using a
CRO.
Page 140
PSNCET
Mode-2: Rate Generator:

It is a simple divide by N counter. The output will be low for one period of the input
clock.
The period from one output pulse to the next, equals the number of input
counts in the count register. If the count register is reloaded between output pulses,
the present period will not be affected, but subsequent period will reflect the new
value.
Using mode 2, let us divide the clock pulse of the channel 1 by 10. Connect the CLK1
to PCLK.
Address
Opcode &
Operand
Label
Mnemonics
START
MVI A, 36H
4100
3E, 36
4102
D3, CE
OUT CEH
4104
3E, 0A
MVI A, 0AH
4106
D3, CA
OUT CAH
4108
3E, 00
MVI A, 00H
410A
D3, CA
OUT CAH
410C
76
Comments
HLT
Load Lower Byte of Count

To Counter
Load Higher byte of Count
To Counter
Stop the program
In a CRO, observe continuously the Input clock to Channel-1 and output at OUT-1
Page 141
PSNCET
OUTPUT:
Mode 0:
Input: 05 Clock pulse

Output: Goes HIGH, after 5 clock pulses.
Mode 1:
Input: 05 Clock pulse

Output: Shifted after 5 clock pulse and again shifted after 5 counts.
Mode 2:
Input: 05 Clock pulse, Clock 4th Pin, grounded 10th Pin.

Output: Toggled after 5th clock pulse and this is repeated.
INPUT CLOCK
TIMER OUTPUT
Amplitude
Amplitude
Time Period
Time Period
RESULT:
Thus the program for interface of programmable timer was executed and the outputs
were verified.
Page 142
PSNCET
APPENDIX A
8085 OPCODE SHEET
Page 143
PSNCET
Page 144
PSNCET
8086 OPCODE SHEET
DATA TRANSFER:
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
AX, [a16]
[a16], AX
AX, DX
AL, d8
AH, d8
[a16], AL
[a16], AH
AL, AH
AH, AL
BP, AX
A1, ___, ___

A3, ___, ___
8B, C2
B0, ___
B4, ___
A2, ___, ___
88, 26, ___, ___
8A, C4
88, C4
8B, E8
MOV
MOV
MOV
MOV
BX, d16
BL, d8
BH, d8
[BX], DX
BB, ___, ___

B3, ___
B7, ___
89, 17
MOV
MOV
MOV
MOV
CX, d16
CL, d8
CH, d8
CX, DI
B9,
B1,
B5,
8B,
___, ___
___
___
CF
MOV [a16], DX
MOV DX, [a16]
MOV DX, d16
87, 16, ___, ___

8B, 16, ___, ___
BA, ___, ___
MOV SI, AX
MOV SI, d16
MOV DI, d16
8B, F0
BE, ___, ___
BF, ___, ___
I/O:
OUT a8, AL
IN AL, a8
E6, a8
E4, a8
ARITHMETIC:
ADD AL, d8
ADD AX, [a16]
ADC AX, [a16]
04, ___
03, 06, ___, ___
13, 06, ___, ___
SUB AX, [a16]

SBB AX, [a16]
SUB AL, d8
2B, 06, ___, ___

1B, 06, ___, ___
2C, ___
MUL [a16]
DIV [a16]
DAA
F7, 26, ___, ___

F7, 36, ___, ___
Page 145
PSNCET
INC BX
INC AL
INC SI
INC DI
43
FE, C0
46
47
DEC BL
DEC CH
DEC CX
FE, CB
FE, CD
49
LOGICAL:
AND AL, d8
AND AX, d16
AND AH, BL
24, ___
25, ___, ___
22, E3
OR AX, d16
OR BL, BH
OR AL, AH
0D, ___, ___

0A, DF
0A, C4
XOR AL, AL
30, C0
NOT AX
CMP AH, AL
F7, A0
38, C4
STRING MANIPULATION
MOVSB
STOSB
CLD
STD
CLI
STI
A4
AA
FC
FD
FA
FB
ITERATION CONTROL
LOOP rel
E2, rel_
EXT H/W SYNCHRONIZATION:

NOP
HLT
90
F4
BRANCHING:
JMP rel
JNC rel
JNZ rel
JZ rel
EB,
73,
75,
74,
rel_
rel_
rel_
rel_
CALL [a16]
RET
E8, ___, ___

C3
Page 146
PSNCET
8051 OPCODE SHEET
Page 147
PSNCET
Page 148
PSNCET
Note:
Data Addr refers to 8-bit (direct) address of Internal RAM memory location / SFR
Code Addr refers to 8-bit relative addressing from the current location
Page 149
PSNCET
APPENDIX B
PROGRAMMING STEPS in Microprocessor Kit:
A. To Store program / Data:

<Res>
<Sub>
<...16-bit address...>
Starting address of memory where data /

Program is to be stored
<Next>
<...Enter the 8-bit data / opcode...>
<Next>
Keep repeating the last two steps until entire data / Program is stored.
B. To Execute the stored program:

<Res>
<Go>
Starting address of memory where data /
Program is stored
<Exec>
A display of letter E in the trainer kit indicates the successful execution of
the program in the kit.
C. To view the Opcode / Data / Result:

<Res>
<Sub>
Address of memory where data is stored
<Next>
Keep pressing <Next> key to view data in subsequent locations.
Page 150

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PSNCET

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

PSN COLLEGE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

Analog to Digital/ Digital to Analog

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

MICROPROCESSOR AND MICROCONTROLLER LABORATORY

Program for 8 bit Arithmetic operation using 8085

(a) Program for 16 bit Arithmetic operation using 8085

(b) Program for 16 bit Arithmetic operation using 8086

(a) Program for sorting and searching using 8085

(b) Program for sorting and searching using 8086

Program for String manipulation operation using 8086

Programming using Arithmetic, Logical and bit manipulation instructions of

Program for sorting and searching using 8051

Code conversion using 8051.

Analog to Digital/ Digital to Analog

Interfacing and programming of stepper motor control

10. Communication between 8051 Microcontroller and PC

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

Aim: To study the working of Intel 8085 Microprocessor trainer kit.

Figure 1.1 Vimicros Micro-85 Microprocessor kit

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

: 2000 - 3FFF & COOO - FFFF

Monitor Data Area

: 4000 - 40FF (Reserved)

User RAM Area

: One number of RS232C compatible Serial interface

Timer : Three channel 16-bit Programmable Timer using 8253.

6) AUDIO CASSETTE INTERFACE with file management.

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

8) HARDWARE SINGLE STEP:

9) SYSTEM POWER CONSUMPTION:

10) POWER SUPPLY SPECIFICATIONS: [External ]

11) PHYSICAL CHARACTERISTICS:

12) TEST POINTS: Test points provided

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

1.2.2 SOFTWARE SPECIFICATIONS

Maskable interrupt connected to CPU's RST 7.5 interrupt.

Decrement the address by one and display it contents

Execute a particular program after selecting the address

Increment address by one and display its contents

NOTE: The Hex-key function summary below is in the order:

MICROPROCESSOR AND MICROCONTROLLER LAB MANUAL

Hex key entry "0"

i. Hex key entry "1"

ii. Examine the 8085A registers and modify the same.

i. Hex key entry "2"

ii. Writes data from memory on to audiotape.

ii. Retrieve data from an audiotape to memory.

iii. Register key "C"

Hex key entry 3

iii. Register key B

Hex key entry 4.

ii. Block search for a byte.

Hex key entry 5.

ii. Fill a block of RAM memory with desired data.