WHOLE BRAIN LEARNING SYSTEM

OUTCOME -BASED EDUCATION

Science, Technology and Engineering (STE) Program
GRADE

ELECTRONICS 10

LEARNING QUARTER 2

MODULE WEEK 3

WBLS-OBE MELC-Aligned Self-Learning Module Electronics (Grade 10)

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 MODULE IN ELECTRONICS
Science, Technology and Engineering
(STE) Program

QUARTER 2
WEEK 3

ELECTRONIC TIMER

Development Team

Writer: Richard F. Aison

Editor: Ponciano S. Raspado

Reviewer: Hamilton C. Remigio

Management Team: Vilma D. Eda, CESO V

Joye D. Madalipay Arnel S. Bandiola

Juanito V. Labao Flenie A. Galicinao

WBLS-OBE MELC-Aligned Self-Learning Module Electronics (Grade 10)

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 What I Need to Know

This module in Electronics contains information and suggested learning activities

that provides you understanding on the knowledge, skills and desirable attitudes required in
assembling consumer electronic products and systems.

In order to benefit much from this module, you should learn the different electronic
timers You should also be able to learn the difference between Electronic Counters, Digital
Registers and Semiconductor Memories.

Most Essential Learning Competencies

1. Discuss about Counters

2. Discuss about Registers

3. Discuss about Memories

Learning Objectives:

1. Discuss different types of Electronic Counters

2. Describe the four modes of operation of a Digital Registers

3. Discuss different types of Semiconductor Memories

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 What I Know

Pre-Test
Directions: Choose the letter of the correct answer and write it on a sheet of paper. Do not
write anything on this module.

1. It is a sequential logic circuit which has a clock input signal and a group of output signals
that represent an integer "counts" value.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

2. It is a group of flip-flop use to increase the storage capacity in terms of number of bits.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

3. It is a digital electronic device used for digital data storage, such as computer memory.

A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

4. It is a 1-bit memory cell which can be used for storing the digital data.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory
5. It is more compact and also more complex than electro-mechanical timers.
A. Electronic Timer B. Electronic Timex
C. Electromagnetic Timer D. Electromagnetic Timex

What’s In

Activity 1
ACRONYMS
Direction: Give the complete meaning of the following acronyms. Write your answers on a
separate sheet of paper.
1. SISO -
2. SIPO -
3. PISO -
4. PIPO -
5. RAM -

What’s New
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 Introduction to Electronic Timers

An electronic timer is more compact and also more complex than electro-
mechanical timers. If feedback/output control functions are required (in terms of an alarm or
another pre-programmed event), an electronic timer is a better fit than an electro-
mechanical timer. Each electronic timer offers digital programmability. Within a computer,
information is represented and stored in a digital binary format. The term bit is an
abbreviation of binary digit and represents the smallest piece of data. Humans interpret
words and pictures; computers interpret only patterns of bits.

Figure 1. Electronic Timers

Source: www.specialtyproducttech

What is It

Lesson
ELECTRONIC COUNTERS
1
An electronic counter is a sequential logic circuit which has a clock input signal and a
group of output signals that represent an integer "counts" value. Upon each qualified clock
edge, the circuit will increment (or decrement, depending on circuit design) the counts.
When the counts have reached the end of the counting sequence (maximum counts when
incrementing; zero counts when decrementing), the next clock will cause the counts to
overflow or underflow and the counting sequence will start over. Internally, counters use flip-
flops to represent the current counts and to retain the counts between clocks. Depending on
the type of counter, the output may be a direct representation of the counts (a binary
number) or it may be encoded. Examples of the latter include ring counters and counters
that output Gray codes.

Many counters provide additional input signals to facilitate dynamic control of the
counting sequence, such as:

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 Reset - sets counts to zero. Some IC manufactures name it "clear" or "master reset
(MR)".
 Enable - allows or inhibits counting.
 Direction - determines whether counts will increment or decrement.
 Data - parallel input data which represents a particular counts value.
 Load - copies parallel input data to the counts.
Some counters provide a Terminal Count output which indicates that the next clock
will cause overflow or underflow. This is commonly used to implement counter cascading
(combining two or more counters to create a single, larger counter), by connecting the
Terminal Count output of one counter to the Enable input of the next counter.
The modulus of a counter is the number of states in its count sequence. The
maximum possible modulus is determined by the number of flip-flops. For example, a four-
bit counter can have a modulus of up to 16 (2^4).
Counters are generally classified as either synchronous or asynchronous. In
synchronous counters, all flip-flops share a common clock and change state at the same
time. In asynchronous counters, each flip-flop has a unique clock and the flip-flop states
change at different times.
Synchronous counters are categorized in various ways. For example:

 Modulus counter - counts through a particular number of states.

 Decade counter – modulus 10 counter (counts through ten states).
 Up/down counter – counts both up and down, as directed by a control input.
 Ring counter – formed by a "circular" shift register.
 Johnson counter – a twisted ring counter.
 Gray code counter - outputs a sequence of Gray codes.
Counters are implemented in a variety of ways, including as
dedicated MSI and LSI integrated circuits, as embedded counters within ASICs, as general-
purpose counter and timer peripherals in microcontrollers, and as IP blocks in FPGAs.
Asynchronous (ripple) counter

Figure 2. Asynchronous counter created from two JK flip-flops

An asynchronous (ripple) Source: wikipedia
counter is encyclopedia
a "chain" of toggle (T) flip-flops wherein the
least-significant flip-flop (bit 0) is clocked by an external signal (the counter input clock) and
all other flip-flops are clocked by the output of the nearest, less significant flip-flop (e.g., bit 0
clocks the bit 1 flip-flop, bit 1 clocks the bit 2 flip-flop, etc.). The first flip-flop is clocked by

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rising edges; all other flip-flops in the chain are clocked by falling clock edges. Each flip-flop
introduces a delay from clock edge to output toggle, thus causing the counter bits to change
at different times and producing a ripple effect as the input clock propagates through the
chain. When implemented with discrete flip-flops, ripple counters are commonly
implemented with JK flip-flops, with each flip-flop configured to toggle when clocked (i.e., J
and K are both connected to logic high).

In the simplest case, a one-bit counter consists of a single flip-flop. This counter will
increment (by toggling its output) once per clock cycle and will count from zero to one before
overflowing (starting over at zero). Each output state corresponds to two clock cycles, and
consequently the flip-flop output frequency is exactly half the frequency of the input clock. If
this output is then used as the clock signal for a second flip-flop, the pair of flip-flops will form
a two-bit ripple counter with the following state sequence:

Clock
Q1 Q0 (Q1:Q0) decimal
cycle

0 0 0 0

1 0 1 1

2 1 0 2

3 1 1 3

4 0 0 0

Additional flip-flops may be added to the chain to form counters of any arbitrary word
size, with the output frequency of each bit equal to exactly half the frequency of the nearest,
less significant bit.

Ripple counters exhibit unstable output states while the input clock is propagating
through the circuit. The duration of this instability (the output settling time) is proportional to
the number of flip-flops. This makes ripple counters unsuitable for use in synchronous
circuits that require the counter to have a fast output settling time. Also, it is often impractical
to use ripple counter output bits as clocks for external circuits because the ripple effect
causes timing skew between the bits. Ripple counters are commonly used as general-
purpose counters and clock frequency dividers in applications where the instantaneous
count and timing skew is unimportant.
Synchronous counter

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 Figure 3. A 4-bit synchronous counter using JK flip-flops
Source: wikipedia encyclopedia
In a synchronous counter, the clock inputs of the flip-flops are connected together
and all flip-flops are simultaneously triggered by the common clock. Consequently, all of the
flip-flops change state at the same time (in parallel).
For example, the circuit shown to the right is an ascending (up-counting) four-bit
synchronous counter implemented with JK flip-flops. Each bit of this counter is allowed to
toggle when all of the less significant bits are at a logic high state. Upon clock rising edge, bit
1 toggles if bit 0 is logic high; bit 2 toggles if bits 0 and 1 are both high; bit 3 toggles if bits 2,
1 and 0 are all high.

Decade counter

Figure 4. A circuit decade counter using JK Flip-flops (74LS112D)

Source: wikipedia encyclopedia
A decade counter is one that counts in decimal digits, rather than binary. A decade
counter may have each (that is, it may count in binary-coded decimal, as the 7490 integrated
circuit did) or other binary encodings. A decade counter is a binary counter that is designed
to count to 1010 (decimal 10). An ordinary four-stage counter can be easily modified to a
decade counter by adding a NAND gate as in the schematic to the right. Notice that FF2 and
FF4 provide the inputs to the NAND gate. The NAND gate outputs are connected to the CLR

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input of each of the FFs. It counts from 0 to 9 and then resets to zero. The counter output
can be set to zero by pulsing the reset line low. The count then increments on each clock
pulse until it reaches 1001 (decimal 9). When it increments to 1010 (decimal 10) both inputs
of the NAND gate go high. The result is that the NAND output goes low, and resets the
counter to zero. D going low can be a CARRY OUT signal, indicating that there has been a
count of ten.

Ring counter
A ring counter is a circular shift register which is initiated such that only one of its flip-
flops is the state one while others are in their zero states.
A ring counter is a shift register (a cascade connection of flip-flops) with the output of
the last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting
of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used.

Johnson counter
A Johnson counter (or switch-tail ring counter, twisted ring counter, walking ring
counter, or Möbius counter) is a modified ring counter, where the output from the last stage
is inverted and fed back as input to the first stage. The register cycles through a sequence of
bit-patterns, whose length is equal to twice the length of the shift register, continuing
indefinitely. These counters find specialist applications, including those similar to the decade
counter, digital-to-analog conversion, etc. They can be implemented easily using D- or JK-
type flip-flops.

Lesson
DIGITAL REGISTERS
2
Flip-flop is a 1-bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, we have to use a group of flip-flop.
Such a group of flip-flop is known as a Register. The n-bit register will consist of n number
of flip-flop and it is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers. There
are four mode of operations of a shift register.

 Serial Input Serial Output

 Serial Input Parallel Output
 Parallel Input Serial Output
 Parallel Input Parallel Output

Serial Input Serial Output (SIS0)

Let all the flip-flop be initially in the reset condition i.e. Q 3 = Q2 = Q1 = Q0 = 0. If an
entry of a four-bit binary number 1 1 1 1 is made into the register, this number should be
WBLS-OBE MELC-Aligned Self-Learning Module Electronics (Grade 10)
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applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D 3 is connected to
serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e.
D2 and so on.

Din
D3 Q3 D2 Q2 D1 Q1 D0 Q0

Figure 5. Block Diagram of Serial Input Series Output (SISO)

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm
Operation

Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the
number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of
clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.
Din
D3 Q3 D2 Q2 D1 Q1 D0 Q0

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm
Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock
hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.
Din
D3 Q3 D2 Q2 D1 Q1 D0 Q0

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm

Apply the next bit to be stored i.e. 1 to D in. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

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 Din
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Output

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm

Similarly, with Din = 1 and with the fourth negative clock edge arriving, the stored
word in the register is Q3 Q2 Q1 Q0 = 1111.

Din
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Output

CLK

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm

Truth Table

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 Waveforms

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Serial Input Parallel Output (SIPO)

 In such types of operations, the data is entered serially and taken out in parallel
fashion.
 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
 As soon as the data loading gets completed, all the flip-flops contain their required
data, the outputs are enabled so that all the loaded data is made available over all
the output lines at the same time.
 4 clock cycles are required to load a four bit word. Hence the speed of operation of
SIPO mode is same as that of SISO mode.

Din D3 Q3 D2 Q2 D1 Q1 D0 Q0

Q3 Q2 Q1 Q0

Figure 6. Block Diagram of Serial Input Parallel Output (SIPO)

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm
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Parallel Input Serial Output (PISO)

 Data bits are entered in parallel fashion.

 The circuit shown below is a four-bit parallel input serial output register.
 Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
 The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
 There are two modes in which this circuit can work namely - shift mode or load
mode.

Load mode

When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they
will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the
binary input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel
loading takes place.

Shift mode

When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive.
Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5
become active. Therefore, the shifting of data from left to right bit by bit on application of
clock pulses. Thus the parallel in serial out operation takes place.

Block Diagram

B0 B1 B2 B3

D0 Q0 D1 Q1 D2 Q2 D3 Q3

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm
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Parallel Input Parallel Output (PIPO)

In this mode, the 4-bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1,
D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the
input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.

B3 B2 B1 B0

D3 Q3 D2 Q2 D1 Q1 D0 Q0

Q3 Q2 Q1 Q0

Figure 7. Block Diagram of Parallel Input Parallel Output (PIPO)

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Bidirectional Shift Register

 If a binary number is shifted left by one position, then it is equivalent to multiplying

the original number by 2. Similarly, if a binary number is shifted right by one position
then it is equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
 Such a register is called bi-directional register. A four-bit bi-directional shift register is
shown in fig.
 There are two serial inputs namely the serial right shift data input DR, and the serial
left shift data input DL along with a mode select input (M).

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 Block Diagram

DR

DL

D3 Q3 D2 Q2 D1 Q1 D0 Q0

Source: https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm

Operation

S.N Condition Operation

.

1 With M = 1 − Shift right operation

If M = 1, then the AND gates 1, 3, 5 and 7 are
enabled whereas the remaining AND gates 2, 4, 6
and 8 will be disabled.
The data at DR is shifted to right bit by bit from FF-3
to FF-0 on the application of clock pulses. Thus
with M = 1 we get the serial right shift operation.

2 With M = 0 − Shift left operation

When the mode control M is connected to 0 then
the AND gates 2, 4, 6 and 8 are enabled while 1, 3,
5 and 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to
FF-3 on the application of clock pulses. Thus with
M = 0 we get the serial right shift operation.

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Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional
shift register. A shift register which can shift the data in both directions is called a bi-
directional shift register. Applying the same logic, a shift register which can shift the data in
both directions as well as load it parallely, is known as a universal shift register. The shift
register is capable of performing the following operation −

 Parallel loading
 Left Shifting
 Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas
it is connected to 0 for serial shifting. With mode control pin connected to ground, the
universal shift register acts as a bi-directional register. For serial left operation, the input is
applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift
right operation, the serial input is applied to D input.

Block Diagram

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 Lesson
SEMICONDUCTOR MEMORIES
3
Semiconductor memory is a digital electronic semiconductor device used for digital
data storage, such as computer memory. It typically refers to MOS memory, where data is
stored within metal–oxide–semiconductor (MOS) memory cells on a silicon integrated
circuit memory chip. There are numerous different types using different semiconductor
technologies. The two main types of random-access memory (RAM) are static
RAM (SRAM), which uses several MOS transistors per memory cell, and dynamic
RAM (DRAM), which uses a single MOS transistor and MOS capacitor per cell. Non-volatile
memory (such as EPROM, EEPROM and flash memory) uses floating-gate memory cells,
which consist of a single floating-gate MOS transistor per cell.

Most types of semiconductor memory have the property of random access, which

means that it takes the same amount of time to access any memory location, so data can be
efficiently accessed in any random order. This contrasts with data storage media such
as hard disks and CDs which read and write data consecutively and therefore the data can
only be accessed in the same sequence it was written. Semiconductor memory also has
much faster access times than other types of data storage; a byte of data can be written to
or read from semiconductor memory within a few nanoseconds, while access time for
rotating storage such as hard disks is in the range of milliseconds. For these reasons it is
used for main computer memory (primary storage), to hold data the computer is currently
working on, among other uses.

As of 2017, semiconductor memory chips sell $124 billion annually, accounting for

30% of the semiconductor industry. Shift registers, processor registers, data buffers and
other small digital registers that have no memory address decoding mechanism are typically
not referred to as "memory" although they also store digital data.

In a semiconductor memory chip, each bit of binary data is stored in a tiny circuit

called a memory cell consisting of one to several transistors. The memory cells are laid out
in rectangular arrays on the surface of the chip. The 1-bit memory cells are grouped in small
units called words which are accessed together as a single memory address. Memory is
manufactured in word length that is usually a power of two, typically N=1, 2, 4 or 8 bits.

Data is accessed by means of a binary number called a memory address applied to

the chip's address pins, which specifies which word in the chip is to be accessed. If the
memory address consists of M bits, the number of addresses on the chip is 2M, each
containing an N bit word. Consequently, the amount of data stored in each chip
is N2M bits. The memory storage capacity for M number of address lines is given by 2M,
which is usually in power of two: 2, 4, 8, 16, 32, 64, 128, 256 and 512 and measured
in kibibits, mebibits, gibibits or tebibits, etc. As of 2014 the largest semiconductor memory
chips hold a few gibibits of data, but higher capacity memory is constantly being developed.
By combining several integrated circuits, memory can be arranged into a larger word length

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and/or address space than what is offered by each chip, often but not necessarily a power of
two.

The two basic operations performed by a memory chip are "read", in which the data
contents of a memory word are read out (nondestructively), and "write" in which data is
stored in a memory word, replacing any data that was previously stored there. To increase
data rate, in some of the latest types of memory chips such as DDR SDRAM multiple words
are accessed with each read or write operation.

In addition to standalone memory chips, blocks of semiconductor memory are

integral parts of many computer and data processing integrated circuits. For example,
the microprocessor chips that run computers contain cache memory to store instructions
awaiting execution.

Types
Volatile Memory

Figure 1. Volatile Memory

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Ram chips for computers usually come on removable memory module like these.
Additional memory can be added to the computer by plugging in additional modules.

Volatile memory loses its stored data when the power to the memory chip is turned
off. However, it can be faster and less expensive than non-volatile memory. This type is
used for the main memory in most computers, since data is stored on the hard disk while the
computer is off. Major types are.

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RAM (Random-access memory) – This has become a generic term for any semiconductor
memory that can be written to, as well as read from, in contrast to ROM (below), which can
only be read. All semiconductor memory, not just RAM, has the property of random access.

 DRAM (Dynamic random-access memory) – This uses metal–oxide–

semiconductor (MOS) memory cells consisting of one MOSFET (MOS field-effect
transistor) and one MOS capacitor to store each bit. This type of RAM is the cheapest
and highest in density, so it is used for the main memory in computers. However,
the electric charge that stores the data in the memory cells slowly leaks out, so the
memory cells must be periodically refreshed (rewritten) which requires additional
circuitry. The refresh process is handled internally by the computer and is transparent to
its user.

 FPM DRAM (Fast page mode DRAM) – An older type of asynchronous DRAM that
improved on previous types by allowing repeated accesses to a single "page" of
memory to occur at a faster rate. Used in the mid-1990s.

 EDO DRAM (Extended data out DRAM) – An older type of asynchronous

DRAM which had faster access time than earlier types by being able to initiate a new
memory access while data from the previous access was still being transferred.
Used in the later part of the 1990s.

 VRAM (Video random access memory) – An older type of dual-

ported memory once used for the frame buffers of video adapters (video cards).

 SDRAM (Synchronous dynamic random-access memory) – This added

circuitry to the DRAM chip which synchronizes all operations with a clock signal
added to the computer's memory bus. This allowed the chip to process multiple
memory requests simultaneously using pipelining, to increase the speed. The data
on the chip is also divided into banks which can each work on a memory operation
simultaneously. This became the dominant type of computer memory by about the
year 2000.

 DDR SDRAM (Double data rate SDRAM) – This could transfer twice

the data (two consecutive words) on each clock cycle by double
pumping (transferring data on both the rising and falling edges of the clock
pulse). Extensions of this idea are the current (2012) technique being used to
increase memory access rate and throughput. Since it is proving difficult to
further increase the internal clock speed of memory chips, these chips increase
the transfer rate by transferring more data words on each clock cycle
 DDR2 SDRAM – Transfers 4 consecutive words per internal
clock cycle
 DDR3 SDRAM – Transfers 8 consecutive words per internal
clock cycle.
 DDR4 SDRAM – Transfers 16 consecutive words per internal
clock cycle.

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  RDRAM (Rambus DRAM) – An alternate double data rate memory
standard that was used on some Intel systems but ultimately lost out to DDR
SDRAM.
 XDR DRAM (Extreme data rate DRAM)

 SGRAM (Synchronous graphics RAM) – A specialized type of SDRAM

made for graphics adaptors (video cards). It can perform graphics-related
operations such as bit masking and block write, and can open two pages of
memory at once.
 GDDR SDRAM (Graphics DDR SDRAM)
 GDDR2
 GDDR3 SDRAM
 GDDR4 SDRAM
 GDDR5 SDRAM
 GDDR6 SDRAM

 HBM (High Bandwidth Memory) – A development of SDRAM used in
graphics cards that can transfer data at a faster rate. It consists of multiple
memory chips stacked on top of one another, with a wider data bus.

 PSRAM (Pseudostatic RAM) – This is DRAM which has circuitry to

perform memory refresh on the chip, so that it acts like SRAM, allowing the external
memory controller to be shut down to save energy. It is used in a few game
consoles such as the Wii.

 SRAM (Static random-access memory) – This stores each bit of data in a circuit

called a flip-flop, made of 4 to 6 transistors. SRAM is less dense and more expensive per
bit than DRAM, but faster and does not require memory refresh. It is used for
smaller cache memories in computers.

 CAM (Content-addressable memory) – This is a specialized type in which, instead of
accessing data using an address, a data word is applied and the memory returns the
location if the word is stored in the memory. It is mostly incorporated in other chips such
as microprocessors where it is used for cache memory.

What’s More

It is common to connect shift register ICs in cascade, using the serial output of one
register to connect to the serial input of the next register in the chain. For this reason, both
the data and clock inputs and outputs of register ICs are normally buffered.

Some examples from the many commercially available IC registers using these and
similar methods, available in both CMOS and TTL versions, are listed below.

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  74HC164 8-Bit SIPO Shift register from NXP
 74HC594 8-Bit SIPO/SISO with PIPO output storage register and dual clocks -
from NXP.
 74HC595 8-Bit SIPO/SISO with tri-state output PIPO storage register and dual clocks
- from NXP.
 HEF4014B PISO Register with 8-bit synchronous parallel LOAD and outputs from
Q5, Q6 & Q7 only - from NXP.
 CD4031B 64 Stage SISO shift register with re-circulation mode - from Texas
Instruments.

What I Have Learned

Difference between Register and Memory:

Register Memory

Memory holds the instructions and the data

Registers hold the operands or instruction that the currently executing program in
that CPU is currently processing. CPU requires.

Register holds the small amount of data Memory of the computer can range from
around 32-bits to 64-bits. some GB to TB.

CPU can operate on register contents at

the rate of more than one operation in one CPU accesses memory at the slower rate
clock cycle. than register.

Types are Accumulator register, Program

counter, Instruction register, Address
register, etc. Type of memory are RAM,etc.

Registers can be control i.e. you can store

and retrieve information from them. Memory is almost not controllable.

Registers are faster than memory. RAM is much slower than registers.

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 What I Can Do

I. CREATIVE CONSTRUCTED RESPONSE TEST ITEM (20 Points)

LEARNING COMPETENCY: 1. Discuss about Counters

2. Discuss about Registers

3. Discuss about Memories

OBJECTIVES:

1. Discuss different types of Electronic Counters

2. Describe the four modes of operation of a Digital Registers

3. Discuss different types of Semiconductor Memories

SITUATION: Chadz wanted to familiarize himself with the 4 block diagrams for the different
mode of operations of a shift register, he wanted you to draw and label the 4
block diagrams for the different mode of operations of a shift register on long
bond paper.

Master Qualified Apprentice Novice Points

Standard Artist Artist Artist Artist Earned
50% 40% 30% 20%
Art Skill All block Only 3 block Only 2 block Only 1 block
(50%) diagrams for diagrams for diagrams for diagrams for
different different different mode different
mode of mode of of operations mode of
operations of operations of of a shift operations of
a shift register a shift register register are a shift register
are drawn are drawn drawn and is drawn and
and label and label label correctly label correctly
correctly correctly
Craftmanship Presents all Present most Present some Present work
(50%) work neatly work neatly work neatly with little
neatness

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 Assessment

POST TEST

Directions: Choose the letter of the correct answer and write it on a sheet of paper. Do not
write anything on this module.

1. It is a 1-bit memory cell which can be used for storing the digital data.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory
2. It is more compact and also more complex than electro-mechanical timers.
A. Electronic Timer B. Electronic Timex
C. Electromagnetic Timer D. Electromagnetic Timex

3. It is a sequential logic circuit which has a clock input signal and a group of output signals
that represent an integer "counts" value.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

4. It is a group of flip-flop use to increase the storage capacity in terms of number of bits.
A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

5. It is a digital electronic device used for digital data storage, such as computer memory.

A. Digital Registers B. Electronic Counters
C. Flip-Flop D. Semiconductor Memory

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 Answer Key

PRE-ASSESSMENT POST-ASSESSMENT
1. B 1. C
2. A 2. A
3. D 3. B
4. C 4. A
5. A 5. D

ACTIVITY 1
1. SERIAL INPUT SERIAL OUTPUT
2. SERIAL INPU PARALLEL OUTPUT
3. PARALLEL INPUT SERIAL OUTPUT
4. PARALLEL INPUT PARALLEL OUTPUT
5. RANDOM ACCESS MEMORY

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References

www.specialtyproducttech

Wikipedia encyclopedia

https://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm

- Grob, Bernard. Grob Basic Electronics, 7th Edition; New York: Mc Graw-Hill Book
Company: 1993

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 For inquiries or feedback, please write or call:

Department of Education – Schools Division of Laoag City

Curriculum Implementation Division
Brgy. 23 San Matias, Laoag City, 2900
Contact Number: (077)-771-3678
Email Address: [email protected]

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