EC6303 - Linear Integrated Circuits and Applications Notes

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Linear IC’s and Applications 10EE56
LINEAR IC’S AND APPLICATIONS

Subject Code : 10EE56 Total No. of Lecture Hrs. : 52 Exam Marks : 100
PART -A
UNIT -1 OP-AMPS AS AC AMPLIFIER: Capacitor coupled voltage follower, high
Zin capacitor coupled voltage follower, capacitor coupled non-inverting amplifier, high
Zin capacitor coupled non-inverting amplifier, capacitor coupled inverting amplifier,
setting upper cut off frequency, capacitor coupled difference amplifier, and use of single
polarity supply.6 Hours
UNIT 2 OP-AMPS FREQUENCY RESPONSE AND COMPENSATION: Op amp
circuits stability, frequency and phase response, frequency compensating methods
,manufacturer’s recommended compensation, opamp circuit band width, slew rate
effects,stray capacitance effects, load capacitance effects, Zin mode compensation, circuit
stability precautions.7 Hours
UNIT -3 SIGNAL PROCESSING CIRCUITS: Precision half wave & full wave
rectifiers, limiting circuits, clamping circuits, peak detectors, sample &hold circuit. DAC
and ADC (Flash and successive approximations) 7 Hours
UNIT -4 OPAMPS AND NONLINEAR CIRCUITS: Op-amps in switching circuits,
zero crossing detectors, inverting Schmitt trigger circuits, non-inverting Schmitt circuits,
astable multivibrator, and monostable multivibrator. 6 Hours
PART -B
UNIT -5 SIGNAL GENERATOR: Triangular/rectangular wave generator, waveform
generator design, phase shift oscillator, oscillator amplitude stabilization, Wein bridge
oscillator, signal generators, output controllers 7 Hours
UNIT -6 ACTIVE FILTERS: First and second order high pass and low pass filters,
band pass filter, band stop filter. 7 Hours
UNIT -7 SPECIALIZED IC APPLICATIONS: Universal active filter, switched
capacitor filter, phase locked loops, power amplifiers. 6 Hours
UNIT -8 DC VOLTAGE REGULATORS: Voltage regulators basics, voltage follower
regulator, adjustable output regulator, precision voltage regulators, and integrated circuit
voltage regulators. 6 Hours
TEXT BOOKS:
1. Operational amplifiers and linear IC’s, David A Bell, Oxford University Press, 2010.
2. Operational amplifiers and linear IC’s, Ramakanth A Gayakwad, PHI, 4th edition,2009. 3. Linear
integrated circuits,S.P.Bali,TMH,2009.
REFERENCE BOOKS:
1. Op Amps and Linear Integrated Circuits-Concepts and Applications, James M.Fiore,Cengage
Learing,2009.
2. Op Amps, Design, Applications and Trouble Shooting,Elsevier,2nd Edition.
3. Operational amplifiers and linear IC’s, Stanley William D, -4th edition, Pearson Education.
4. Linear Integrated Circuits-Analysis,Design and Applications,B.Somanathan Nair, Wiley India,
First,Edition, 2009.
Contents:
Department Of EEE, SJBIT Page 1
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Contents
Sl.no Chapters Page no.

1 OP-AMPS AS AC AMPLIFIER 3 to 20
2 OP-AMPS FREQUENCY RESPONSE AND 21 to 42
COMPENSATION
3 SIGNAL PROCESSING CIRCUITS 43 to 55

4 OPAMPS AND NONLINEAR CIRCUITS 56 to 68
5 SIGNAL GENERATOR 69 to 82
6 Active filters 83 to 101
7 SPECIALIZED IC APPLICATIONS 102 to 123
8 DC voltage regulator 124 to 132
UNIT -1
OP-AMPS AS AC AMPLIFIER
Capacitor coupled voltage follower

high Zin capacitor coupled voltage follower
capacitor coupled non-inverting amplifier
high Zin capacitor coupled non-inverting amplifier
capacitor coupled inverting amplifier
setting upper cut off frequency
capacitor coupled difference amplifier
use of single polarity supply
Need for analog circuitry: To understand and obtain the best performance of a system,
designers need to understand the principles of both analog and digital world.
DATA ACQUISITION SYSYTEM BLOCK DIAGRAM:
Input stage
Intermediate stage
Level shifting stage
Output stage
INPUT STAGE:
Dual input, balanced output differential amplifier.
Provides voltage gain and establishes the input resistance of the op-amp.
INTERMEDIATE STAGE:
Dual input, unbalanced output differential amplifier.
It is driven by the first stage.
LEVEL SHIFTING STAGE:
The output of the differential amplifier is directly coupled to the input of the intermediate
level shifter stage.
It is used after the intermediate stage to shift the DC level at the output of the
intermediate.
This stage has the circuit, called level translator circuit.
OUTPUT STAGE:
It is a complementary symmetry push-pull amplifier.
Raises the output voltage swing and current capability of the op-amp.
Provides low output impedance.
An Operational Amplifier, or Op Amp, is a dual-input, single-output linear

amplifier that exhibits a high open-loop gain, high input resistances, and a low
output resistance. One of the inputs of an operational amplifier amp is non-
inverting while the other is inverting. The output Vout of an operational amplifier
without feedback (also known as open-loop) is given by the formula: Vout =
A(Vp-Vn) where A is the open-loop gain of the op amp, Vp is the voltage at the
non-inverting input, and Vn is the voltage at the inverting input. The open-loop
gain of a typical op amp is in the range of 105-106.
The operational amplifier got its name from the fact that it can be configured to
perform many different mathematical operations. Depending on its feedback
circuit and biasing, an op amp can be made to add, subtract, multiply, divide,
negate, and, interestingly, even perform calculus operations such as differentiation
and integration. Of course, aside from these operations, op amps are also found in
a very large number of applications. In fact, many consider the op amp as the
foundation of many analog semiconductor products today.
Because of the very high resistance exhibited by the inputs of an op amp, the currents
flowing through them are very small. The current flowing in or out of an op amp's input
pin, known as input bias current, is basically just leakage current at the base or gate of the
input transistor of that input, which is why it is very small. When solving voltage/current
equations for op amp circuits, the input currents are usually assumed to be zero. For most
of the commonly-used op-amp circuits, this means that the total output current of the op
amp is flowing through the feedback circuit between the output and the inverting input
(the feedback is usually connected to the inverting input for operation stability).
As the main path for an op amp's output current, the feedback circuit used in an op amp
largely determines how the op amp will function. There are many ways to operate an op
amp, but one commonly-used basic configuration is to: 1) provide it with balanced supply
voltages (say, +/-15V, although single-supply operation is also commonly used); 2)
connect the non-inverting input to ground (either directly or with a passive element such
as a resistor); 3) connect a feedback circuit between the output and the inverting input;
and 4) connect a resistor between the inverting input and the input signal source. Figure
1 shows some op amp circuits using this basic configuration.
Figure 1. Some Common Operational Amplifier Circuits
Another special characteristic of a close-looped op amp with negative feedback is the

zero voltage drop across its inputs. Thus, in the circuits above, the voltage at the inverting
input is zero, in effect putting the inverting input at a 'virtual ground.' Table 1 shows the
voltage/current equations governing the circuits in Figure 1, based on the assumptions
that the currents flowing through the op amp inputs and the voltage across them are zero.
OP-AMP DEVELOPMENT: Originally they contained only bipolar transistors, but now
there a host of devices that use field-effect transistors (FET), within the op-amp. Junction
field effect transistors (JFET) at the input draw very small currents. MOS transistors in
the output circuitry allow its terminal to have voltage level in milli volts of power supply.
Op amps designed with bipolar inputs and complementary MOS outputs called BiMOS,
are faster and have a higher frequency response than general purpose op-amps.
OP-AMP:
It is called operational amplifier since it is used to perform mathematical operations
like addition, subtraction, multiplication and integration.
It is a direct coupled, high gain amplifier to which feedback is added.
It has highinput impedance and low output impedance.
It is also used for a variety of applications such as ac and dc signal amplification,
filters, oscillators, comparators, regulators.
INTERNAL CIRCUITRY OF OP-AMP:

The basic op-amp consists of an input stage with two terminals, an output stage with
one output terminal and an intermediate stage that connects the output signal of the input
stage to input terminal of the output stage.
V (+) and V (-) can be positive, negative or zero.
The output voltage is measured across the resistor RL, which is connected between op-
amp’s output terminal and common. It depends on the input signals and characteristics of
the op-amp
CHARACTERISTICS (PARAMETERS) OF AN OP-AMP:

Input offset voltage (Vio):
It is defined as the voltage that must be applied between the 2 input terminals of an op-
amp to reduce the output voltage to zero. Vio= (Vdc1-Vdc2).
It is generally very low, in the order of μV.
Ideally DC output voltage (V between 2 collectors) should be zero if both input
voltages are zero. Else the level shifting ckt reduces the DC voltage.
For IC741 Vio= 6mV.
Input offset current (Iio):

It is defined as the algebraic difference between the currents into the 2 input terminals.
Iio= (Ib1-Ib2).
Its value is very small of the order 20 to 60 nA.
If the matching between the 2 input terminals is high, Iio is very less.
For IC741 Iio= 200 nA.
Input bias current (IB):

It is defined as the average of the currents that flow into the inv. and non- inv. input
terminals of the op-amp.
IB= (IB1+IB2)/2.
For IC741 IB= 500 nA.
Output offset voltage (VOO):

It is defined as the DC output voltage of the op-amp when no voltage is applied to any
of the input terminals.
Ideally it is zero and practically of the order of few mV.
Common Mode Rejection Ratio (CMRR):

When same voltage is applied to both the input terminals, the voltage is called Common
mode voltage VCM and the op-amp is said to be operating in Common mode
configuration. If VOCM is the corresponding output voltage then common mode voltage
gain is, ACM= (VOCM/VCM)
Ideally VOCM is zero and hence ACM is zero, since the output voltage is proportional
to difference of the input voltage.
CMRR= (Ad/ACM). (Here Ad is the voltage gain when two different signals are applied
to the 2 inputs).
For an ideal op-amp ACM is zero and thus is CMRR=∞. Practically ACM is very small
and Ad is very large, thus CMRR is very large.
It is oftenexpressed in dB.
Higher the value of CMRR better is the matching between the 2 terminals and better is
the rejection of the common mode signal.
For IC741 CMRR is 90dB.
SIGNIFICANCE: The CMRR expresses the ability of an op-amp to reject (reject means
output is zero) a common mode signal. The noise or the unwanted signals is common to
both the input terminals therefore the output due to the signal would be zero. Hence no
undesirable signal will be amplified. CMRR decreases as frequency in increased.
Supply Voltage Rejection Ratio (SVRR) or Power Supply Rejection Ratio (PSRR):
It is defined as the op-amp’s input offset voltage Vio caused by variations in supply
voltage
If ΔV is change in supply voltage and ΔVio be the corresponding change in input offset
voltage then
PSSR= ΔVio/ΔV
Usually denoted by μV/V.
Lower the PSSR the better is the performance of the op-amp.
Slew Rate(SR):
It is defined as the max. Change of rate of output voltage per unit time and is expressed
in V/μs.
It indicated how rapidly the output of an op-amp change in response to the change in
input frequency.
The slew rate of an op-amp is a fixed value.
For IC741 it is 0.5 V/μs.
Change in voltage gain results in change in slew rate.
Gain Bandwidth product:

Bandwidth of op-amp when voltage gain is 1.
Also called closed loop BW, unity gain BW or small signal BW.
Value approx equal to 1MHz.
Properties of an ideal op-amp:

i. A=∞.
ii. Ri=∞, thus no loading effect of the previous stage.
iii. Ro=0.
iv. Infinite BW, so that any signal can be amplified.
v. Infinite CMRR.
vi. Infinite slew rate.
vii. Characteristics are independent of temperature.
viii. Perfect balance, Vo =0when V1=V2.
NOTE: The op-amp amplifies the difference in the input voltages and not the input
voltages themselves and thus the polarity of the output voltage depends on the difference
in voltage. Ideal Voltage Transfer Curve:
The curve obtained while plotting Vo against Vid.
Vo is linearly proportional to Vid only up to certain extent after that Vo remains
constant, because Vo cannot exceed +ve and –ve saturation voltages.
Inverting Amplifier:
The input signal is applied to –ve terminal and the +ve terminal is grounded.
Vo= A∙Vid= A∙(V1-V2) = A∙(0-Vs)

= -AVs
Op-amp with negative feedback: Drawbacks of open loop op-amp: An open loop op-amp
is generally not used in linear applications because of the following reasons:
i. The open loop gain is very high. Hence even for small signals the output of op-amp is
very high.
ii. Open loop gain is not constant and varies with temperature and power supply and thus
affects its use in linear application.
iii. BW of most op-amp is generally very small, almost zero.
Advantages of negative feedback op-amp:

i. Stabilizes gain over variations in temperature, supply voltage etc.
ii. Increases input resistance and bandwidth.
iii. Decreases output resistance and distortion.
iv. Decreases voltage gain.
An op-amp with negative feedback is called feedback amplifier or closed loop amplifier.
There are 4 types of feedback configuration, and the most commonly used configurations
are:
1. Voltage series and
2. Voltage shunt.
Voltage series feedback or non- inverting feedback amplifier: Input is applied to the non
inverting terminal
SUBTRACTOR (INVERTING CONFIGURATION):
UNIT 2
OP-AMPS FREQUENCY RESPONSE AND
COMPENSATION
Op amp circuits stability,
frequency and phase response,
frequency compensating methods
manufacturer’s recommended compensation
opamp circuit band width
slew rate effects
stray capacitance effects
load capacitance effects
Zin mode compensation
circuit stability precautions
OP AMP STABILITY AND INPUT CAPACITANCE

OP AMP INSTABILITY IS COMPENSATED OUT WITH THE ADDITION OF AN EXTERNAL RC
NETWORK TO THE CIRCUIT. THERE ARE THOUSANDS OF DIFFERENT OP AMPS, BUT ALL OF
THEM FALL INTO TWO CATEGORIES: UNCOMPENSATED AND INTERNALLY COMPENSATED.
UNCOMPENSATED OP AMPS ALWAYS REQUIRE EXTERNAL COMPENSATION COMPONENTS TO
ACHIEVE STABILITY; WHILE INTERNALLY COMPENSATED OP AMPS ARE STABLE, UNDER
LIMITED CONDITIONS, WITH NO ADDITIONAL EXTERNAL COMPONENTS. INTERNALLY
COMPENSATED OP AMPS CAN BE MADE UNSTABLE IN SEVERAL WAYS: BY DRIVING
CAPACITIVE LOADS, BY ADDING CAPACITANCE TO THE INVERTING INPUT LEAD, AND BY
ADDING IN PHASE FEEDBACK WITH EXTERNAL COMPONENTS. ADDING IN PHASE FEEDBACK
IS A POPULAR METHOD OF MAKING AN OSCILLATOR THAT IS BEYOND THE SCOPE OF THIS
ARTICLE. INPUT CAPACITANCE IS HARD TO AVOID BECAUSE THE OP AMP LEADS HAVE STRAY
CAPACITANCE AND THE PRINTED CIRCUIT BOARD CONTRIBUTES SOME STRAY CAPACITANCE,
SO MANY INTERNALLY COMPENSATED OP AMP CIRCUITS REQUIRE EXTERNAL
COMPENSATION TO RESTORE STABILITY. OUTPUT CAPACITANCE COMES IN THE FORM OF
SOME KIND OF LOAD—A CABLE, CONVERTER-INPUT CAPACITANCE, OR FILTER
CAPACITANCE—AND REDUCES STABILITY IN BUFFER CONFIGURATIONS.
STABILITY THEORY REVIEW
THE THEORY FOR THE OP AMP CIRCUIT SHOWN IN FIGURE 1 IS TAKEN FROM
REFERENCE 1, CHAPTER 6. THE LOOP GAIN, A,IS
CRITICAL BECAUSE IT SOLELY DETERMINES STABILITY; INPUT CIRCUITS
AND SOURCES HAVE NO EFFECT ON STABILITY BECAUSE INPUTS ARE
GROUNDED FOR THE STABILITY ANALYSIS. EQUATION 1 IS THE LOOP GAIN
EQUATION FOR THE RESISTIVE CASE WHERE Z = R.
(1)
BEWARE OF EQUATION 1; ITS SIMPLICITY FOOLS PEOPLE BECAUSE THEY
MAKE THE ASSUMPTION THAT A = A, WHICH IS
NOT TRUE FOR ALL CASES. STABILITY CAN BE DETERMINED EASILY FROM
A PLOT OF THE LOOP GAIN VERSUS FREQUENCY. THE CRITICAL POINT IS
WHEN THE LOOP GAIN EQUALS 0 DB (GAIN EQUALS 1) BECAUSE A CIRCUIT
MUST HAVE A GAIN ≥1 TO BECOME UNSTABLE. THE PHASE MARGIN, WHICH
IS THE DIFFERENCE BETWEEN THE MEASURED PHASE ANGLE AND 180º, IS
CALCULATED AT THE 0-DB POINT. A TYPICAL OPEN-LOOP-GAIN CURVE FOR
THE TLV278X FAMILY OF OP AMPS IS USED AS A TEACHING EXAMPLE AND
IS SHOWN IN FIGURE 2.
THE OP AMP’S OPEN-LOOP GAIN AND PHASE (A IN EQUATION 1) ARE

REPRESENTED IN FIGURE 2 BY THE LEFT AND RIGHT VERTICAL
AXES, RESPECTIVELY. NEVER ASSUME THAT THE OP AMP OPEN-LOOP GAIN
CURVE IS IDENTICAL TO THE LOOP GAIN BECAUSE EXTERNAL
COMPONENTS HAVE TO BE ACCOUNTED FOR TO GET THE LOOP-GAIN
CURVE. WHEN RF = 0 AND RG = ∞, THE OP AMP REDUCES TO A
NONINVERTING BUFFER AMP (UNITY GAIN) AND THE LOOP GAIN BECOMES
EQUAL TO THE OP AMP OPEN-LOOP GAIN. WE CAN OBTAIN THE BUFFER
PHASE MARGIN DIRECTLY FROM FIGURE 2 BY TRACING THE GAIN LINE
DOWN FROM ITS VERTICAL INTERCEPT (AT APPROXIMATELY 78 DB) TO
WHERE IT CROSSES THE 0-DB LINE AT APPROXIMATELY 8 MHZ. THEN WE
CAN TRACE THE 8-MHZ LINE UP UNTIL IT INTERSECTS THE PHASE CURVE,
AND READ THE PHASE MARGIN AS APPROXIMATELY 56º. THIS PLOT WAS
MADE WITH PHASE MARGIN, BUT MANY PLOTS ARE MADE INSTEAD WITH
PHASE SHIFT. FOR PLOTS MADE WITH PHASE SHIFT, THE PHASE SHIFT MUST
BE SUBTRACTED FROM 180º TO OBTAIN THE PHASE MARGIN. NOW THAT WE
HAVE THE PHASE MARGIN, WHAT CAN WE DO WITH IT OTHER THAN TO SAY
THAT THE CIRCUIT DOES NOT OSCILLATE? FIGURE 3 IS A PLOT OF PHASE
MARGIN AND PERCENT MAXIMUM OVERSHOOT VERSUS A DUMMY
VARIABLE, THE DAMPING RATIO. ENTER THIS PLOT AT A PHASE MARGIN OF
56º AND GO UP TO THE PHASE CURVE INTERSECTION. AT THIS POINT, GO

HORIZONTALLY (CONSTANT DAMPING RATIO) TO THE INTERSECTION OF
THE OVERSHOOT CURVE, AND THEN DROP DOWN TO READ AN OVERSHOOT
OF APPROXIMATELY 11%. THIS PLOT ENABLES THE DESIGNER TO PREDICT
THE TRANSIENT STEP RESPONSE FROM THE PHASE MARGIN, AND
TRANSIENT RESPONSE IS A MEASURE OF RELATIVE STABILITY.
THE EXTERNAL RESISTORS COME INTO PLAY WHEN THE OP AMP IS

CONFIGURED AS AN INVERTING, NONINVERTING, OR DIFFERENTIAL
AMPLIFIER. WHEN RF = RG, EQUATION 1 REDUCES TO A= A/2; AND THE
VERTICAL INTERCEPT FOR THE AMPLIFIER REDUCES FROM THAT OF THE
BUFFER BY 6 DB. ALTHOUGH THE VERTICAL INTERCEPT HAS CHANGED,
THE POLE LOCATION REMAINS CONSTANT BECAUSE GAIN IS NOT TIED TO
PHASE. THE 0-DB CROSSOVER FREQUENCY CHANGES TO APPROXIMATELY
3 MHZ BECAUSE OF THE GAIN DROP; THE PHASE MARGIN INCREASES TO
APPROXIMATELY 87º; AND THE PERCENT OVERSHOOT IS NEGLIGIBLE.

NOTICE THAT THE BUFFER IS LESS STABLE THAN ANY OF THE AMPLIFIER
CIRCUITS AND THAT, AT THE SAME PHASE MARGIN, THE INVERTING GAIN
IS –1 WHILE THE NONINVERTING GAIN IS 2.
ADDED INPUT CAPACITANCE AND ITS EFFECT

WHEN INPUT CAPACITORS ARE ADDED TO THE CIRCUIT (SEE FIGURE 4),
THEY CAUSE A POLE TO OCCUR IN THE LOOP GAIN, AS
SHOWN IN EQUATION 2.
THE INPUT CAPACITOR, CIN, IS THE SUMMATION OF ALL THE INVERTING

INPUT CAPACITANCES, AND IT ADDS A POLE TO THE LOOP
GAIN. ADDING A POLE TO THE LOOP GAIN DOES NOT ALWAYS CHANGE THE
STABILITY BECAUSE THE POLE LOCATION AND ITS ADDED PHASE SHIFT
MAY NOT AFFECT THE PHASE MARGIN. CONSIDER THE CASE WHERE THE
POLE IS LOCATED AT A VERY HIGH FREQUENCY—SAY, 100 MHZ—FOR THE
TLV278X. NOTICE FROM FIGURE 2 THAT THE OP AMP OPEN-LOOP GAIN IS SO
LOW ABOVE 10 MHZ THAT THE OVERALL GAIN CAN NEVER EQUAL 1, SO
THE ADDED POLE IS OF NO VALUE. THE CASE WHERE THE POLE IS LOCATED
AT A VERY LOW FREQUENCY—SAY, 0.001 HZ—IS HARDER TO CALCULATE
BECAUSE THE LOW-FREQUENCY RESPONSE IS NOT SHOWN IN FIGURE 2.

HOWEVER, WE CAN BE SURE THAT THE PHASE SHIFT IS CLOSE TO ZERO AT
THIS FREQUENCY. A POLE WITH A FREQUENCY INTERCEPT THAT LOW
WOULD CAUSE THE GAIN TO BE DOWN 120 DB AT 1 KHZ, AND AGAIN THE
LOOP GAIN WOULD BE LESS THAN 1 BEFORE THE PHASE MARGIN WENT TO
ZERO. AN OP AMP OPEN-LOOP GAIN/PHASE PLOT
THAT SHOWS LOW-FREQUENCY RESPONSE IS SHOWN IN FIGURE 5. NOTICE
THAT THE PHASE SHIFT (NOT PHASE MARGIN IN THIS PLOT) APPROACHES
ZERO AT LOW FREQUENCIES. IN ADDITION, NOTICE THAT THE PHASE SHIFT
APPROACHES 180º AT VERY HIGH FREQUENCIES AND THAT THE GAIN IS
GIVEN IN RATIOS RATHER THAN IN DECIBELS.
OP AMP INPUT BIAS CURRENT
CIRCUIT
One of the golden rules of op amp analysis says this: no current flows into either input
terminal. This concept is key for analyzing an amplifier's signal gain. However, in reality,
a small current flows into both inputs to bias the input transistors. Unfortunately, this bias
current gets converted into a voltage by the circuit's local resistors and amplified right
along with the signal. The result is an output error in your circuit. What can you do about
it? A clever choice of resistor values can help you cancel most of the output error. The
remaining error can be adjusted to zero if necessary.
INPUT BIAS CURRENT
Depending on the type of input transistor, the bias current can flow in or out of the input
terminals. The input current is modeled as current sources, Ib+ and Ib-, in parallel with
the positive and negative input terminals. How big is this current? The magnitudes can
range from μA down to pA. Generally speaking, JFET or CMOS op amps have smaller
bias currents than BJT types. Although Ib+ and Ib- are similar in magnitude, there not
exactly the same. This difference, called the input offset current, is described by Iboff =
Ib+ - Ib- .
AMPLIFIER WITH BIAS CURRENT
Is the circuit shown above an inverting or non-inverting amplifier? The answer is yes,
both! With the input signal source set to 0 V ( shorted ), the inverting and non-inverting
amplifiers look the same. What kind of undesirable voltage does the bias current create in
your circuit?
Effect of Ib+ on Vo
Vo = Ib+ ∙ R3 ∙ ( R2 / R1 + 1 )
This is easy to understand. Ib+ flowing into R3 produces a voltage at the + input.
Treating it like any other voltage at this terminal, the op amp amplifies it according to
the non-inverting gain equation.
Effect of Ib- on Vo
Vo = - ( Ib- ∙ R2 )
Just like the transimpedance (current-to-voltage) amplifier, the output voltage is simply
the input current times the feedback resistor.
What are the equations above telling us about resistor choice? For a given op amp, the
smaller the resistor values, the smaller the errors. However, certain design goals, like
low power, may force high resistor values. As usual, the end result is a compromise
between competing design parameters.
INPUT BIAS CANCELLATION
Currents Ib+ and Ib- create errors of opposite polarity. The question now is this: can we
choose a magical value of R3 to force the errors caused by both bias currents to cancel
each other? First, let's describe our goal mathematically. We would like the errors from
both sources to be equal and opposite to one another. To do so, just take the two error
equations above and set them equal to each other. Also, assume that the bias currents are
equal Ib+ = Ib- = Ib.
Ib ∙ R3 ∙ ( R2 / R1 + 1 ) = Ib ∙ R2
Next, solve for R3 in terms of R1 and R2.
R3 = ( R2 ∙ R1 ) / ( R1 + R2 ) = R1 || R2
The solution is clear, choose R3 equal to the parallel combo of R1 and R2, and the bias
current errors will cancel!
HANDS-ON DESIGN Set both IBPOS and IBNEG equal to 100nA. With R1=10k and
R2=10k set R3 equal to R1 || R2 = 5k. Run a simulation of OP_IBIAS.CIR. Did your new
choice of R3 reduce the output error at V(4) to 0V?
NPUT OFFSET CURRENT
Not to burst your bubble, but a clever choice of R3 doesn't mean all of the error is gone.
In reality, the input currents are not exactly matched. They could differ by 10% or more.
To see the effect of this offset, set IBPOS = 100nA and IBNEG = 90 nA. Run a
simulation. How much residual error has popped up at V(4) due to the input offset
current?
INPUT OFFSET CURRENT ADJUSTMENT
The output error due to the offset current may be too big for your application. So how do
you get rid of it? You can plum in another voltage to cancel out the remaining error.
Using a potentiometer VPOT and a resistor connected to the op amp's negative input does
the trick. Check out this circuit from Op Amp Input Offset Voltage.
BIAS CURRENT DRIFT
Bias currents will drift as temperature changes. You have no control over this. But,
knowing your overall error budget, you can select an op amp with a low enough bias
current for the intended temperature range.
INPUT OFFSET VOLTAGE
Input bias current is not the only undesirable characteristic of the op amp's input. A
number of unbalances in the op amp's internal transistors and resistors create an input
offset voltage. You can predict the error at you circuit's output and adjust it to 0V if
needed. (See Op Aamp Input Offset Voltage )
OP AMP INPUT OFFSET VOLTAGE
CIRCUIT
Build any opamp circuit, apply 0V to its input, and what do you expect at the output?
Although you'd be tempted to say 0 V, there's actually an error voltage present at its
output. What causes this error? You can trace the error back to a number of unbalances in
the op amp's internal transistors and resistors. To account for this in a circuit design, the
net error is modeled as an offset voltage, Voff, in series with op amp's input terminals.
How will it affect your circuit? That depends on the op amp itself and your circuit design.
INPUT OFFSET VOLTAGE
The input offset voltage can range from microvolts to millivolts and can be either
polarity. Generally speaking, bipolar op amps have lower offset voltages than JFET or
CMOS types. The offset voltage is modeled in series with one of the op amp input
terminals. Which one? Although the net effect is the same at either input, it's much easier
to analyze Voff in series with the positive (V+) input. Why? The resulting circuit with
Voff at V+ looks just like the non-inverting amplifier configuration. The analysis for
this circuit is a simple one.
AMPLIFIER WITH OFFSET VOLTAGE
Ignoring Voff for a moment, is the circuit (shown above) an inverting or non-inverting
amplifier? The answer is yes, both! With the input signal source set to 0 V ( shorted ), the
inverting and non-inverting amplifiers look the same. The analysis for offset voltage is
independent of the amplifier configuration. You can predict the error at the output Vo by
the equation for the non-inverting amplifier
Vo_error = Voff ( R2 / R1 + 1 )
What danger is this equation warning you about? If you have a large signal gain in your
circuit, the amplifier will increase the error Voff along with the signal.
CIRCUIT INSIGHT Run a simulation of OP_VOFF.CIR. Voltage source VOFF

models the offset voltage, initially set to +1 mV. With R1 = 10k and R2 = 100 k, what is
the error at the output V(4)? The output error gets bumped to a whopping 11 mV as
predicted by the equation above. Choose a different gain and/or offset voltage. Run a
simulation. Is the output error what you expected?
OFFSET VOLTAGE CANCELLATION
In some applications, the output offset may be unacceptable. So how do you get rid of
this error? One solution involves canceling it using another voltage of the same
magnitude and opposite polarity. But the exact magnitude and polarity of the offset is
unknown! You'll need a range of values (using a potentiometer, for example) to cover
your basis. The question is how to get the canceling voltage into the circuit? One simple
way is via a resistor R3 to the op amp's negative input.
For simplicity, VPOT represents a voltage generated by a potentiometer divider circuit.

The output due to VPOT is simply
Vo = VPOT ( -R2 /R3 )
which is the same equation as for the inverting amplifier.
HANDS-ON DESIGN INSERT VPOT AND R3 INTO THE CIRCUIT BY REMOVING THE * AT
THE BEGINNING OF THE STATEMENTS. RUN A SIMULATION OF OP_VOFF.CIR. VOLTAGE
VPOT GENERATES A RAMP THAT GOES FROM -0.2V TO +0.2 V. THIS SIMULATES YOU
TURNING THE POTENTIOMETER OVER THE FULL RANGE. CHECK OUT THE OUTPUT VOLTAGE
V(4). AT SOME POINT, DOES THE OUTPUT GET TRIMMED TO 0 V?
SUPPOSE YOU HAVE A POORER GRADE OP AMP WITH A MAXIMUM OFFSET OF 5 MV. CHANGE
THE VOFF VALUE TO 5MV. RUN A NEW SIMULATION. DOES THE OUTPUT GET TRIMMED TO
0V? IF NOT, INCREASE VPOTS RANGE BEYOND -0.2V TO 0.2V. HOW BIG OF A RANGE TO
YOU NEED TO CANCEL THE 5MV OFFSET. ANOTHER WAY YOU CAN ADJUST THE
CANCELLATION RANGE IS TO ADJUST R3. THE EQUATION ABOVE TELLS YOU THAT
DECREASING R3 INCREASES THE GAIN FROM VPOT TO VO.
HOW DOES R3 EFFECT GAIN?
WHAT EFFECT DOES R3 HAVE ON THE GAIN OF YOUR CIRCUIT? THAT DEPENDS ON WHICH
GAIN WE'RE TALKING ABOUT. T HERE ARE THREE GAIN OF INTEREST HERE. ( NOTICE THAT
LOOKING LEFT FROM THE OP AMPS' NEGATIVE INPUT, R3 IS EFFECTIVELY IN PARALLEL WITH
R1.)
INPUT OFFSET VO / VOFF = R2 / R3 DIRECTLY EFFECTS THE OUTPUT

VOLTAGE GAIN (R1||R3) + 1 ERROR - THE SMALLER R3, THE
THE
LARGER THE ERROR DUE TO VOFF.
NON-INVERTING VO / VIN = R2 / FEEDING A SIGNAL TO THE OP AMP'S
AMPLIFIER GAIN (R1||R3) + 1 POSITIVE INPUT FORMS THE NON-
INVERTING AMPLIFIER. THE
EQUATION IS IDENTICAL TO THE ONE
ABOVE.
INVERTING AMPLIFIER VO / VIN = - R2 / R1 FEEDING A SIGNAL TO THE LEFT LEG
GAIN OF R1 FORMS THE INVERTING
AMPLIFIER. R3 HAS NO EFFECT ON
THIS GAIN.
CIRCUIT INSIGHT WHAT ARE THE ABOVE EQUATIONS TELLING US ? IF YOU DON'T
WANT YOUR GAIN SEVERELY AFFECTED, KEEP R3 AS LARGE AS POSSIBLE. YOU CAN CHECK
THE INFLUENCE OF R3 BY SETTING VPOTS'S RAMP LIMITS TO 0V AND 0V. THEN, WITH R1 =
10K, R2 = 100K AND VOFF = 1MV, THE EXPECTED OUTPUT ERROR IS 11 MV. RUN A
SIMULATION TO SEE HOW R3 = 1MEG OR 100K CHANGES THE OUTPUT VOLTAGE ERROR?
OFFSET VOLTAGE DRIFT
JUST BECAUSE YOU TRIMMED OUT THE OFFSET VOLTAGE, DOESN'T MEAN ALL IS TRANQUIL
ON PARADISE ISLAND. THE INPUT OFFSET VOLTAGE WILL DRIFT WITH TEMPERATURE; YOU
HAVE NO CONTROL OVER THIS. BUT, KNOWING YOUR OVERALL ERROR BUDGET, YOU CAN
SELECT AN OP AMP WITH A LOW ENOUGH OFFSET DRIFT FOR THE INTENDED TEMPERATURE
RANGE.
INPUT BIAS CURRENT
INPUT OFFSET VOLTAGE IS NOT THE ONLY ERROR OF THE OP AMP'S INPUT. THE INPUT STAGE
IS MADE OF TRANSISTORS, REQUIRING A FINITE AMOUNT OF BIAS CURRENT FOR OPERATION.
THE CIRCUIT ABOVE ASSUMES THE BIAS IS NEGLIGIBLE. HOWEVER, REAL OP AMPS HAVE
BIAS CURRENTS TO BE RECKONED WITH. THE GOOD NEWS IS THERE ARE CLEVER
TECHNIQUES YOU CAN USE TO MINIMIZE AND CANCEL OUT THESE ERRORS TOO.
FREQUENCY COMPENSATION
In electrical engineering, frequency compensation is a technique used in amplifiers, and

especially in amplifiers employing negative feedback. It usually has two primary goals:
To avoid the unintentional creation of positive feedback, which will cause the amplifier
to oscillate, and to control overshoot and ringing in the amplifier's step response.
Most amplifiers use negative feedback to trade gain for other desirable properties, such as
decreased distortion or improved noise reduction. Ideally, the phase characteristic of an
amplifier's frequency response would be constant; however, device limitations make this
goal physically unattainable. More particularly, capacitances within the amplifier's gain
stages cause the output signal to lag behind the input signal by 90° for each pole they
create. If the sum of these phase lags reaches 360°, the output signal will be in phase with
the input signal. Feeding back any portion of this output signal to the input when the gain
of the amplifier is sufficient will cause the amplifier to oscillate. This is because the
feedback signal will reinforce the input signal. That is, the feedback is then positive
rather than negative.
Frequency compensation is implemented to avoid this result.
Another goal of frequency compensation is to control the step response of an amplifier

circuit as shown in Figure 1. For example, if a step in voltage is input to a voltage
amplifier, ideally a step in output voltage would occur. However, the output is not ideal
because of the frequency response of the amplifier, and ringing occurs. Several figures of
merit to describe the adequacy of step response are in common use. One is the rise time
of the output, which ideally would be short. A second is the time for the output to lock
into its final value, which again should be short. The success in reaching this lock-in at
final value is described by overshoot (how far the response exceeds final value) and
settling time (how long the output swings back and forth about its final value). These
various measures of the step response usually conflict with one another, requiring
optimization methods.
Frequency compensation is implemented to optimize step response, one method being

pole splitting.
USE IN OPERATIONAL AMPLIFIERS
Because operational amplifiers are so ubiquitous and are designed to be used with
feedback, the following discussion will be limited to frequency compensation of these
devices.
It should be expected that the outputs of even the simplest operational amplifiers will
have at least two poles. An unfortunate consequence of this is that at some critical
frequency, the phase of the amplifier's output = -180° compared to the phase of its input
signal. The amplifier will oscillate if it has a gain of one or more at this critical
frequency. This is because (a) the feedback is implemented through the use of an
inverting input that adds an additional -180° to the output phase making the total phase
shift -360° and (b) the gain is sufficient to induce oscillation.
A more precise statement of this is the following: An operational amplifier will oscillate
at the frequency at which its open loop gain equals its closed loop gain if, at that
frequency,
1. The open loop gain of the amplifier is ≥ 1 and

2. The difference between the phase of the open loop signal and phase response of
the network creating the closed loop output = -180°. Mathematically,
ΦOL – ΦCLnet = -180°
OP AMP BANDWIDTH
CIRCUIT
NON-INVERTING AMPLIFIER
INVERTING AMPLIFIER
ITS ALL ABOUT SPEED - AT LEAST THAT'S WHAT THIS TOPIC IS ABOUT. IN AN IDEAL WORLD,
AN OP AMP RESPONDS ACCURATELY AND INSTANTLY TO AN AUDIO OR VIDEO SIGNAL. BUT
IN THE REAL WORLD, THERE'S A LIMIT ON THE HIGHEST FREQUENCY (BANDWIDTH) AND
FASTED EDGE YOUR OP AMP CAN PROCESS. A FEW SIMPLE CONCEPTS PROVIDE INSIGHT INTO
AN AMPLIFIER'S BANDWIDTH. AND KNOWING THIS CAN HELP YOU MAKE BETTER OP AMP
AND CIRCUIT CHOICES.
THE REAL STORY OF GAIN
TO UNDERSTAND BANDWIDTH, WE MUST UNDERSTAND THE REAL GAIN EQUATION. YOU'VE

PROBABLY SEEN THE IDEAL CLOSED-LOOP VOLTAGE GAIN EQUATION FOR A NON-
INVERTING AMPLIFIER.
BUT, WHAT'S THE REAL STORY INCLUDING THE OP AMP'S INTERNAL GAIN ? I T ACTUALLY
LOOKS LIKE THIS
WHERE A - OPEN-LOOP GAIN - INTERNAL GAIN OF THE OP AMP ITSELF.
Β - FEEDBACK FACTOR - HOW MUCH OF THE OUTPUT IS FED BACK TO THE NEGATIVE
INPUT
HERE'S THE BEAUTY OF THIS EQUATION. CHECK OUT WHAT HAPPENS TO GCL IF A IS
MADE LARGE.
FOR A >> (R2+R1) / R1,
THE BOTTOM LINE? THE GAIN IS SET BY R1

R2, NOT THE OP AMP GAIN A! ( THIS
AND
FACT CERTAINLY SIMPLIFIES OP AMP CIRCUIT DESIGN.) AND CONSEQUENTLY, A CAN VARY
DUE TO INITIAL TOLERANCES OR TEMPERATURE DRIFT, BUT THE VOLTAGE GAIN HOLDS
ROCK SOLID SET BY THE RESISTOR VALUES!
BANDWIDTH
SO WHAT'S THE PROBLEM WITH THE REAL GAIN EQUATION?

ALTHOUGH, A IS LARGE AT
LOWER FREQUENCIES, IT FALLS AT HIGHER FREQUENCIES. AND WHEN A DROPS NEAR
(R2+R1) / R1, GCL DROPS TOO. THE FREQUENCY WHERE GCL FALLS BELOW THE IDEAL
GAIN IS CALLED THE BANDWIDTH FC.
CIRCUIT INSIGHT RUN OP_BANDWIDTH1.CIR. THE CLOSED-

A SIMULATION OF
LOOP GAIN FOR THIS CIRCUIT IS GCL = (10K+10K)/10K = 2 V/ V. PLOT THE AC RESPONSE
FOR THE OUTPUT AT V(4) AND A VIA THE EQUATION V(4)/(V(2)-V(1)). TO GET A CLEARER
VIEW, SELECT LOG FOR THE Y-AXIS. FOR THIS PARTICULAR OP AMP, A HAS A DC GAIN OF
100,000 V/V, 100 HZ. WHAT ABOUT GCL? YOU CAN SEE THAT
THEN FALLS OFF ABOVE
ALL IS WELL AS LONG AS A >> 2. BUT WHEN A DROPS CLOSE TO GCL, THE CLOSED-LOOP
GAIN TAKES A DIVE.
NOTE WHERE GCL BEGINS TO DROP. THE FREQUENCY WHERE THE VOLTAGE FALLS TO
0.707 OF ITS INTENDED VALUE IS THE CUTOFF OR -3 DB FREQUENCY, FC. ( GAIN IN
DECIBELS = 20∙ LOG(0.707) = -3DB. )
HANDS-ON DESIGN PICK A HIGHER GAIN FOR THIS AMPLIFIER. CHOOSE R2

SOMEWHERE IN THE RANGE OF 10 K TO 10,000 KΩ. RERUN THE SIMULATION. YES, GCL
LOOKS GREAT AT LOW FREQUENCIES, BUT WHAT HAPPENED TO THE BANDWIDTH? BECAUSE
GCL IS ESSENTIALLY BOUNDED BY A, THE BANDWIDTH FC GETS SMALLER AS GAIN
INCREASES! LIFE AND CIRCUIT DESIGN ARE FULL OF COMPROMISE, AND GAIN VERSUS
BANDWIDTH IS A FINE EXAMPLE.
LET'S TRY TO EXTEND THE BANDWIDTH.TO DO THIS, PROVIDE THE OP AMP WITH MORE
AVAILABLE A BY INCREASING ITS DC GAIN OR BANDWIDTH. THE OP AMP MODEL
SIMULATES THE DC GAIN WITH EGAIN 3 0 1 2 100K. INCREASE THE 100K BY A FACTOR OF
10 OR SO. OR, YOU CAN INCREASE THE BANDWIDTH BY DECREASING RP1 OR CP1 BY A
FACTOR OF 10. RUN A NEW SIMULATION. DID YOUR NEW OP AMP EXTEND THE BANDWIDTH
AT V(4)?
GAIN-BANDWIDTH PRODUCT
AS YOU HAVE SEEN, GAIN AND BANDWIDTH HAVE A RELATIONSHIP. MORE PRECISELY, THE
PRODUCT OF CLOSED-LOOP GAIN GCL AND BANDWIDTH FC IS CONSTANT!
GAIN X BANDWIDTH = GCL X FC = GBP (GAIN BANDWIDTH PRODUCT)
WHAT DOES THIS MEAN? IF YOU WANT TO INCREASE THE GAIN GCL, THE BANDWIDTH FC
WILL DROP TO MAINTAIN A CONSTANT GBP. ALTERNATIVELY, IF YOU NEED A HIGHER
BANDWIDTH, THEN LOWER THE GAIN. IF YOU NEED BOTH HIGHER GAIN AND BANDWIDTH,
PICK AN OP AMP WITH A HIGHER GBP ON ITS DATA SHEET. (GBP MAY BE ALSO CALLED THE
UNITY-GAIN FREQUENCY.)
YOU CAN USE GBP TO PREDICT THE BANDWIDTH AT ANY GAIN. FOR EXAMPLE, A NON-
INVERTING AMPLIFIER HAVING A GBP = 10 MHZ AND R1 = R2 = 10K GIVES A CLOSED-
LOOP GAIN GCL = 2 AND A BANDWIDTH OF
FC = GBP / GCL
= 10 MHZ / 2
= 5 MHZ
HANDS-ON DESIGN RUN A FEW SIMULATIONS WITH VARIOUS VOLTAGE GAINS OF

OP_BANDWIDTH1.CIR. PLOT THE AC RESPONSE AT THE OUTPUT AT V(4) AND A VIA
THE EQUATION V(4)/(V(2)-V(1)). YOU SHOULD BE ABLE TO PREDICT THE BANDWIDTH AT
V(4) FOR ANY OF YOUR CHOSEN GAINS.
THE INVERTING AMPLIFIER
WHAT ABOUT THE OTHER MAJOR PLAYER IN OP AMP CIRCUITS: THE INVERTING AMPLIFIER?
THE RESULTS ARE SIMILAR WITH A SLIGHT TWIST. LET'S START WITH THE CLOSED-LOOP
GAIN EQUATION
WHERE A IS THE INTERNAL GAIN. THE FEEDBACK FACTOR IS
Β = R1 / (R1+R2).
NOTE, THE FEEDBACK FACTOR, Β = R1 / (R1+R2), IS THE SAME FOR INVERTING OR NON-
INVERTING AMPLIFIER. THAT'S BECAUSE Β IS CALCULATED WITH VS SET TO 0V, MAKING
BOTH CIRCUITS LOOK THE SAME!
SIMILAR TO THE NON-INVERTING AMPLIFIER, WHEN A IS LARGE, THE IDEAL INVERTING

GAIN IS ACHIEVED.
FOR A >> (R2+R1) / R1,
HOWEVER, AS A DROPS CLOSE TO THE IDEAL GAIN, THE ACTUAL GCL BEGINS TO DROP.
HOW DO WE PREDICT THIS FREQUENCY WHERE THE GAIN FALLS OFF? USING GBP WE
CALCULATE
FC = GBP / GN
BUT HERE'S THE TWIST, THE FC CALCULATION USES THE NON-INVERTING GAIN
GN = (R1 + R2) / R1
IN THE DENOMINATOR, NOT THE INVERTING GAIN! FOR EXAMPLE, AN OP AMP HAVING A
GBP = 10 MHZ AND R1 = R2 = 10K GIVES AN INVERTING GAIN OF GCL = -1. HOWEVER,
THE BANDWIDTH IS REDUCED BY
GN = (R1 + R2) / R1 = 2 GIVING
FC = GBP / GN
= 10 MHZ / 2
= 5 MHZ
THERE'S THE DISADVANTAGE OF THE INVERTING AMPLIFIER: SIGNALS ARE AMPLIFIED BY THE
R2 / R1 RATIO, BUT THE BANDWIDTH IS KNOCKED DOWN BY THE LARGER ( R1+R2 ) / R1 RATIO.
( GN IS ALSO CALLED THE NOISE GAIN BECAUSE OP AMP INPUT ERRORS AND NOISE ARE
AMPLIFIED BY THE NON-INVERTING GAIN, EVEN FOR THE INVERTING AMPLIFIER. )
CIRCUIT INSIGHT TRY OUT THE INVERTING AMPLIFIER IN THE

OP_BANDWIDTH1.CIR. PLOT THE AC RESPONSE FOR THE OUTPUT V(14) AND THE OP
AMP'S INTERNAL GAIN V(14)/V(12). A LOG PLOT ON THE Y-AXIS CAN GIVE A BETTER VIEW.
THE GAIN SHOULD MATCH THE IDEAL -R2 / R1 AS LONG AS A IS LARGER THAN (R1+R2)/R1.
HANDS-ON DESIGN CRANK UP THE GAIN BY CHOOSING R2 SOMEWHERE IN THE RANGE

OF 10 K TO 10,000 KΩ. RERUN THE SIMULATION. FOR ANY GAIN, GCL SHOULD BE
BOUNDED BY A. DOES THE BANDWIDTH GET SMALLER AS YOU INCREASE GAIN?
NON-INVERTING VS. INVERTING AMPLIFIER
HERE'S A SHOWDOWN BETWEEN THE TWO CLASSIC AMPLIFIERS. THE CHALLENGE IS THIS:
FOR THE SAME GAIN, WHICH AMPLIFIER HAS THE GREATER BANDWIDTH? WE'LL USE A
VOLTAGE GAIN OF 2 FOR BOTH CIRCUITS.
CLOSED-LOOP
GAIN NOISE GAIN BANDWIDTH
AMPLIFIER GAIN GBP
COMPONENTS GN FC = GBP / GN
GCL
NON- R1 = 10 K (R1+R2) / R1 = (R1+R2) / R1 = 10 MHZ / 2 = 5

10 MHZ
INVERTING R2 = 10 K +2 V/V 2 MHZ
R1 = 10 K (R1+R2) / R1 = 10 MHZ / 3 =
INVERTING - R2 / R1 = -2 V/V 10 MHZ
R2 = 20 K 3 3.3 MHZ
THE BANDWIDTH CHAMPION IS THE NON-INVERTING AMPLIFIER! HOWEVER, THIS

BANDWIDTH DIFFERENCE IS LESS FOR LARGER GAINS. STILL, ALL OTHER THINGS BEING
EQUAL, CHOOSE THE NON-INVERTING AMPLIFIER TO MAXIMIZE YOUR BANDWIDTH.
CIRCUIT INSIGHT RUN A SIMULATION OF OP_BANDWIDTH1.CIR. SET THE

RESISTORS IN THE NON-INVERTING AND INVERTING AMPLIFIERS TO VALUES IN THE TABLE
ABOVE. PLOT THE AC OUTPUT AT V(4) AND V(14). DID THE NON-INVERTING GAIN LIVE UP
TO EXPECTATIONS?
ANOTHER WAY TO MEASURE CIRCUIT SPEED IS HOW FAST THE AMPLIFIER RESPONDS TO A
STEP INPUT. IN THE REAL WORLD, THE STEP INPUT REPRESENTS A QUICK BRIGHTNESS
CHANGE IN A VIDEO SIGNAL OR THE RISING / FALLING EDGE OF A CLOCK SIGNAL. RUN A
SIMULATION AND PLOT THE TRANSIENT RESPONSE AT V(4) AND V(14). HOW MUCH FASTER
DOES THE NON-INVERTING OUTPUT REACH 90% OF ITS FINAL VALUE COMPARED TO THE
INVERTING OUTPUT?
MORE TO BANDWIDTH
ALTHOUGH GBP AND GAIN PLAY A MAJOR ROLE IN DETERMINING BANDWIDTH, THERE'S
MORE TO IT. SLEW RATE AND HEAVY LOADING CAN CUT INTO YOUR BANDWIDTH. SLEW
RATE WOULD NOT ONLY MAKE AN INTERESTING DESIGN TOPIC, BUT A CHALLENGING
SIMULATION TOPIC AS WELL. ITS ON THE LIST OF FUTURE TOPICS. LET US KNOW WHICH
DESIGN TOPICS OR CIRCUITS PEAK YOUR INTEREST.
SLEW RATE
IN ELECTRONICS, THE SLEW RATE REPRESENTS THE MAXIMUM RATE OF CHANGE OF A

SIGNAL AT ANY POINT IN A CIRCUIT. LIMITATIONS IN SLEW RATE CAPABILITY CAN GIVE RISE
TO NON LINEAR EFFECTS IN ELECTRONIC AMPLIFIERS. FOR A SINUSOIDAL WAVEFORM NOT
TO BE SUBJECT TO SLEW RATE LIMITATION, THE SLEW RATE CAPABILITY AT ALL POINTS IN
AN AMPLIFIER MUST SATISFY THE FOLLOWING CONDITION:
WHERE F IS THE FREQUENCY, AND VPK IS THE PEAK AMPLITUDE OF THE WAVEFORM. SLEW
RATE IS USUALLY EXPRESSED IN UNITS OF V/µS.
IN MECHANICS THE SLEW RATE IS GIVEN IN DIMENSIONS 1/T AND IS ASSOCIATED WITH THE
CHANGE IN POSITION OVER TIME OF AN OBJECT WHICH ORBITS AROUND THE OBSERVER.
DEFINITION
The output slew-rate of an amplifier or other electronic circuit is defined as the maximum
rate of change of the output voltage for all possible input signals.
where vout(t) is the output produced by the amplifier as a function of time t.
SLEW RATE LIMITING IN AMPLIFIERS
There are slight differences between different op-amp designs in how the slewing
phenomenon occurs. However, the general principles are the same as in this illustration.
The input stage of modern power amplifiers is usually a differential amplifier with a
transconductance characteristic. This means the input stage takes a differential input
voltage and produces an output current into the second stage.
The transconductance is typically very high — this is where the large open loop gain of
the amplifier is generated. This also means that a fairly small input voltage can cause the
input stage to saturate. In saturation, the stage produces a nearly constant output current.
The second stage of modern power amplifiers is, amongst other things, where frequency
compensation is accomplished. The low pass characteristic of this stage approximates an
integrator. A constant current input will therefore produce a linearly increasing output. If
the second stage has a compensation capacitance C and gain A2, then slew rate in this
example can be expressed as:
where Isat is the output current of the first stage in saturation.
Slew rate helps us to identify what is the maximum input frequency applicable to the
amplifier such that the output is not distorted. Thus it becomes imperative to check the
datasheet for the device's slew rate before using it for high frequency applications.
Stray Capacitance effect
Compensate for input parasitic Capacitance

A small capacitor across the feedback resistor will compensate for parasitic capacitance
at the (inverting) input of the Op-Amp. Normally 3pF to 10pF will compensate. This is
true for Inverting, Non-Inverting, or Voltage Follower configurations. A feed back pole is
created when the feedback around any amplifier is resistive. The parallel resistance and
capacitance from the input of the device (usually the inverting input) to Ac ground set the
frequency of the pole. In many cases the frequency of the pole is much greater than the
3dB frequency of the closed loop gain ~ there is negligible effect on the stability margin.
How ever, if the feed back pole is less than approximately six times the expected 3dB
frequency, a 'lead' capacitor should be placed from the output to the input of the Op-Amp.
The value of the added capacitor should be such that the RC time constant of this
capacitor and resistor it parallels is greater than or equal to the original feed back pole
time constant.
UNIT -3
SIGNAL PROCESSING CIRCUITS
Precision half wave & full wave rectifiers

limiting circuits
clamping circuits
peak detectors
Sample & hold circuit.
DAC and ADC (Flash and successive approximations)
OP AMP PRECISION HALF-WAVE RECTIFIER
CIRCUIT
Rectifiers are often called into action to measure signal strength. Rectify an AC signal,
pass it through a low-pass filter and the resulting DC level represents some measure of
the signal's magnitude. Although the series diode is the classic rectifier, it can't rectify
signals smaller that it own forward voltage! But what if your expected amplitude can be
as low as 100 mV? Op amps to the rescue! The advantage of op amp circuits lies in their
ability to compensate for non-linear devices in the feedback loop. Combining the
rectifying action of a diode with the accuracy of an op amp, this circuit creates a
precision rectifier.
NVERTING HALF-WAVE RECTIFIER
During the negative half-cycle of a sinewave input, the output should be positive. During
the positive half-cycle, the output should be zero. The circuit that accomplishes this
amazing feat looks like the inverting amplifier with a couple of diodes added. Why two?
Only one actually does the rectifying action. The other simply keeps the op amp in
control while the signal output holds at zero.
For the negative half-cycle input, the op amp output goes positive forcing D1 to turn
ON and D2 to shut OFF.
It looks and acts just like the inverting amplifier, except for a diode in a series with the
op amp's output pin. But no need to worry, the output pin adjusts itself higher (by the
diode's forward voltage, about 0.6V ) to get the right voltage at the Vo. The classic
inverting equation applies.
Vo = - R2 / R1 ∙ VS
For R1 = R2 = 10k and VS = -1 V, the output is Vo = - 10k / 10k x -1 = +1 V. The

current running through both R1 and R2 is I = VS / R1 = 1 /10k = 0.1 mA. And like the
classic inverting amplifier, the op amp holds the negative input V- at 0V (virtual ground).
For the positive half-cycle input, the op amp output goes negative forcing D2 to turn
ON and D1 to shut OFF.
The first question to ask is what is the output voltage Vo? Although the circuit looks a
little strange, the output actually sits at 0V. This is because the op amp still does its job of
holding V- at 0V. And because there's no current through R2, you get Vo = V- = 0V. The
only thing left to reckon with is the current running through R1, I = VS / R1 = +1 / 10k =
0.1 mA. During this half-cycle, the op amp's output swings negative to turn on D1
enough to pull 0.1 mA through the diode.
PRECISION RECTIFIER
CIRCUIT INSIGHT Run a simulation of the precision op amp rectifier

OP_HW_RECTIFIER.CIR. Does the output V(3) rectify the input V(1) as expected?
Take a look at the op amp's output pin V(4). It should ride above the positive output half-
cycle by a diode's forward voltage when D1 is ON. During the negative half-cycle, V(4)
should swing below zero by the diode's voltage when D2 is ON. To see each diode in
action, plot their currents by opening a separate plot window and adding traces I(D1) and
I(D2).
Let's compare the precision rectifier to the cheap and dirty diode rectifier, D3 and RL2.
Plot the output at V(5). Yes, it rectifies, but the output falls short by a diode drop. What
about small input signals like 100 mV? Change VS to 0.1V and compare rectifier outputs.
GAIN AND POLARITY
HANDS-ON DESIGN This rectifier circuit comes with some flexibility. To change the
output polarity, simply swap the diode polarities. To change the gain, select the R2/R1
ratio for your desired gain. Choose a different gain or polarity and take the new circuit
out for a test drive.
SPEED LIMIT
This circuit runs fine at a 1 kHz input, but what happens at higher frequencies? You may
have noticed that when the input crosses zero, the op amp's output V(4) changing rapidly
as it attempts to turn the diodes on and off. How fast can the op amp's output change?
That depends on the speed of the op amp.
CIRCUIT INSIGHT Change the input VS back to 1 Vpeak and crank up the frequency
from 1 kHz to 100 kHz. You'll also need to change the Transient Analysis statement to
look like
.TRAN 0.1US 20US 0US 0.1US
Simulate the circuit and plot V(1), V(3) and V(4). What's happening to the once perfect
Vo at V(3)? How long does it take V(4) to swing positive enough to turn on D1? The
output distortion is especially noticeable for smaller input signals like 100 mV.
A Precision Full-Wave Rectifier
The precision rectifier, which is also known as a super diode, is a configuration

obtained with an operational amplifier in order to have a circuit behaving like an ideal
diode or rectifier.[1] It can be useful for high-precision signal processing.
The basic circuit implementing such a feature is shown on the right, where RL can be any
load. When the input voltage is negative, there is a negative voltage on the diode, too, so
it works like an open circuit, there is no current in the load and the output voltage is zero.
When the input is positive, it is amplified by the operational amplifier and it turns the
diode on. There is current in the load and, because of the feedback, the output voltage is
equal to the input.
In fact the threshold of the super diode is not actually zero, as it should be for an ideal
one, but it equals the threshold of the normal diode divided by the gain of the operational
amplifier, that is almost zero.
This basic configuration has a problem so it is not commonly used: when the input
becomes (even sightly) negative, the output of the operational amplifier can easily
become greater than the voltage supplied to the op-amp, thus causing saturation. Then, if
the input becomes positive again, the op-amp has to get out of the saturation to amplify
again. This change takes some time, and this greatly reduces the frequency response of
the circuit.
MPROVED CIRCUIT
An improved precision rectifier circuit.
An alternative version is given on the right.
In this case, when the input is greater than zero, D1 is OFF and D2 is ON, so the output is
zero, because one side R2 is connected to the virtual ground, and there is no current
through it. When the input is less than zero, D1 is ON and D2 is OFF, and the output is
like the input with an amplification of − R2 / R1. Its transfer characteristic is the
following:
This circuit has the benefit that the op-amp never goes in saturation, so the only thing
affecting its frequency response is the amplification and the gain-bandwidth product.
Similar circuitry can be used to create a precision full-wave rectifier circuit.
PEAK DETECTOR
With little modifications basic precision rectifier can be used also for detecting peak
levels of signal. In the following circuit a capacitor keeps the peak voltage level of signal
and switch can be used for resetting detected level.
THE HALF-WAVE RECTIFIER KEPT ONLY THOSE PARTS OF THE ORIGINAL INPUT SIGNAL THAT
WERE POSITIVE (OR NEGATIVE). IS THERE A WAY TO KEEP BOTH HALVES OF THE INPUT
SIGNAL, AND YET RENDER THEM BOTH WITH THE SAME OUTPUT POLARITY? THIS IS THE
BEHAVIOR OF A FULL-WAVE RECTIFIER.
THE CIRCUIT SHOWN ABOVE PERFORMS FULL-WAVE RECTIFICATION ON THE INPUT SIGNAL,
AS SHOWN. IF YOU WISH THE FINAL OUTPUT TO BE POSITIVE INSTEAD OF NEGATIVE, SIMPLY
REVERSE THE TWO DIODES IN THE HALF-WAVE RECTIFIER SECTION.
THE FULL-WAVE RECTIFIER DEPENDS ON THE FACT THAT BOTH THE HALF-WAVE RECTIFIER
AND THE SUMMING AMPLIFIER ARE PRECISION CIRCUITS. IT OPERATES BY PRODUCING AN
INVERTED HALF-WAVE-RECTIFIED SIGNAL AND THEN ADDING THAT SIGNAL AT DOUBLE
AMPLITUDE TO THE ORIGINAL SIGNAL IN THE SUMMING AMPLIFIER. THE RESULT IS A
REVERSAL OF THE SELECTED POLARITY OF THE INPUT SIGNAL.
THE RESISTOR VALUES SHOWN ARE REASONABLE; THE RESISTORS THEMSELVES MUST BE OF
HIGH PRECISION IN ORDER TO KEEP THE RECTIFICATION PROCESS ACCURATE. IF FOR SOME
REASON YOU MUST BUILD SUCH A CIRCUIT WITH A DIFFERENT SET OF RESISTANCE VALUES,
YOU MUST MAINTAIN THE INDICATED 2:1 RESISTANCE RATIO, AND YOU MUST STILL USE
PRECISION RESISTORS IN ORDER TO OBTAIN ACCURATE RESULTS.
OP AMP LIMITER
CIRCUIT
Suppose you've been asked to limit the maximum output voltage of an amplifier. Why?
Maybe the next stage will go up in smoke if its input swings beyond the maximum input
rating. Or, maybe an op amp output gets frequently slammed into a rail by a big input
signal. The recovery time can be long for some devices. To speed up recovery time, you
can limit the output voltage level before saturation is reached. But how? A zener diode
across the feedback resistor creates a fine limiting function. Unfortunately, for high
precision applications, the non-ideal characteristics of the zener diode can wreck circuit
accuracy. However, performance can be restored with a simple modification to the

topology.
LIMITING ACTION
During normal operation (no limiting), the op amp works like your basic inverting
amplifier. VS and R1 produce an input current I = VS / R1. (The negative input is at
virtual ground, or 0V.) This same I flows through feedback element R2 to develop the
output voltage, Vo = I ∙ R2. However, limiting occurs when the signal swings large
enough to force D1 and D2 to conduct. For positive signals, the clip level begins at
V LIM POS = Vf D2 + VZ D1
where Vf D2 is the forward diode voltage of D2 and VZ D1 is the zener voltage of D1.
Likewise, the negative clip level is set at
V LIM NEG = - ( Vf D1 + VZ D2 )
Above these levels the diodes conduct, clamping the output voltage to the same level.
CIRCUIT INSIGHT Run a simulation of OP_LIMITER1.CIR. Voltage source VS

drives the input of inverting amplifier to 10 Vpeak for an expected output of -10 Vpeak.
However, diodes D1 and D2 begin to conduct at V LIM POS or V LIM NEG, clipping
the output at this level. To see the limiter in action, plot V(1) and V(4)
HANDS-ON DESIGN Pick another zener diode from the collection and place it in the
circuit by typing a different model name in the diode statement. If both diodes D1 and D2
are the same device, you get symmetrical clipping. If you want asymmetrical clipping,
pick two different devices for D1 and D2. Try putting in a single zener diode, what will
output look like?
LEAKY DIODES
As expected, the world is an imperfect place, not the least being zener diodes. For reverse
voltages below the zener voltage, you'd expect the zener diode to be OFF and essentially
out of the circuit. Unfortunately, a small current leaks across the diode defined by the IS
parameter in the diode model. For the 1N746, the reverse leakage is specified at ILEAK
= 5 μA. This seemingly small leakage current can do nasty things to amplifier gain,
especially at low voltages.
CIRCUIT INSIGHT Change the input level of VS to 0.5 Vpeak and replace D1 and D2
with the 1N746 devices. We could naively expect to see -0.5 V peak at the output, but we
know better. Plot V(4) to see the less than spectacular gain performance due to zener
leakage.
Only 0.45 V at the output! Why? Remember VS and R1 set up an input current I = 0.5V /
10 kΩ
= 50 uA. Normally, this same I flows through R2 to develop the output Vo = 50 μA ∙ 10
kΩ = 0.5 V. However, not all of the 50 μA flows through R2. 5 μA leaks across the zener
diode leaving only 45 μA through R2 to produce 0.45 V!
HANDS-ON DESIGN The larger the value of R1, the smaller the I, and the bigger an
impact ILEAK has on the gain. Change R1 and R2 to something like 100 kΩ and watch
the effect. Alternatively, choose smaller values of R1 and R2, 1 kΩ or so, to minimize the
impact of zener leakage
ISOLATING LEAKAGE CURRENT
If reverse leakage is too troublesome, you can isolate it from the rest of the circuit. A
simple addition of two ordinary diodes and a resistor can save the day.
During normal operation (no limiting) the voltage across D3 and D4 is small. Why? First,
the op amp's negative input is at virtual ground (0V). Second, voltage across R3 is merely
the zener leakage current from flowing into R3, VR3 = 5 μA ∙ 10 kΩ = 50 mV. This
small voltage leaves D3 and D4 OFF! And, because these diodes typically have small
leakage currents, no significant current flows into the op amp's feedback element to
disturb the gain. The circuit essentially looks like this.
Diodes D3 and D4 effectively isolate the zener diodes from the amplifier. However,
when the output voltage swings beyond the following limits
V LIM POS = Vf D3 + Vf D2 + VZ D1
V LIM NEG = - ( Vf D4 +Vf D1 + VZ D2 )
the diodes begin to conduct, clamping the voltage across R2.
CLAMP (CIRCUIT)
A clamp or clamp circuit is an electrical circuit used to prevent another circuit from
exceeding a certain predetermined voltage level. It operates by sensing the output voltage
of the monitored circuit and then as the output voltage approaches the preset limit,
applies an electric load which draws greater and greater current from the output in a
regulated manner in order to prevent the output voltage from exceeding the
predetermined voltage level. The clamp circuit works only if it has a lower output
impedance than the monitored circuit thereby overpowering that circuit. It is the circuit
which places either the positive or negative peak of a signal at the required direct current
level.
A clamp circuit has no memory -- when the voltage is significantly below the limit, the
clamp circuit always draws almost no current. (In this way it differs from a crowbar
circuit).
Alternatively a clamping circuit may also be defined as a circuit which inserts a DC

component into a signal. Perhaps the most common such clamping circuit is the DC
restorer circuit in analog television receiver, which returns the voltage of the signal
during the back porch of the line blanking period to 0V. Since the back porch is required
to be at 0V on transmission, any DC or low frequency humm that has been induced onto
the signal can be effectively removed via this method.
The network must have a capacitor, a diode and a resistive element, but it can also
employ an independent DC supply to introduce an additional shift. The magnitude of R
and C must be chosen so that t = RC is large enough to ensure that the voltage across the
capacitor does not discharge significantly during the diode's "Unconducting" interval.
The term voltage clamp is often used to refer to the clamp circuit.
SAMPLE AND HOLD
IN ELECTRONICS, A SAMPLE AND HOLD CIRCUIT IS USED TO INTERFACE REAL-WORLD

SIGNALS, BY CHANGING ANALOGUE SIGNALS TO A SUBSEQUENT SYSTEM SUCH AS AN
ANALOG-TO-DIGITAL CONVERTER. THE PURPOSE OF THIS CIRCUIT IS TO HOLD THE
ANALOGUE VALUE STEADY FOR A SHORT TIME WHILE THE CONVERTER OR OTHER
FOLLOWING SYSTEM PERFORMS SOME OPERATION THAT TAKES A LITTLE TIME.
IN MOST CIRCUITS, A CAPACITOR IS USED TO STORE THE ANALOGUE VOLTAGE, AND AN

ELECTRONIC SWITCH OR GATE IS USED TO ALTERNATELY CONNECT AND DISCONNECT THE
CAPACITOR FROM THE ANALOGUE INPUT. THE RATE AT WHICH THIS SWITCH IS OPERATED IS
THE SAMPLING RATE OF THE SYSTEM.
IN A SAMPLE AND HOLD CIRCUIT THE SWITCH OPENS FOR A VERY SHORT DURATION, WHILE
IN A TRACK AND HOLD CIRCUIT THE SWITCH CAN BE OPENED CONTINUOUSLY. THE SAMPLE
AND HOLD CIRCUIT INTEGRATES FOR A SHORT DURATION CHARGE INTO A CAPACITOR, A
TRACK AND HOLD CIRCUIT TRACKS THE SIGNAL PRECISELY AND THIS DOES NOT CHANGE ON
HOLD [1]. A SAMPLING OSCILLOSCOPE INCLUDES A VOLTAGE SOURCE TO CALIBRATE ITS
SAMPLE AND HOLD CIRCUIT. TRACK AND HOLD RELIES ON OPAMPS AND THUS WAS
HISTORICALLY LIMITED TO THE AUDIO RANGE, BUT AS OF 2008 THEY ARE AVAILABLE UP TO
10 MHZ[CITATION NEEDED]. SAMPLE AND HOLD CIRCUITS USE BACK TO BACK SCHOTTKY DIODES
OR DIODE RINGS AND SPECIAL PULSE SHAPING LINES TO DRIVE THESE SWITCHES AND
[CITATION NEEDED]
HISTORICALLY REACHED TO 1 GHZ, AND AS OF 2008 THEY REACH TO 20 GHZ .
SAMPLE TIMES.
SAMPLE AND HOLD.
THE NECESSITY OF SUCH A CIRCUIT IS EASY TO SEE IF ONE CONSIDERS WHAT WOULD
HAPPEN IF IT WERE NOT PRESENT. IN SOME KINDS OF ADC FOR EXAMPLE, THE INPUT IS
OFTEN COMPARED TO A VOLTAGE GENERATED INTERNALLY FROM A DIGITAL- TO-ANALOG
CONVERTER. THE CIRCUIT TRIES A SERIES OF VALUES, AND STOPS CONVERTING ONCE THE
VOLTAGES ARE "THE SAME" WITHIN SOME DEFINED ERROR MARGIN. IF THE INPUT VALUE
WAS PERMITTED TO CHANGE DURING THIS COMPARISON PROCESS, THE RESULTING
CONVERSION WOULD BE INACCURATE, AND POSSIBLY COMPLETELY UNRELATED TO THE
TRUE INPUT VALUE. SUCH SUCCESSIVE APPROXIMATION ADCS WILL OFTEN INCORPORATE
INTERNAL SAMPLE AND HOLD CIRCUITRY.
SAMPLE AND HOLD CIRCUITS ARE OFTEN USED WHEN MULTIPLE SAMPLES NEED TO BE
MEASURED AT THE SAME TIME. EACH VALUE IS SAMPLED AND HELD, USING A COMMON
SAMPLE CLOCK. THE VALUES CAN THEN BE READ AT LEISURE.
IN ORDER THAT THE INPUT VOLTAGE IS HELD CONSTANT FOR ALL PRACTICAL PURPOSES, IT
IS ESSENTIAL THAT THE CAPACITOR HAS VERY LOW LEAKAGE, AND THAT IT IS NOT LOADED
TO ANY SIGNIFICANT DEGREE WHICH CALLS FOR A VERY HIGH INPUT IMPEDANCE.
POSITIVE AND NEGATIVE PEAK DETECTOR CIRCUIT USING CA3130 OP-AMP
Implementing peak-detector circuits is very easy with the CA3130, as shown in

schematic diagram of this circuit. The figure below shows the schematic diagram of the
peak detector circuit. The upper section is peak-positive and the lower section is peak-
negative circuit.
Please note that with large-signal inputs, the bandwidth of the peak-negative circuit is
much less than that of the peak-positive circuit. In this case, the second stage of the
CA3130 limits the bandwidth. The time constant of peak-holding-time or peak-decay-
time is determined by the 100k resistor and the 5uF capacitor, you can modify their
values for different setting of this peak detector circuit.
UNIT -4
OPAMPS AND NONLINEAR CIRCUITS
Op-amps in switching circuits

zero crossing detectors
inverting Schmitt trigger circuits
non-inverting Schmitt circuits
astable multivibrator
monostable multivibrator
Op Amp Comparator with Hysteresis
CIRCUIT
The challenge sounds simple enough - take a 60 Hz (or 50 Hz) sinewave from the AC
power line and convert it to a square wave. This signal will serve as a clock to drive
counters for a 24 hour time clock. So you hook up an op amp as a comparator to do the
job. But your surprised to see the clock running too fast! With oscilloscope in hand you
discover the AC line is noisy! And to your horror, you see glitches (additional edges) at
the comparator's output, causing the counters to advance too quickly. What you need is a
better comparator, immune to the noise swinging above and below the comparator's
threshold.
SIMPLE COMPARATOR
The elementary comparator looks similar to circuit below.
You connect V- to ground (0V), then apply Vin to V+. (Since there's no current through
R1, VIN essentially appears at V+.) What happens at the output? In theory, when Vin >
V- = 0V, the output goes to a POSITIVE Output State. And, not surprising, when Vin <
V- = 0V, the output goes to a NEGATIVE Output State. Zener diodes D1 and D2 set the
positive and negative output levels: VP = Vf D1 + VZ D2 and VN = Vf D2 + VZ D1.
CIRCUIT INSIGHT VIN applies a 10V peak sinewave to the input. The output swings
to the POSITIVE and NEGATIVE States of +5 V and -5 V, respectively. Run a
simulation of OP_COMP.CIR. Plot the input V(2) and output V(6). It appears the
comparator performs well as a zero-crossing detector and all is right with the world.
However, the real world throws in a few "goodies" for free - mostly noise where you
need it the least. So let's add some noise by changing the VNOISE statement to read
1VPEAK instead of 0VPEAK. VNOISE adds a 1V @ 2.5 kHz sinewave ontop of our
pristine 60 Hz. Rerun the simulation and let's look at our output now. Unfortunately, our
fine square wave is rife chatter - it no longer provides one rising edge per 60 Hz cycle!
COMPARATOR WITH HYSTERESIS
How do we overcome the problems of the basic comparator? Just add some positive
feedback to the circuit.
Notice, how V+ is developed - its now a combination of the both the input VIN and the
output state Vo. This basically means that there are two thresholds: one when for a
POSITIVE Output State and another for the NEGATIVE Output State. (For now, assume
VREF = 0)
What are these two thresholds? Some simple math uncovers the answer. First, we need to
find the voltage at V+.
V+ = VIN ∙ R2/(R1 + R2) + Vo ∙ R1/(R1 + R2)
Next, recall that the op amp's switching threshold occurs at V+ = V- = 0. So the question
becomes, what value of VIN causes V+ = 0V. To accomplish this, we solve the above
equation for VIN when V+ = 0. The only tricky part lies in the fact that one of the
variables, Vo, can be in one of two states:
◊ POSITIVE Output State Vo = VP

◊ NEGATIVE Output State Vo = VN
So we solve the above equation first with Vo = VP and then Vo = VN. We get two
thresholds for VIN:
Vth+ = - VN ∙ R1 / R2
Vth- = - VP ∙ R1 / R2
In a nutshell, this is how the comparator operates.
To get to the POSITIVE Output State

Assume Vo = VN.
The input must rise above the threshold: VIN > Vth+
To get to the NEGATIVE Output State

Assume Vo = VP.
The input must fall below the threshold: VIN < Vth-
Having two thresholds based on both the input VIN and the current output state is called
hysteresis. As an example, suppose VP = +5V, VN = -5V, R1 = 1k and R2 = 5k. You get
two thresholds
Vth+ = - (-5V) ∙ 1k / 5k
= +1V
Vth- = - 5V ∙ 1k / 5k
= -1V
CIRCUIT INSIGHT Okay, let's see the two thresholds in action. Add R2 into the
picture by removing the comment character "*" before the R2 statement. Also return
VNOISE to 0VPEAK. Run a new simulation of OP_COMP.CIR and plot the input V(2)
and output V(6). Check it out! The output switches at VIN = 1 V on the way up, but,
switches state at VIN = -1 V on the way down.
So why go through all this trouble of creating two thresholds? Here's why. Just add some
noise back onto our 60 Hz by changing the VNOISE amplitude parameter to 1VPEAK.
Where has all the chatter gone? By choosing thresholds separated by a voltage larger than
the noise, the comparator's output produces a nice clean squarewave.
HANDS-ON DESIGN Return VNOISE back to 0VPEAK. Choose different values for
R1 and R2. and rerun the SPICE file. Does the comparator switch where you expect?
You can change the voltage levels of VP and VN by changing the zener diode's reverse
voltage parameter BV. Also, no one says that VP and VN must be equal and opposite.
Now add some noise onto the circuit. What's the largest noise the circuit can tolerate
before unwanted edges appear?
POSITIVE FEEDBACK AND SLOW MOVING INPUTS
The powerful advantage of hysteresis has been brought to you by positive feedback. The
R2, R1 combo feeds some of the output back to the positive input. Not only does it
provide two thresholds, but it also helps the V+ input swing faster through the V+ = V-
region - even for slow moving inputs! How? First, let's imagine a circuit without positive
feedback. Now, if VIN happens to be hovering slowly around 0V, then Vo may hover
between VN and VP (that's because V+ ≈ V- = 0 and op amp has finite gain.) Bad news!
However, positive feedback improves things. Suppose a rising input causes the output to
begin swinging positive. Now, the positive feedback delivers some of this positive swing
back to V+ helping it swing faster through the op amp's transition point of V+ = V-.
THE HYSTERESIS LOOP
Can SPICE show us the classic "hysteresis loop" for this comparator? Hopefully, your
SPICE version allows it. First, plot the output V(6). Next, change the X Axis variable
from time to the input V(2). What does this hysteresis loop mean? Here's a quick tour.
1. The bottom left corner indicates that for an input of X = -10V, you get an output
Y = -5V. As the input X increases (moving right) the output Y remains at -5V.
2. Eventually, X reaches Vth+ = +1V and Y jumps to +5V and stays there even though X
increases to +10V (moves right). Also, notice that Y does not change to +5V at
Vth- = -1V.
3. The upper right corner indicates that for an input of X = +10V, you get an output
Y = +5V. As X decreases (moving left), Y stays at +5 V
4. When, X reaches Vth- = -1V, the output Y swings to -5V. Again, notice that Y does
not change states at Vth+ = +1V.
In summary, Y can only swing positive at Vth+ and negative at Vth- thereby creating the
hysteresis loop.
ADDING VREF
You can add more flexibility to your comparator by adding a reference voltage VREF to
the op amp's negative input. Actually, its been there all along, just set to 0V. VREF let's
you place the thresholds more freely - they can now both be positive or negative.
Basically, VREF can shift the thresholds up or down as shown in the equation.
Vth+ = VREF ∙ (R1+R2)/R2 - VN ∙ R1 / R2

Vth- = VREF ∙ (R1+R2)/R2 - VP ∙ R1 / R2
SPREADSHEET Here's an Excel Spreadsheet - Opamp_Comp.xls - to help you with

some basic calculations. If your not using VREF, just set it to 0V. If your using a
standard comparator with an output of say 0 to 5V, simply set VN = 0 and VP = 5.
HANDS-ON DESIGN Pick a value for VREF. Run a simulation and check your new
thresholds. Do they match what your calculations predicted?
THE INVERTING COMPARATOR
What if you need an inverting comparator? Just swap the VIN and VREF locations and
you ready to go.
SCHMITT TRIGGER
In electronics, a Schmitt trigger is a comparator circuit that incorporates positive

feedback.
When the input is higher than a certain chosen threshold, the output is high; when the
input is below another (lower) chosen threshold, the output is low; when the input is
between the two, the output retains its value. The trigger is so named because the output
retains its value until the input changes sufficiently to trigger a change. This dual
threshold action is called hysteresis, and implies that the Schmitt trigger has some
memory.
The benefit of a Schmitt trigger over a circuit with only a single input threshold is greater
stability (noise immunity). With only one input threshold, a noisy input signal near that
threshold could cause the output to switch rapidly back and forth from noise alone. A
noisy Schmitt Trigger input signal near one threshold can cause only one switch in output
value, after which it would have to move beyond the other threshold in order to cause
another switch.
INVENTION
The Schmitt trigger was invented by US scientist Otto H. Schmitt in 1934 while he was
still a graduate student,[1] later described in his doctoral dissertation (1937) as a
"thermionic trigger".[2] It was a direct result of Schmitt's study of the neural impulse
propagation in squid nerves.
SYMBOL
The symbol for Schmitt triggers in circuit diagrams is a triangle with a hysteresis symbol.
The symbol depicts a typical hysteresis curve.
Standard Schmitt trigger
COMPARATOR IMPLEMENTATION
Today Schmitt triggers are typically built around comparators, connected to have positive
feedback instead of the usual negative feedback. For this circuit the switching occurs near
ground, with the amount of hysteresis controlled by the resistances of R1 and R2:
The comparator gives out the highest voltage it can, +VS, when the non-inverting (+)
input is at a higher voltage than the inverting (-) input, and then switches to the lowest
output voltage it can, −VS, when the positive input drops below the negative input. For
very negative inputs, the output will be low, and for very positive inputs, the output will
be high, and so this is an implementation of a "non-inverting" Schmitt trigger.
For instance, if the Schmitt trigger is currently in the high state, the output will be at the
positive power supply rail (+V S). V+ is then a voltage divider between Vin and +VS. The
comparator will switch when V+=0 (ground). Current conservation shows that this
requires
and so Vin must drop below to get the output to switch. Once the comparator
output has switched to −VS, the threshold becomes to switch back to high.
So this circuit creates a switching band centered around zero, with trigger levels
. The input voltage must rise above the top of the band, and then below the bottom of the
band, for the output to switch on and then back off. If R1 is zero or R2 is infinity (i.e., an
open circuit), the band collapses to zero width, and it behaves as a standard comparator.
The output characteristic is shown in the picture on the right. The value of the threshold T
is given by and the maximum value of the output M is the power supply rail.
A possible structure of a more realistic configuration is the following:
The output characteristic has exactly the same shape of the previous basic configuration
and the threshold values are the same as well. On the other hand, in the previous case the
output voltage was depending on the power supply, while now it is defined by the Zener
diodes: this way the output can be modified and it is much more stable. The resistor R3 is
there to limit the current through the diodes, while R4 is there to minimize the input
voltage offset caused by the op-amp's input bias currents (see Limitations of real op-
amps).
The comparator-based implementation of a relaxation oscillator is shown below.
Here, a comparator-based Schmitt trigger is used in its inverting configuration. That is,
the input and ground are swapped from the Schmitt trigger shown above, and so very
negative signals correspond to a positive output and very positive signals correspond to a
negative output. Additionally, slow negative feedback is added with an RC network. The
result, which is shown on the right, is that the output automatically oscillates from VSS to
VDD as the capacitor charges from one Schmitt trigger threshold to the other.
OPERATIONAL AMPLIFIER MULTIVIBRATOR OSCILLATOR CIRCUIT
- circuit and design details for a simple multivibrator oscillator using a single op
amp or oeprational amplifier.
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OPERATIONAL AMPLIFIER MULTIVIBRATOR OSCILLATOR CIRCUIT
- circuit and design details for a simple multivibrator oscillator using a single op
amp or oeprational amplifier.
Multivibrator oscillators are used in many circuits and they are simple to construct. It is
possible to construct them using a couple of transistors, but it is also possible to construct
a very simple multivibrator oscillator circuit using an operational amplifier. The circuit
can be used in a variety of applications where a simple square wave oscillator circuit is
required.
The use of an operational amplifier integrated circuit is ideal from many viewpoints.
Although circuits can be made using just two transistors, operational amplifiers are also
very cheap these days, and there is often little to choose in terms of cost.
The operational amplifier multivibrator circuit comprises two sections. The feedback to
the capacitor is provided by the resistor R1, whereas hysterisis is provided by the two
resistors R2 and R3.
Operational amplifier multivibrator oscillator
The time period for the oscillation is provided by the formula:
T = 2 C R1 loge (1 + 2 R2 / R3)
Although many multivibrator circuits may be provided using simple logic gates, this
circuit has the advantage that it can be used to provide an oscillator that will
generate a much higher output than that which could come from a logic circuit
running from a 5 volt supply. In addition to this the multivibrator oscillator circuit
is very simple, requiring just one operational amplifier ( op amp ), three resistors,
and a single capacitor.
Op-Amp Monostable Multivibrator
Figure 1. Op-Amp Monostable Multivibrator Circuit Diagram
This is a monostable multivibrator circuit that employs a single op amp. The main
component of this circuit is the 741, a general-purpose operational amplifier. A
monostable multivibrator is a timing circuit that changes state once triggered, but
returns to its original state after a certain time delay. It got its name from the fact
that only one of its output states is stable. It is also known as a 'one-shot'.
A negative trigger pulse at the input forces the output of the op amp to logic 'high'.
This charges up C2 which keeps the non-inverting input of the op amp temporarily
higher than the inverting input, maintaining the output high for a certain period of
time. Eventually C2 discharges to ground and the op amp output swings back to
logic 'low'. The duration of the pulse is defined by R2 and C2. The 'one-shot' has
several applications, which include dividing the frequency of the input signal and
converting an irregular input pulse to a uniform output pulse.
UNIT -5
Triangular/rectangular wave generator

waveform generator design
phase shift oscillator
oscillator amplitude stabilization
Wein bridge oscillator
signal generators
output controllers
Op Amp Integrator
CIRCUIT
The integrator basically works like this: whatever current I you get flowing in R1, gets
integrated across capacitor C1. The output voltage Vo is simply the voltage across C1.
One great application of the integrator is generating a ramp voltage. You can do this by
placing a fixed voltage at VS that forces a constant current through R1. The capacitor
then integrates this current creating a ramping voltage. The action is just like a garden
hose running water at a constant rate causing the level in a bucket to rise steadily. The
smaller the diameter bucket (smaller capacitor), the faster the increase in water level
(greater voltage). The switch is needed to discharge the capacitor (empty the bucket) at
the end of a ramping cycle.
RAMP GENERATOR
The circuit essentially integrates the input current Is = VS / R1 across capacitor C1.
After a time interval T, the output is the capacitor voltage described by
If you apply a constant voltage at VS, the output voltage increases steadily (ramp). You
can predict the ramp's voltage at any time T by the simplified equation
CIRCUIT ANALYSIS Try the circuit. What is the output voltage V(3) after 100us?
With VS= -1, R1=10k and C1 = 1nF, the output should be Vo = -1/1nF x (-1/ 10k) x
100us = 1V.
Look at the switch control voltage VRESET at V(4). VRESET turns the switch OFF
(VRESET=0V) and ON (VRESET=5V). Switch S1 is initially OFF. After 100us, S1
turns ON discharging the capacitor for 10us. Then, the ramping cycle begins again.
HANDS-ON DESIGN Design a circuit that ramps faster or slower than the original
circuit. The equation above tells you that you can change VS, R1 or C1 to achieve your
goal. (Example: For a slower ramp that reaches only 5V in 100us, make R1 equal to 2x
its initial value. This cuts the current through R1 by ½ decreasing the ramp rate by ½. )
You may have noticed that this is an inverting circuit; a negative VS creates a positive
output. Need to create a create a negative ramp? Apply a positive VS.
Op Amp Triangle-Wave Generator
CIRCUIT
This signal generator gives you two waveforms for the price of one: a triangle-wave and
a square-wave. What is the central component of this circuit? The integrator capacitor CI.
Basically we are interested in performing two functions on CI: charge it, discharge it -
repeat indefinitely. During the design process, we ask these essential questions
1. How do we charge/discharge CI?

2. How fast do we charge/discharge CI?
3. How do we switch from charging to discharging?
4. When do we switch from charging to discharging and visa-versa?
Most likely, there are scores of circuit options for every question. It all depends on the
usual design context - budget, required accuracy, schedule, available components,
personal experience and so on. Here's one simple incarnation of the triangle wave
generator.
LINEAR RAMPS
How do we charge / discharge CI? A triangle wave implies that our circuit generates a
linear voltage ramp. One way to achieve this goal is by charging / discharging CI with a
constant current. The Op Amp Integrator provides a handy way to accomplish this. Here's
a simplified version of the circuit.
Ramp Up Connect RI to VN and what happens? With V- held at the virtual

ground (0V), a constant current flows from V- to VN.
Iin = VN / RI.
CI integrates Iin creating a positive linear ramp at Vo. The ramp is linear because Vo
changes proportionally to the time elapsed ΔT.
ΔVo = - VN / (CI ∙ RI) ∙ ΔT
Ramp Down Connect RI to VP and a constant current flows from VP to V-,

Iin = - VP / RI. Now Vo ramps down linearly
ΔVo = - VP / (CI ∙ RI) ∙ ΔT
How Fast? To control the period of the generator, you need to answer this - how fast
does Vo ramp up and down? Just look at the above equations and solve for ΔVo / ΔT.
Ramp Up: ΔVo / ΔT = - VN / ( CI ∙ RI )

Ramp Down: ΔVo / ΔT = - VP / ( CI ∙ RI )
These equations show you the parameters available to control the ramp up / down
speeds.
UPPER AND LOWER BOUNDS
When do we switch from charging to discharging CI? Basically, you need to pick two
levels - an upper and a lower threshold - to define the bounds of the triangle wave. The
circuit ramps up or down, reversing at the upper and lower thresholds.
With one leg of RI at VN, the output ramps up until the Upper Threshold (
Vth+ ) is reached. Then RI is switched from VN to VP.
With one leg of RI at VP, the output ramps down until the Lower Threshold (
Vth- ) is reached. Then RI is switched from VP to VN.
COMPARATOR
And for our final question: how do we switch from ramping up to ramping down? Our
goal is to replace the switch and VP/VN levels in the simplified circuit above. Here's one
way to do it - an Op Amp Comparator with two thresholds. This simple yet wondrous
circuit changes it's output state from VN to VP (or vise-versa) depending on the upper
Vth+ and lower Vth- thresholds.
Vth+ = - VN ∙ R1 / R2
Vth- = - VP ∙ R1 / R2
How does it work?
o When Vin > Vth+, the output switches to VP, the POSITIVE output state.
o When Vin < Vth-, the output switches to VN, the NEGATIVE output state.
Zener diodes D1 and D2 set the positive and negative output levels:
VP = Vf D1 + VZ D2
VN = Vf D2 + VZ D1.
These output levels do double duty! Not only do they set the comparator thresholds, but
also set the voltage levels for the next stage - the integrator.
TRIANGLE WAVE GENERATOR
HANDS-ON DESIGN Okay, time to design it, built it and simulate it! Suppose our
design calls for a +/-10 V triangle wave, cruising along at 10 kHz. This means that Vth+
= +10 V and Vth- = -10 V. Given VP = +5 V, VN = -5 V, let's choose R2 = 10 kΩ and
then calculate R1 = 20 kΩ from the equation above.
Now, if you have a 1 nF cap in stock, then what value of RI is needed for 10 kHz (T =
100 μs)? Because Vo needs to swing ΔVo = 10 - (-10) = 20 V in an interval ΔT = 50 μs,
we solve the above equation in the Linear Ramps section for RI.
RI = (VP / CI ) ∙ (ΔT / ΔVo)

= (5 V / 1 nF) ∙ (50 μs / 20 V)
= 12.5 kΩ
Run a SPICE simulation of OP_TRI_GEN.CIR. Plot the triangle-wave output V(3) and
the comparator output V(1). I don't know why, but I get a strange satisfaction out of
watching the output ramping up and down on its own!
Want to speed up or slow down the action? Just change the current source level by
doubling or halving RI. Run a new simulation and watch it go. Need a different peak to
peak voltage swing? Simply raise or lower R1. But beware - changing the voltage
thresholds also changes the time required to reach the thresholds. Also, make sure Vth+
and Vth- are not outside the +/-15V limits of the op amp model!
And don't forget the option of changing the reverse voltage of the zener diode via the BV
parameter. Just remember the charging currents and thresholds will change too.
HOW ACCURATE?
You may have noticed that the triangle peaks and period may not accurately meet our +/-
10V swing at 100 us. Why? The main reason is that our current source and thresholds
are derived from zener diodes - not exactly the most accurate reference on the planet!
You may need to spend a few bucks on trim pots for both R1 and RI. Other options for
improving accuracy include bringing in some precision references for VP and VN. Some
designs use improved means for deriving and switching the current sources that charge
CI.
ASYMMETRICAL VOLTAGES
You can create asymmetrical voltage swings by including a reference voltage VREF to
the comparator's negative input. (Actually, its been there all along, just set to 0V.) VREF
let's you place the thresholds more freely - they can now both be positive or negative.
Basically, VREF can shift the thresholds up or down as shown in the equation.
Vth+ = VREF ∙ (R1+R2)/R2 - VN ∙ R1 / R2

Vth- = VREF ∙ (R1+R2)/R2 - VP ∙ R1 / R2
HANDS-ON DESIGN Pick new thresholds by including VREF. For example, set R1 =
R2 = 10k and VREF = 2.5 V. Run a new simulation and check your new triangle
boundaries. Again, make sure your Vth+ and Vth- are not outside the +/-15V limits of the
op amp model!
ASYMMETRICAL RAMPS
Good news! You're not confined to equal ramp up and down rates. For this trick, create a
new voltage source VREF2 and connect it to the integrator's positive input. For example,
add VREF and change XOP1 to look like this.
XOP1 9 2 3 OPAMP1
VREF2 9 0 2V
What does this do? Now you've got two different current-source levels to charge CI.
Iin+ = ( VP - V+) / RI.

Iin- = (VN - V+) / RI.
For example, set VREF2 to a voltage like 2V. With VREF2 = 2V, VP = 5V, VN = -5 V
and RI = 12.5 kohms, you get unequal constant currents of Iin+ = -0.24 mA and Vin- =
0.56 mA. Rerun the simulation. You're triangle wave should start looking like sawtooth.
Op Amp Square Wave Generator
Figure 1. Square Wave Generator Circuit Diagram
This is a square wave generator circuit. The main component of this circuit is the
741, a general-purpose operational amplifier. This circuit employs a single power
supply Vs that can range from +5V to +15V.
The square wave output of this circuit is easy to adjust. 'Timing' is defined by C1,
R4, R5, R6, and R7 while duration is defined by R1, R2, and R3. Pulse symmetry
is achieved by making the resistance from pin 3 to ground equal to the resistance
from pin 3 to Vs. If this is desired, then R1, R2, and R3 may simply be replaced
by two equal resistors from pin 3, one of which is tied to Vs while the other is tied
to ground.
PHASE-SHIFT OSCILLATOR
A phase-shift oscillator is a simple sine wave electronic oscillator. It contains an

inverting amplifier, and a feedback filter which 'shifts' the phase by 180 degrees at the
oscillation frequency.
The filter must be designed so that at frequencies above and below the oscillation
frequency the signal is shifted by either more or less than 180 degrees. This results in
constructive superposition for signals at the oscillation frequencies, and destructive
superposition for all other frequencies.
The most common way of achieving this kind of filter is using three cascaded resistor-
capacitor filters, which produce no phase shift at one end of the frequency scale, and a
phase shift of 270 degrees at the other end. At the oscillation frequency each filter
produces a phase shift of 60 degrees and the whole filter circuit produces a phase shift of
180 degrees.
OP. AMP. IMPLEMENTATION
One of the simplest implementations for this type of oscillator uses an operational
amplifier (op-amp), three capacitors and four resistors, as shown in the diagram.
The mathematics for calculating the oscillation frequency and oscillation criterion for this
circuit are surprisingly complex, due to each R-C stage loading the previous ones. The
calculations are greatly simplified by setting all the resistors (except the negative
feedback resistor) and all the capacitors to the same values. In the diagram, if R1 = R2 =
R3 = R, and C1 = C2 = C3 = C, then:
and the oscillation criterion is:
Without the simplification of all the resistors and capacitors having the same value, the
calculations become more complex:
Oscillation criterion:
Another version of this circuit can be made by putting an op-amp buffer between each R-
C stage which simplifies the calculations. Тhe voltage gain of the inverting channel is
always unity.
WIEN BRIDGE OSCILLATOR
A Wien bridge oscillator is a type of electronic oscillator that generates sine waves. It
can generate a large range of frequencies. The circuit is based on an electrical network
originally developed by Max Wien in 1891. The bridge comprises four resistors and two
capacitors. It can also be viewed as a positive feedback system combined with a bandpass
filter. Wien did not have a means of developing electronic gain so a workable oscillator
could not be realized.
The modern circuit is derived from William Hewlett's 1939 Stanford University master's
degree thesis. Hewlett, along with David Packard co-founded Hewlett-Packard. Their
first product was the HP 200A, a precision sine wave oscillator based on the Wien bridge.
The 200A was one of the first instruments to produce such low distortion.
The frequency of oscillation is given by:
AMPLITUDE STABILIZATION
The key to Hewlett's low distortion oscillator is effective amplitude stabilization. The
amplitude of electronic oscillators tends to increase until clipping or other gain limitation
is reached. This leads to high harmonic distortion, which is often undesirable.
Hewlett used an incandescent bulb as a positive temperature coefficient (PTC) thermistor

in the oscillator feedback path to limit the gain. The resistance of light bulbs and similar
heating elements increases as their temperature increases. If the oscillation frequency is
significantly higher than the thermal time constant of the heating element, the radiated
power is proportional to the oscillator power. Since heating elements are black body
radiators, they follow the Stefan-Boltzmann law. The radiated power is proportional to
T4, so resistance increases at a greater rate than amplitude. If the gain is inversely
proportional to the oscillation amplitude, the oscillator gain stage reaches a steady state
and operates as a near ideal class A amplifier, achieving very low distortion at the
frequency of interest. At lower frequencies the time period of the oscillator approaches
the thermal time constant of the thermistor element and the output distortion starts to rise
significantly.
Light bulbs have their disadvantages when used as PTC thermistors in Wien bridge
oscillators, most notably a very high sensitivity to vibration due to the bulbs microphonic
nature amplitude modulating the oscillator output, and a limitation in high frequency
response due to the inductive nature of the coiled filament. Bead thermistors perform
much better than light bulbs in these respects, but are many times more expensive.
Wien bridge oscillators that use thermistor elements as gain control devices also exhibit
"amplitude bounce" when the oscillator frequency is changed. This is due to the low
damping factor and long time constant of the crude control loop, and disturbances cause
the output amplitude to exhibit a decaying sinusoidal response. This can be used as a
rough figure of merit, as the greater the amplitude bounce after a disturbance, the lower
the output distortion under steady state conditions.
Modern Wien bridge oscillators have used field effect transistors or photocells for
amplitude stabilization in place of light bulbs. Distortion as low as 0.0008% (8 parts per
million) can be achieved with only modest improvements to Hewlett's original circuit.
Other ways of stabilizing the amplitude include using non-linear elements, such as diodes
or thermistors, to modify the gain of the negative feedback network.
ANALYSIS
f a voltage source is applied directly to the input of an ideal amplifier with feedback, the
input current will be:
Where vin is the input voltage, vout is the output voltage, and Zf is the feedback impedance.
If the voltage gain of the amplifier is defined as:
And the input admittance is defined as:
Input admittance can be rewritten as:
For the Wien bridge, Zf is given by:
If Av is greater than 1, the input admittance is a negative resistance in parallel with an

inductance. The inductance is:
If a capacitor with the same value of C is placed in parallel with the input, the circuit has
a natural resonance at:
Substituting and solving for inductance yields:
If Av is chosen to be 3:
Lin = R2C
Substituting this value yields:
Or:
Similarly, the input resistance at the frequency above is:
For Av = 3:
Rin = − R
If a resistor is placed in parallel with the amplifier input, it will cancel some of the
negative resistance. If the net resistance is negative, amplitude will grow until clipping
occurs. Similarly, if the net resistance is positive, oscillation amplitude will decay. If a
resistance is added in parallel with exactly the value of R, the net resistance will be
infinite and the circuit can sustain stable oscillation at any amplitude allowed by the
amplifier.
Notice that increasing the gain makes the net resistance more negative, which increases
amplitude. If gain is reduced to exactly 3 when a suitable amplitude is reached, stable,
low distortion oscillations will result. Amplitude stabilization circuits typically increase
gain until a suitable output amplitude is reached. As long as R, C, and the amplifier are
linear, distortion will be minimal.
UNIT -6
ACTIVE FILTERS
First and second order high pass and low pass filters
band pass filter
band stop filter
Frequency Response and Active Filters
This document is an introduction to frequency response, and an introduction to active

filters (filters using active amplifiers, like op amps). You might also want to read a
similar document from National Semiconductor, A Basic Introduction to Filters - Active,
Passive, and Switched-Capacitor.
Frequency Response -- Background
Up to now we have looked at the time-domain response of circuits. However it is often

useful to look at the response of circuits in the frequency domain. In other words, you
want to look at how circuits behave in response to sinusoidal inputs. This is important
and useful for several reasons: 1) if the input to a linear circuit is a sinusoid, then the
output will be a sinusoid at the same frequency, though its amplitude and phase may have
changed, 2) any time domain signal can be decomposed via Fourier analysis into a series
of sinusoids. Therefore if there is an easy way to analyze circuits with sinusoidal inputs,
the results can be generalized to study the response to any input.
To determine the response of a circuit to a sinusoidal signal as a function of frequency it

is possible to generalize the concept of impedance to include capacitors and inductors.
Consider a sinusoidal signal represented by a complex exponential:
where j=-1)1/2 (engineers use j instead of i, because i is used for current),  is frequency
and t is time. It is a common shorthand to use "s" instead of "j".
Now let us look at the voltage-current relationships for resistors capacitors and inductors.
For a resistor ohms law states:
where we define the impedance, "Z", of a resistor as its resistance "R".
For a capacitor we can also calculate the impedance assuming sinusoidal excitation
starting from the current-voltage relationship:
Note that for a capacitor the magnitude of the impedance, 1/C, goes down with
increasing frequency. This means that at very high frequencies the capacitor acts as an
short circuit, and at low frequencies it acts as an open circuit. What is defined as a high,
or low, frequency depends on the specific circuit in question.
Likewise, for an inductor you can show that Z=sL.
For an inductor, impedance goes up with frequency. It behaves as a short circuit at low
frequencies, and an open circuit at high frequencies; the opposite of a capacitor. However
inductors are not used often in electronic circuits due to their size, their susceptibility to
parisitic effects (esp. magnetic fields), and because they do not behave as near to their
ideal circuit elements as resistors and capacitors..
A Simple Low-Pass Circuit
To see how complex impedances are used in practice consider the simple case of a
voltage divider.
If Z1 is a resistor and Z2 is a capacitor then
Generally we will be interested only in the magnitude of the response:
Recall that the magnitude of a complex number is the square root of the sum of the
squares of the real and imaginary parts. There are also phase shifts associated with the
transfer function (or gain, Vo/Vi), thought we will generally ignore these.
This is obviously a low pass filter (i.e., low frequency signals are passed and high
frequency signals are blocked).. If «1/RC then CR«1 and the magnitude of the gain is
approximately unity, and the output equals the input. If »1/RC (CR»1 ) then the gain
goes to zero, asdoes the output. At =1/RC, called the break frequency (or cutoff
frequency, or 3dB frequency, or half-power frequency, or bandwidth), the magnitude of
the gain is 1/sqrt(20.71. In this case (and all first order RC circuits) high frequency is
defined as »1/RC; the capacitor acts as a short circuit and all the voltage is across the
resistance. At low frequencies, «1/RC, the capacitor acts as an open circuit and there is
no current (so the voltage across the resistor is near zero).
If Z1 is an inductor and Z2 is a resistor another low pass structure results with a break
frequency of R/L.
A Simple High-Pass Circuit
If Z1 is a capacitor and Z2 is a resistor we can repeat the calculation:
and
At high frequencies, »1/RC, the capacitor acts as a short and the gain is 1 (the signal is
passed). At low frequencies, «1/RC, the capacitor is an open and the output is zero (the
signal is blocked). This is obviously a high pass structure and you can show that the
break frequency is again 1/RC.
If Z1 is a resistor and Z2 is an inductor the resulting circuit is high pass with a break
frequency of R/L.
This concept of a complex impedance is extremely powerful and can be used when
analyzing operational amplifier circuits, as you will soon see.
Active Filters
Low-Pass filters - the integrator reconsidered.
In the first lab with op-amps we considered the time response of the integrator circuit, but
its frequency response can also be studied.
First Order Low Pass Filter with Op Amp
If you derive the transfer function for the circuit above you will find that it is of the form:
which is the general form for first-order (one reactive element) low-pass filters. At high
frequencies (>>o) the capacitor acts as a short, so the gain of the amplifier goes to
zero. At very low frequencies (<<o) the capacitor is an open and the gain of the circuit
is Ho. But what do we mean by low (or high) frequency?
We can consider the frequency to be high when the large majority of current goes
through the capacitor; i.e., when the magnitude of the capacitor impedance is much less
than that of R1. In other words, we have high frequency when 1/C<<R1, or
>>1/R1C=o. Since R1 now has little effect on the circuit, it should act as an integrator.
Likewise low frequency occurs when <<1/R1C, and the circuit will act as an amplifier
with gain -R1/R2= Ho.
High-Pass filters - the differentiator reconsidered.
The circuit below is a modified differentiator, and acts as a high pass filter.
First Order High Pass Filter with Op Amp
Using analysis techniques similar to those used for the low pass filter, it can be shown
that
which is the general form for first-order (one reactive element) low-pass filters. At high
frequencies (>>o) the capacitor acts as a short, so the gain of the amplifier goes to
H0= -R1/R2. At very low frequencies (<<o) the capacitor is an open and the gain of
the circuit is Ho. For this circuit 0=1/R2C. Therefore this circuit is a high-pass filter (it
passes high frequency signals, and blocks low frequency signals.
Band-Pass circuits
Besides low-pass filters, other common types are high-pass (passes only high frequency
signals), band-reject (blocks certain signals) and band-pass (rejects high and low
frequencies, passing only signal areound some intermediate frequency).
The simplest band-pass filter can be made by combining the first order low pass and high
pass filters that we just looked at.
Simple Band Pass Filter with Op Amp
This circuit will attenuate low frequencies (<<1/R2C2) and high frequencies
(>>1/R1C1), but will pass intermediate frequencies with a gain of -R1/R2. However,
this circuit cannot be used to make a filter with a very narrow band. To do that requires a
more complex filter as discussed below.
High Q (Low Bandwidth) Bandpass Filters.
For a second-order band-pass filter the transfer function is given by
where o is the center frequency,  is the bandwidth and Ho is the maximum amplitude
of the filter. These quantities are shown on the diagram below. The quantities in
parentheses are in radian frequencies, the other quantities are in Hertz (i.e. f o=o/2,
B=/2). Looking at the equation above, or the figure, you can see that as 0 and  -
>infinitythat |H(s=j)|0. You can also easily show that at = o that |H(s=jo)|=H0.
Often you will see the equation above written in terms of the quality factor, Q, which can
be defined in terms of the bandwidth, , and center frequency, o, as Q=o/. Thus the
Q, or quality, of a filter goes up as it becomes narrower and its bandwidth decreases.
If you derive the transfer function of the circuit shown below:
High-Q Bandpass Filter with Op Amp
you will find that it acts as a band-pass filter with:
and the center frequency and bandwidth given by:
Radian frequency Hertz
The notation R1||R2 denotes the parallel combination of R1 and R2,
Switched Capacitor Filters
There is a special type of active filter, the switched capacitor filter, that takes advantage
of integration to achieve very accurate filter characteristics that are electronically
tuneable. The page Switched Capacitor Filters describes these in more detail.
BUTTERWORTH FILTER
The Butterworth filter is one type of electronic filter design. It is designed to have a
frequency response which is as flat as mathematically possible in the passband. Another
name for it is maximally flat magnitude filter.
The Butterworth type filter was first described by the British engineer Stephen
Butterworth in his paper "On the Theory of Filter Amplifiers", Wireless Engineer (also
called Experimental Wireless and the Wireless Engineer), vol. 7, 1930, pp. 536-541.
OVERVIEW
The frequency response of the Butterworth filter is maximally flat (has no ripples) in the
passband, and rolls off towards zero in the stopband. When viewed on a logarithmic Bode
plot, the response slopes off linearly towards negative infinity. For a first-order filter, the
response rolls off at −6 dB per octave (−20 dB per decade) (all first-order lowpass filters
have the same normalized frequency response). For a second-order lowpass filter, the
response ultimately decreases at −12 dB per octave, a third-order at −18 dB, and so on.
Butterworth filters have a monotonically changing magnitude function with ω, unlike
other filter types that have non-monotonic ripple in the passband and/or the stopband.
Compared with a Chebyshev Type I/Type II filter or an elliptic filter, the Butterworth
filter has a slower roll-off, and thus will require a higher order to implement a particular
stopband specification. However, Butterworth filter will have a more linear phase
response in the passband than the Chebyshev Type I/Type II and elliptic filters.
A SIMPLE EXAMPLE
A simple example of a Butterworth filter is the 3rd order low-pass design shown in the
figure on the right, with C2 = 4 / 3 farad, R4 = 1 ohm, L1 = 3 / 2 and L3 = 1 / 2 henry.
Taking the impedance of the capacitors C to be 1/Cs and the impedance of the inductors
L to be Ls, where s = σ + jω is the complex frequency, the circuit equations yields the
transfer function for this device:
The magnitude of the frequency response (gain) G(ω) is given by:
and the phase is given by:
The group delay is defined as the derivative of the phase with respect to angular
frequency and is a measure of the distortion in the signal introduced by phase differences
for different frequencies. The gain and the delay for this filter are plotted in the graph on
the left. It can be seen that there are no ripples in the gain curve in either the passband or
the stop band.
The log of the absolute value of the transfer function H(s) is plotted in complex
frequency space in the second graph on the right. The function is defined by the three
poles in the left half of the complex frequency plane. These are arranged on a circle of
radius unity, symmetrical about the real s axis. The gain function will have three more
poles on the right half plane to complete the circle.
By replacing each inductor with a capacitor and each capacitor with an inductor, a high-
pass Butterworth filter is obtained. If we change each capacitor and inductor into a
resonant capacitor and inductor in parallel, with the proper choice of component values, a
band-pass Butterworth filter is obtained.
THE TRANSFER FUNCTION
Like all filters, the typical prototype is the low-pass filter, which can be modified into a
high-pass filter, or placed in series with others to form band-pass and band-stop filters,
and higher order versions of these.
The gain G(ω) of an n-order Butterworth low pass filter is given in terms of the transfer
function H(s) as:
where
n = order of filter
ωc = cutoff frequency (approximately the -3dB frequency)
G0 is the DC gain (gain at zero frequency)
It can be seen that as n approaches infinity, the gain becomes a rectangle function and
frequencies below ωc will be passed with gain G0, while frequencies above ω c will be
suppressed. For smaller values of n, the cutoff will be less sharp.
We wish to determine the transfer function H(s) where s = σ + jω. Since H(s)H(-s)
evaluated at s = jω is simply equal to |H(jω)|2, it follows that:
The poles of this expression occur on a circle of radius ω c at equally spaced points. The
transfer function itself will be specified by just the poles in the negative real half-plane of
s. The k-th pole is specified by:
and hence,
The transfer function may be written in terms of these poles as:
The denominator is a Butterworth polynomial in s.
Normalized Butterworth polynomials
The Butterworth polynomials may be written in complex form as above, but are usually
written with real coefficients by multiplying pole pairs which are complex conjugates,
such as s1 and sn. The polynomials are normalized by setting ωc = 1. The normalized
Butterworth polynomials then have the general form:
for n even
for n odd
To four decimal places, they are:
n Factors of Polynomial Bn(s)

1 (s + 1)
2 s2 + 1.4142s + 1
3 (s + 1)(s2 + s + 1)
4 (s2 + 0.7654s + 1)(s2 + 1.8478s + 1)
5 (s + 1)(s2 + 0.6180s + 1)(s2 + 1.6180s + 1)
6 (s2 + 0.5176s + 1)(s2 + 1.4142s + 1)(s2 + 1.9319s + 1)
7 (s + 1)(s2 + 0.4450s + 1)(s2 + 1.2470s + 1)(s2 + 1.8019s + 1)
8 (s2 + 0.3902s + 1)(s2 + 1.1111s + 1)(s2 + 1.6629s + 1)(s2 + 1.9616s + 1)
Maximal flatness
Assuming ωc = 1 and G0 = 1, the derivative of the gain with respect to frequency can be
shown to be:
which is monotonically decreasing for all ω since the gain G is always positive. The gain
function of the Butterworth filter therefore has no ripple. Furthermore, the series
expansion of the gain is given by:
In other words, all derivatives of the gain up to but not including the 2n-th derivative are
zero, resulting in "maximal flatness". If the requirement to be monotonic is limited to the
passband only and ripples are allowed in the stopband, then it is possible to design a filter
of the same order that is flatter in the passband than the "maximally flat" Butterworth.
Such a filter is the inverse Chebyshev filter.
High-frequency roll-off
Again assuming ωc = 1, the slope of the log of the gain for large ω is:
In decibels, the high-frequency roll-off is therefore 20n dB/decade, or 6n dB/octave (The

factor of 20 is used because the power is proportional to the square of the voltage gain;
see 20 log rule.)
FILTER DESIGN
There are a number of different filter topologies available to implement a linear analogue
filter. These circuits differ only in the values of the components, but not in their
connections.
Cauer topology
The Cauer topology uses passive components (shunt capacitors and series inductors) to
implement a linear analog filter. The Butterworth filter having a given transfer function
can be realised using a Cauer 1-form. The kth element is given by:
; k = odd
; k = even
The filter may start with a series inductor if desired, in which case the Lk are k odd and
the Ck are k even.
Sallen-Key topology
The Sallen-Key topology uses active and passive components (op amps and capacitors) to
implement a linear analog filter. Each Sallen-Key stage implements a conjugate pair of
poles; the overall filter is implemented by cascading all stages in series. If there is a real
pole (in the case where n is odd), this must be implemented separately, usually as an RC
circuit, and cascaded with the op-amp stages.
The Sallen-Key transfer function is given by
We wish the denominator to be one of the quadratic terms in a Butterworth polynomial.

Assuming that ωc = 1, this will mean that
and
This leaves two component values undefined, which may be chosen at will.
COMPARISON WITH OTHER LINEAR FILTERS
Here is an image showing the gain of a discrete-time Butterworth filter next to other
common filter types. All of these filters are fifth-order.
The Butterworth filter rolls off more slowly around the cutoff frequency than the others,
but shows no ripples.
How to design a second-order high pass Butterworth filter:
1. Determine your cutoff frequency
2. Make = = R and = =C
3. Select a mylar or tantalum capacitor with a value of less than about 1 F.
4. Calculate the value of R using
5. Choose a value of that's less than
6. Make = 0.586 . Note that this makes your passband gain approximately
equal to 1.586. This is necessary to guarantee a Butterworth response[].
BAND-PASS FILTER
A band-pass filter is a device that passes frequencies within a certain range and rejects
(attenuates) frequencies outside that range. An example of an analogue electronic band-
pass filter is an RLC circuit (a resistor–inductor–capacitor circuit). These filters can also
be created by combining a low-pass filter with a high-pass filter.[1]
Bandpass is an adjective that describes a type of filter or filtering process; it is frequently

confused with passband, which refers to the actual portion of affected spectrum. The two
words are both compound words that follow the English rules of formation: the primary
meaning is the latter part of the compound, while the modifier is the first part. Hence, one
may correctly say 'A dual bandpass filter has two passbands'.
An ideal bandpass filter would have a completely flat passband (e.g. with no
gain/attenuation throughout) and would completely attenuate all frequencies outside the
passband. Additionally, the transition out of the passband would be instantaneous in
frequency. In practice, no bandpass filter is ideal. The filter does not attenuate all
frequencies outside the desired frequency range completely; in particular, there is a
region just outside the intended passband where frequencies are attenuated, but not
rejected. This is known as the filter roll-off, and it is usually expressed in dB of
attenuation per octave or decade of frequency. Generally, the design of a filter seeks to
make the roll-off as narrow as possible, thus allowing the filter to perform as close as
possible to its intended design. Often, this is achieved at the expense of pass-band or
stop-band ripple.
The bandwidth of the filter is simply the difference between the upper and lower cutoff
frequencies. The shape factor is the ratio of bandwidths measured using two different
attenuation values to determine the cutoff frequency, e.g., a shape factor of 2:1 at 30/3 dB
means the bandwidth measured between frequencies at 30 dB attenuation is twice that
measured between frequencies at 3 dB attenuation.
Outside of electronics and signal processing, one example of the use of band-pass filters
is in the atmospheric sciences. It is common to band-pass filter recent meteorological data
with a period range of, for example, 3 to 10 days, so that only cyclones remain as
fluctuations in the data fields.
In neuroscience, visual cortical simple cells were first shown by David Hubel and Torsten
Wiesel to have response properties that resemble Gabor filters, which are band-pass
BAND-REJECTION FILTER
1-39 Figure 1-20C.—Components of a simple bandpass filter. Band-Reject Filter A band-

reject filter circuit is used to block the passage of current for a narrow band of
frequencies, while allowing current to flow at all frequencies above or below this band.
This type of filter is also known as a BAND-SUPPRESSION or BAND-STOP filter. The
way it responds is shown by the response curve of figure 1-21. Since the purpose of the
band-reject filter is directly opposite to that of a bandpass filter, the relative positions of
the resonant circuits in the filter are interchanged. The parallel-LC circuit shown in figure
1-22, view (A), replaces the capacitor of figure 1-18, view (A). It acts as a band-reject
filter, blocking the passage of currents having frequencies at or near resonant frequency
and passing all currents having frequencies outside this band. The series-LC circuit
shown in figure 1-22, view (B), replaces the inductor of figure 1-18, view (B). If this
series circuit is tuned, to the same frequency as the parallel circuit, it acts as a bypass for
the band of rejected frequencies. Then, the simplest type of band- reject filter is obtained
by connecting the two circuits as shown in figure 1-22, view (C). Figure 1-21.—Band-
reject filter response curve.
UNIT -7
SPECIALIZED IC APPLICATIONS
Universal active filter
switched capacitor filter
phase locked loops
power amplifiers.
UNIVERSAL FILTER
ORIGINALLY I WAS ONLY INTERESTED IN THIS CIRCUIT FOR SOME EXPERIMENTS, BUT THE
BREADBORD ASSEMBLY TURNED OUT TO BE SO USEFUL THAT I DECIDED TO MAKE IT A REAL
PROJECT. THE UNIVERSAL FILTER IS A DOUBLE POLE (= SECOND ORDER) ACTIVE FILTER
BUILT OF 4 OP-AMPS.
FIGURE 1 - BASIC CIRCUIT OF A UNIVERSAL FILTER
EACH OUTPUT OF THE FOUR OP-AMPS PROVIDES DIFFERENT FILTER CHARACTERISTICS:
NOTCH-FILTER
2ND ORDER HIGH-PASS FILTER
BAND-PASS FILTER
2ND ORDER LOW-PASS FILTER
IN THE CIRCUIT DIAGRAM ABOVE IT IS POSSIBLE TO DIRECTLY SET UP THE MOST

INTERESTING FILTER PARAMETERS, THE FREQUENCY AND THE QUALITY-FACTOR Q. (OTHER
CIRCUITS ARE POSSIBLE, I. E. TO DIRECTLY SET UP THE COEFFICIENTS K1, K2, L1 AND L2 OF
THE TRANSFER FUNCTION.) ADDITIONALLY IT IS POSSIBLE TO SET UP THE OVERALL GAIN.
THE EFFECT OF GAIN AND FREQUENCY SETTING IS OBVIOUS, BUT BEFORE I COME TO THE
PRACTICAL IMPLEMENTATION LET ME EXPLAIN WHAT THE Q-FACTOR IS.
THE Q-FACTOR IS KNOWN FROM RESONANT CIRCUITS. THE HIGHER Q (THE "QUALITY") IS,
THE SHARPER THE RESONANCE IS. NUMERICALLY, THE Q-FACTOR IS THE RELATION
BETWEEN CENTER FREQUENCY AND THE -3 DB-BANDWIDTH. IN LC-RESONANT CIRCUITS IT
IS ALSO THE RELATION BETWEEN THE L- AND C-IMPEDANCES AND THE DAMPING OR
FEEDING RESISTOR R.
FIGURE 2 - EFFECT OF THE Q-FACTOR
HERE YOU SEE FREQUENCY RESPONSES OF THREE RESONANT CIRCUITS WITH Q-FACTORS OF
1, 10 AND 100 RESP.. THE RESONANCE FREQUENCY IS 1,59 KHZ AND THE -3 DB-
BANDWIDTHS ARE 1,59 KHZ, 159 HZ AND 15,9 HZ RESP.. FILTERS WITH ORDERS > 1 ARE
ND
BUILT OF ONE OR MORE 2 ORDER FITERS, EACH WITH A DESIGNATED RESONANCE
FREQUENCY AND Q-FACTOR. IF YOU WANT TO KNOW MORE ABOUT DIFFERENT Q-FACTORS
OF DIFFERENT STAGES OF DIFFERENT FILTER TYPES HAVE A LOOK AT MY ARTICLE ACTIVE
FILTER DESIGN AND DIMENSIONING. MOST INTERESTING, HOWEVER, IS TO SEE HOW
FREQUENCY RESPONSES OF THE UNIVERSAL FILTER WITH RESPECT TO DIFFERENT SETTINGS
OF THE Q-FACTOR WILL BE:
Q-FACTOR DEPENDING FREQUENCY RESPONSES
FOR ALL FREQUENCY RESPONSES SHOWN BELOW A CENTER FREQUENCY (RESP. CORNER
FREQUENCY) OF 1.59 KHZ IS SET. NOTE: IT IS A CHARACTERISTICAL FEATURE OF THE
UNIVERSAL FILTER THAT FOR ALL Q-FACTORS THE GAIN AT THE CENTER OR CORNER
FREQUENCY IS 1! (EXCEPT THE NOTCH FILTER OF COURSE.)
PRACTICAL IMPLEMENTATION
THE FIRST APPLICATION I USED MY BREADBORD ASSEMBLY FOR WAS NOISE AND
DISTORTION MEASUREMENTS AT MY HIGH-QUALITY AUDIO ANALOG-TO-DIGITAL
CONVERTERS, WHERE MY LOW DISTORTION GENERATOR WAS NOT GOOD ENOUGH. SO MY
EMPHASIS WAS ON DISTORTION, NOISE AND THE BAND-PASS FILTER, IN ORDER TO IMPROVE
THE SPECTRAL PURITY OF A SINGLE TONE. TO KEEP IT NOT TO ELABORATE I OMITTED THE
GAIN POTENTIOMETER.
THE FREQUENCY SET-UP IS DIVIDED INTO TWO RANGES OF 5 HZ TO 1 KHZ AND 500 HZ TO
100 KHZ. FOR A RANGE OF MORE THAN ONE DECADE IT IS VERY ADVISABLE TO USE A
LOGARITHMIC POTENTIOMETER. UNFORTUNATELY ONLY POSITIVE ONES ARE EASILY
AVAILABLE, SO THAT FOR HIGHER FREQUENCIES IT MUST BE TURNED LEFT.
THE Q-FACTOR IS ADJUSTABLE BETWEEN 0.1 AND 100 AND THE FILTER CHARACTERISTICS
CAN BE SELECTED BY A ROTARY SWITCH.
FIGURE 7 - SCHEMATICS OF THE PRACTICAL IMPLEMENTATION
CIRCUIT DETAILS
IN ORDER TO ACHIEVE A RANGE FOR THEQ-FACTOR OF 0.1 : 100 AND TO AVOID A HIGH
LOAD FOR IC1A AT LOW Q MY CHOICE WAS A 1 MOHM POTENTIOMETER.
I AIMED FOR A FREQUENCY RANGE OF AT LEAST 1 : 200. I HAD AN APPROPRIATE DUAL

GANGED 100 KOHM POTENTIOMETER WITH AN ACTUAL RESISTANCE OF CLEARLY BELOW
100 KOHM. SO I DIMENSIONED R7 AND R8 AS 390 OHM WHICH GUARANTEES A RANGE >
1 : 200. 390 OHM IS LESS THAN I ACTUALLY LIKE - MAYBE I'LL CHANGE THIS WHEN I FIND A
CHEAP ALPS 250 KOHM POT IN EBAY.
ON THE OTHER HAND I WANT TO AVOID HIGH RESISTOR VALUES AS THEY MAY CREATE
MORE NOISE THAN THE OP-AMPS DO. THEREFORE IT WOULD NOT BE UNWISE TO REDUCE THE
10 KOHM RESISTORS DOWN TO 1 KOHM OR SO, AS THE NOISE GENERATED BY 10 KOHM IS
ALMOST 20 NV/SQR(HZ) - AS MUCH AS A TL072 GENERATES AND MORE THAN TWICE AS
MUCH AS THE OPA2134 DO. BUT I'M AFRAID DISTORTION WOULD BE INCREASED, AT LEAST
FOR HIGHER VOLTAGES.
C1 HAS TO COMPENSATE THE PHASE DELAY OF THE OP-AMPS. WITHOUT IT THE CIRCUIT
OSCILLATES AT HIGHER FREQUENCIES.
THE FREQUENCY DETERMINING CAPACITORS C3, C5, C7 ANDC9 ARE IN PARALLEL BY A

SECOND, SMALLER CAPACITOR TO ADJUST THE DESIRED RANGE. IN MY CASE WITH THE
FREQUENCY POTENTIOMETER OF 90 KOHM APPROX. AND THE UNKNOWN TRUE VALUES OF
THE CAPACITORS PARALLELING 2 X 33 NF AND 2 X 560 PF RESP. TURNED OUT TO BE
OPTIMAL. MY FREQUENCY RANGES NOW ARE 4.8 HZ TO 1.07 KHZ AND 470 HZ TO
104 KHZ.
WHAT IS DEFINTIVELY MISSING IN THIS CIRCUIT IS A VERNIER FOR THE FREQUENCY. WITH A
POTENTIOMETER COVERING TWO DECADES IT IS NOT POSSIBLE TO MEET EXACTLY THE
CENTER FREQUENCY OF A BAND-PASS OR - EVEN WORSE - A NOTCH FILTER WITH A Q-
FACTOR OF 100. A VERNIER BY JUST PUTTING ANOTHER POTENTIOMETER IN SERIES WITH
THE MAIN ONE DOES NOT MAKE MUCH SENSE WITH 2 LOGARITHMIC DECADES, AND AN
APPROPRIATE APPROACH IS NOT THAT SIMPLE AND PROBABLY REQUIRES ANOTHER TWO OP-
AMPS. SO IT MIGHT HAVE BEEN BETTER TO GO FOR 9 RANGES OF 1 : 3. THEN IT IS NOT ONLY
EASIER TO SET-UP THE MAIN POTENTIOMETER BUT ALSO A SECOND, SIMPLE (VERNIER)
POTENTIOMETER IN SERIES MAKES SENSE. AS MY FATHER USED TO SAY: YOU'RE GROWING
OLD TOO EARLY AND WISE TOO LATE.
COMPONENT SELECTION
I OPA2134 BECAUSE IT IS DESIGNED FOR LOW NOISE AND VERY LOW

SELECTED
DISTORTION. THEY MAY NOT BE THE CHEAPEST ONES AND NOT EVERYWHERE AVAILABLE,
BUT ON THE OTHER HAND THEY ARE NOT TOO EXPENSIVE OR RARE. FOR LESS
REQUIREMENTS TL072 OR NE5532 SHOULD DO, TOO.
THE TYPE OF CAPACITORS C2 - C9 IS IMPORTANT. WHEN HIGH Q-FACTORS ARE TO BE

ACHIEVED LOW-LOSS TYPES MUST BE SELECTED. POLYPROPYLENE AS DIELECTRIC IS THE
BEST CHOICE, POLYCARBONATE FINE, BUT NOT THAT GOOD. FOR LOWER CAPACITANCES
CERAMIC TYPES BETWEEN P100 AND N1500 ARE FINE. IF YOU WANT TO SEE THE EFFECT OF
A REALLY LOSSY CAPACITOR TRY THE SMALL 100 NF RF-BLOCKING X7R OR Y5V
CAPACITORS (THESE ONES ARE OF COURSE FINE FOR C10 AND C11.) THE CAPACITIVE LOSSES
ARE REFLECTED IN A GAIN LESS THAN ONE IN CASE OF HIGH Q-FACTORS. WITH THE
POLYPROPYLENE CAPS I ACHIEVE GAINS > 0.9 IN THE LOWER FREQUENCY RANGE AND > 0.7
IN THE UPPER RANGE. OTHER EFFECTS HAVE MORE INFLUENCE ON THE GAIN HERE. THE
HIGHER THE FREQUENCY, THE LOWER THE GAIN, EXCEPT AT VERY HIGH FREQUENCY,
WHERE THE CIRCUIT WOULD OSCILLATE WITHOUT C1. THUS ADJUST C1 IN A WAY SO THAT A
REASONABLE GAIN AT 100 KHZ IS ACHIEVED - EITHER SO THAT IT RISES TO UP TO 1 AGAIN,
OR TO THE SAME GAIN AS AT THE BEGINNING OF THE RANGE OR SO THAT THE GAIN
CONSTANTLY DECREASES UNTIL THE END OF THE RANGE. FOR ME THIS IS A QUESTION OF
TASTE.
THE POTENTIOMETERS ARE LOGARITHMIC ONES. THE ONE FOR THE Q-FACTOR IDEALLY
SHOULD COVER THREE DECADES (I. E. 10 KOHM AT 33%, 100 KOHM AT 67% AND 1 MOHM
AT 100%), BUT ACTUALLY YOU HAVE NO CHOICE OF THE NUMBER OF DECADES LOG POTS
COVER. USUALLY THEY ARE OPTIMIZED FOR 2 DECADES APPROXIMATELY (I. E. 10%
RESISTANCE IN MID POSITION) AND THIS OFTEN IS ACHIEVED WITH TWO LINEAR SECTIONS
ONLY. YOU MAY LEARN MORE ABOUT POTS AT ROD ELLIOTTS BEGINNERS' GUIDE TO
POTENTIOMETERS. FOR THE DUAL GANGED FREQUENCY SET-UP POT I AFFORDED A MORE
EXPENSIVE ONE HOPING FOR BETTER LOGARITHMIC CHARACTERISTICS AND BETTER
SYNCHRONIZATION.
NOT REALLY A QUESTION OF COMPONENT SELECTION IS THE SUPPLY VOLTAGE: WITH

2 X 15 V THE MAXIMUM OUTPUT VOLTAGE IS JUST BELOW 10 VRMS, SO IT MIGHT BE
INTERESTING TO INCREASE THE SUPPLY VOLTAGE SLIGHTLY TO 2 X 16 V OR 17 V, BUT
KEEP IN MIND THAT MOST OP-AMPS ARE LIMITED TO 36 V.
SWITCHED CAPACITOR CIRCUITS
In the last decade or so many active filters with resistors and capacitors have been
replaced with a special kind of filter called a switched capacitor filter. The switched
capacitor filter allows for very sophisticated, accurate, and tuneable analog circuits to be
manufactured without using resistors. This is useful for several reasons. Chief among
these is that resistors are hard to build on integrated circuits (they take up a lot of room),
and the circuits can be made to depend on ratios of capacitor values (which can be set
accurately), and not absolute values (which vary between manufacturing runs).
The Switched Capacitor Resistor
To understand how switched capacitor circuits work, consider the circuit shown
with a capacitor connected to two switches and two different voltages.
If S2 closes with S1 open, then S1 closes with switch S2 open, a charge (q is transferred
from v2 to v1 with
If this switching process is repeated N times in a time (t, the amount of charge transferred
per unit time is given by
Recognizing that the left hand side represents charge per unit time, or current, and the the
number of cycles per unit time is the switching frequency (or clock frequency, f CLK) we
can rewrite the equation as
Rearranging we get
which states that the switched capacitor is equivalent to a resistor. The value of this
resistor decreases with increasing switching frequency or increasing capacitance, as
either will increase the amount of charge transfered from v2 to v1 in a given time.
The Switched Capacitor Integrator
Now consider the integrator circuit. You have shown (in a previous lab) that the input-
output relationship for this circuit is given by (neglecting initial conditions):
We can also write this with the "s" notation (assuming a sinusoidal input, Aest, s=j)
If you replaced the input resistor with a switched capacitor resistor, you would get
Thus, you can change the equivalent ' of the circuit by changing the clock frequency.
The value of ' can be set very precisely because it depends only on the ratio of C1 and
C2, and not their absolute value.
The LMF100 Switched Capacitor Filter
In this lab you will be using the MF100, or LMF100 (web page, datasheet, application
note). This integrated circuit is a versatile circuit with four switched capacitor
integrators, that can be connected as two second order filters or one fourth order filter.
With this chip you can choose ' to either be 1/50 or 1/100 of the clock frequency (this is
given by the ratio C1/C2 in the discussion above),. By changing internal and external
connections to the circuit you can obtain different filter types (lowpass, highpass,
bandpass, notch (bandreject) or allpass).
2nd Order Filters

Filter Type Transfer Function
Low Pass
High Pass
Band Pass
Notch (Band
Reject)
The pinout for the LMF100 is shown below (from the data sheet):
You can see that the chip, for the most part, is split into two halves, left and right. A
block diagram of the left half ((and a few pins from the right half) is shown below.
The pins are described on page 8 of the datasheet. I will describe a few of them here:
50/100 - determines if the value of ' is CLK/100, or CLK/50.

CLKA - is CLK.
INVA - the inverting input to the op-amp
N/AP/HPA - an intermediate output, and the non-inverting input to the
summer. Used for Notch, All Pass or High Pass output.
BPA - another intermediate output, the output of the first integrator. Used
for Band Pass output.
LPA - the output of the second integrator. Used for Low Pass output.
S1A - an inverting input to the summer.
SAB - determins if the switch is to the left or to the right. That is, this pin
determines if the second inverting input to the summer is ground (AGND),
or the low pass output.
The two integrators are switched capacitor integrators. Their transfer functions are given
by,
where ' is CLK/100, or CLK/50, depending on the state of the 50/100 pin. Note that
the integrator is non-inverting.
A Typical Circuit.
The diagram below shows one of the modes (mode 1) of operations (pages 13 through 20
of the datasheet).
Let's analyze this circuit and try to derive the filter specifications as given in the
datasheet, and given below.
The low pass (LP A) output is easily given in terms of the band pass output (BP A), as well
as the band pass output as a function of the summer (SUM, not labeled on diagram).
The summer output (SUM) is simply the output of the op amp (N A) minus the lowpass
output (LPA). However we can see that the op amp is set up as the inverting summing
circuit. So
Replace SUM on the left hand side using equation (2) from above, and LP A using
equation (1).
Rearranging brings
Equating this with the transfer function for a bandpass circuit
yields,
which is what we were trying to derive.
Similarly, the relationship between low pass and band pass, equation (1), can be used to
find the low pass transfer function. The notch filter transfer function is derived in the
same way.
PHASE-LOCKED LOOP
A phase-locked loop or phase lock loop (PLL) is a control system that generates a
signal that has a fixed relation to the phase of a "reference" signal. A phase-locked loop
circuit responds to both the frequency and the phase of the input signals, automatically
raising or lowering the frequency of a controlled oscillator until it is matched to the
reference in both frequency and phase. A phase-locked loop is an example of a control

system using negative feedback.
In simpler terms, a PLL compares the frequencies of two signals and produces an error
signal which is proportional to the difference between the input frequencies. The error
signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO)
which creates an output frequency. The output frequency is fed through a frequency
divider back to the input of the system, producing a negative feedback loop. If the output
frequency drifts, the error signal will increase, driving the frequency in the opposite
direction so as to reduce the error. Thus the output is locked to the frequency at the other
input. This input is called the reference and is often derived from a crystal oscillator,
which is very stable in frequency.
Phase-locked loops are widely used in radio, telecommunications, computers and other
electronic applications. They may generate stable frequencies, recover a signal from a
noisy communication channel, or distribute clock timing pulses in digital logic designs
such as microprocessors. Since a single integrated circuit can provide a complete phase-
locked-loop building block, the technique is widely used in modern electronic devices,
with output frequencies from a fraction of a cycle per second up to many gigahertz.
STRUCTURE AND FUNCTION
Phase-locked loop mechanisms may be implemented as either analog or digital circuits.

Both implementations use the same basic structure.
Block diagram of a PLL
Both analog and digital PLL circuits include three basic elements:
a phase detector,
a variable electronic oscillator, and
a feedback path (which often includes a frequency divider).
DIGITAL PHASE-LOCKED LOOP (DPLL)
A digital phase-locked loop operates similarly to an analog phase-locked loop, but is

implemented entirely using digital circuits. In place of a voltage-controlled oscillator
(VCO), a DPLL uses local reference clock and a variable dividing counter under digital
control to create the equivalent oscillator function.
DPLLs are easier to design and implement, and are less sensitive to voltage noise than
analog PLLs, however they typically suffer from higher phase noise due to the
quantization error of using a non-analog oscillator. For this reason digital phase locked
loops are not well-suited to synthesizing higher frequencies or handling high frequency
reference signals. DPLLs are sometimes used for data recovery.
ANALOG PHASE-LOCKED LOOP
Basic design
Phase-locked loop block diagram
Analog phase locked loops are generally built of a phase detector, low pass filter and
voltage-controlled oscillator (VCO) placed in a negative feedback closed-loop
configuration. There may be a frequency divider in the feedback path or in the reference
path, or both, in order to make the PLL's output signal frequency an integer multiple of
the reference. A non integer multiple of the reference frequency can be created by
replacing the simple divide-by-N counter in the feedback path with a programmable pulse
swallowing counter. This technique is usually referred to as a fractional-N synthesizer or
fractional-N PLL.
The oscillator generates a periodic output signal. Assume that initially the oscillator is at
nearly the same frequency as the reference signal. Then, if the phase from the oscillator
falls behind that of the reference, the phase detector changes the control voltage of the
oscillator, so that it speeds up. Likewise, if the phase creeps ahead of the reference, the
phase detector changes the control voltage to slow down the oscillator. A low-pass filter
smooths out abrupt changes in the control voltage; it can be demonstrated that some
filtering is required for a stable system. Since initially the oscillator may be far from the
reference frequency, practical phase detectors may also respond to frequency differences,
so as to increase the lock-in range of allowable inputs.
Depending on the application, either the output of the controlled oscillator, or the control
signal to the oscillator, provides the useful output of the PLL system.
EQUATIONS
THE EQUATIONS GOVERNING A PHASE-LOCKED LOOP WITH AN ANALOG MULTIPLIER AS THE

PHASE DETECTOR MAY BE DERIVED AS FOLLOWS. LET THE INPUT TO THE PHASE DETECTOR
BE XC(T) AND THE OUTPUT OF THE VOLTAGE-CONTROLLED OSCILLATOR (VCO) IS XR(T)
WITH FREQUENCY ΩR(T), THEN THE OUTPUT OF THE PHASE DETECTOR XM(T) IS GIVEN BY
THE VCO FREQUENCY MAY BE WRITTEN AS A FUNCTION OF THE VCO INPUT Y(T) AS
WHERE GV IS THE SENSITIVITY OF THE VCO AND IS EXPRESSED IN HZ / V.
HENCE THE VCO OUTPUT TAKES THE FORM
WHERE
THE LOOP FILTER RECEIVES THIS SIGNAL AS INPUT AND PRODUCES AN OUTPUT
XF(T) = FFILTER(XM(T))
WHERE FFILTER IS THE OPERATOR REPRESENTING THE LOOP FILTER TRANSFORMATION.
WHEN THE LOOP IS CLOSED, THE OUTPUT FROM THE LOOP FILTER BECOMES THE INPUT TO
THE VCO THUS
Y(T) = XF(T) = FFILTER(XM(T))
WE CAN DEDUCE HOW THE PLL REACTS TO A SINUSOIDAL INPUT SIGNAL:
XC(T) = ACSIN(ΩCT).
THE OUTPUT OF THE PHASE DETECTOR THEN IS:
THIS CAN BE REWRITTEN INTO SUM AND DIFFERENCE COMPONENTS USING TRIGONOMETRIC
IDENTITIES:
AS AN APPROXIMATION TO THE BEHAVIOUR OF THE LOOP FILTER WE MAY CONSIDER ONLY

THE DIFFERENCE FREQUENCY BEING PASSED WITH NO PHASE CHANGE, WHICH ENABLES US
TO DERIVE A SMALL-SIGNAL MODEL OF THE PHASE-LOCKED LOOP. IF WE CAN MAKE
, THEN THE CAN BE APPROXIMATED BY ITS ARGUMENT RESULTING IN:
. THE PHASE-LOCKED LOOP IS SAID TO BE LOCKED IF

THIS IS THE CASE.
CONTROL SYSTEM ANALYSIS
PHASE LOCKED LOOPS CAN ALSO BE ANALYZED AS CONTROL SYSTEMS BY APPLYING THE
LAPLACE TRANSFORM. THE LOOP RESPONSE CAN BE WRITTEN AS:
WHERE
ΘO IS THE OUTPUT PHASE IN RADIANS

ΘI IS THE INPUT PHASE IN RADIANS
KP IS THE PHASE DETECTOR GAIN IN VOLTS PER RADIAN
KV IS THE VCO GAIN IN RADIANS PER VOLT-SECOND
F(S) IS THE LOOP FILTER TRANSFER FUNCTION (DIMENSIONLESS)
THE LOOP CHARACTERISTICS CAN BE CONTROLLED BY INSERTING DIFFERENT TYPES OF

LOOP FILTERS. THE SIMPLEST FILTER IS A ONE-POLE RC CIRCUIT. THE LOOP TRANSFER
FUNCTION IN THIS CASE IS:
THE LOOP RESPONSE BECOMES:
THIS IS THE FORM OF A CLASSIC HARMONIC OSCILLATOR. THE DENOMINATOR CAN BE

RELATED TO THAT OF A SECOND ORDER SYSTEM:
WHERE
Ζ IS THE DAMPING FACTOR

ΩN IS THE NATURAL FREQUENCY OF THE LOOP
FOR THE ONE-POLE RC FILTER,
THE LOOP NATURAL FREQUENCY IS A MEASURE OF THE RESPONSE TIME OF THE LOOP, AND
THE DAMPING FACTOR IS A MEASURE OF THE OVERSHOOT AND RINGING. IDEALLY, THE
NATURAL FREQUENCY SHOULD BE HIGH AND THE DAMPING FACTOR SHOULD BE NEAR 0.707
(CRITICAL DAMPING). WITH A SINGLE POLE FILTER, IT IS NOT POSSIBLE TO CONTROL THE
LOOP FREQUENCY AND DAMPING FACTOR INDEPENDENTLY. FOR THE CASE OF CRITICAL
DAMPING,
A SLIGHTLY MORE EFFECTIVE FILTER, THE LAG-LEAD FILTER INCLUDES ONE POLE AND ONE
ZERO. THIS CAN BE REALIZED WITH TWO RESISTORS AND ONE CAPACITOR. THE TRANSFER
FUNCTION FOR THIS FILTER IS
THIS FILTER HAS TWO TIME CONSTANTS
Τ1 = C(R1 + R2)
Τ2 = CR2
SUBSTITUTING ABOVE YIELDS THE FOLLOWING NATURAL FREQUENCY AND DAMPING

FACTOR
THE LOOP FILTER COMPONENTS CAN BE CALCULATED INDEPENDENTLY FOR A GIVEN

NATURAL FREQUENCY AND DAMPING FACTOR
REAL WORLD LOOP FILTER DESIGN CAN BE MUCH MORE COMPLEX EG USING HIGHER ORDER
FILTERS TO REDUCE VARIOUS TYPES OR SOURCE OF PHASE NOISE.
APPLICATIONS
Phase-locked loops are widely used for synchronization purposes; in space

communications for coherent carrier tracking and threshold extension, bit
synchronization, and symbol synchronization. Phase-locked loops can also be used to
demodulate frequency-modulated signals. In radio transmitters, a PLL is used to
synthesize new frequencies which are a multiple of a reference frequency, with the same
stability as the reference frequency.
Clock recovery
Some data streams, especially high-speed serial data streams (such as the raw stream of
data from the magnetic head of a disk drive), are sent without an accompanying clock.
The receiver generates a clock from an approximate frequency reference, and then phase-
aligns to the transitions in the data stream with a PLL. This process is referred to as clock
recovery. In order for this scheme to work, the data stream must have a transition
frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of
redundant encoding is used; 8B10B is very common.
Deskewing
If a clock is sent in parallel with data, that clock can be used to sample the data. Because
the clock must be received and amplified before it can drive the flip-flops which sample
the data, there will be a finite, and process-, temperature-, and voltage-dependent delay
between the detected clock edge and the received data window. This delay limits the
frequency at which data can be sent. One way of eliminating this delay is to include a
deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched
to the received clock. In that type of application, a special form of a PLL called a Delay-
Locked Loop (DLL) is frequently used ;;.[5]
Clock generation
Many electronic systems include processors of various sorts that operate at hundreds of
megahertz. Typically, the clocks supplied to these processors come from clock generator
PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to
the operating frequency of the processor. The multiplication factor can be quite large in
cases where the operating frequency is multiple gigahertz and the reference crystal is just
tens or hundreds of megahertz.
Spread spectrum
All electronic systems emit some unwanted radio frequency energy. Various regulatory
agencies (such as the FCC in the United States) put limits on the emitted energy and any
interference caused by it. The emitted noise generally appears at sharp spectral peaks
(usually at the operating frequency of the device, and a few harmonics). A system
designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by
spreading the energy over a larger portion of the spectrum. For example, by changing the
operating frequency up and down by a small amount (about 1%), a device running at
hundreds of megahertz can spread its interference evenly over a few megahertz of
spectrum, which drastically reduces the amount of noise seen on FM channels, which
have a small bandwidth around 200kHz or so.
Clock distribution
Typically, the reference clock enters the chip and drives a phase locked loop (PLL),
which then drives the system's clock distribution. The clock distribution is usually
balanced so that the clock arrives at every endpoint simultaneously. One of those
endpoints is the PLL's feedback input. The function of the PLL is to compare the
distributed clock to the incoming reference clock, and vary the phase and frequency of its
output until the reference and feedback clocks are phase and frequency matched. From a
control theory perspective, the PLL is a special case of the Kalman filter.
PLLs are ubiquitous -- they tune clocks in systems several feet across, as well as clocks
in small portions of individual chips. Sometimes the reference clock may not actually be
a pure clock at all, but rather a data stream with enough transitions that the PLL is able to
recover a regular clock from that stream. Sometimes the reference clock is the same
frequency as the clock driven through the clock distribution, other times the distributed
clock may be some rational multiple of the reference.
Opamp Based Power Amplifier
DESCRIPTION
THE AMPLIFIER IS BASED ON THE COMMONLY USED CLASS-AB COMPLEMENTARY POWER

AMPLIFIER WITH COMPOUND PAIR OUTPUT TRANSISTORS. THE SYSTEM USES A TL074 QUAD
OPAMP TO DRIVE THE OUTPUT TRANSISTORS. AS CAN BE SEEN FROM FIGURE 1, A2 IS USED
TO SET THE VOLTAGE GAIN OF THE AMPLIFIER. ASSUMING THE VOLTAGE GAIN OF A
COMMON COLLECTOR STAGE TO BE UNITY, THE OVERALL VOLTAGE GAIN OF THE AMPLIFIER
IS EQUAL TO (R4 / R3) + 1, I.E. THE GAIN OF A NON-INVERTING OP-AMP (16 OR 24DB, IN
THIS CASE). SINCE THE OUTPUT TRANSISTORS ARE WITHIN THE FEEDBACK LOOP OF A2, A2
ALSO ACTS TO LINEARISE THE INPUT CHARACTERISTIC OF THE COMPLEMENTARY PAIR
Q1/Q2 & Q3/Q4. THIS ALLOWS FOR GREATER MISMATCH BETWEEN THE NPN-PNP
TRANSISTORS.
Figure 1 - Power Amplifier Schematic
THE BIASING TO Q1 & Q3 IS PROVIDED BY R6, R7 & DIODES D1 & D2. THIS
ARRANGEMENT BIASES THE TRANSISTORS JUST ABOVE CUT-OFF AND REDUCES CROSSOVER
DISTORTION. R6 MUST BE ADJUSTED TO THE HIGHEST VALUE WHICH ELIMINATES
CROSSOVER DISTORTION. IDEALLY D1 & D2 SHOULD BE MOUNTED SO THEY ARE IN
CONTACT WITH THE DRIVER TRANSISTORS - NOT THE MAIN HEATSINK.
TO ADJUST R6 WITHOUT AN OSCILLOSCOPE, START WITH R6 SET TO MAXIMUM, SET THE

VOLUME CONTROL R2 TO GET THE MINIMUM AUDIBLE OUTPUT WITH A SUITABLE INPUT
SOURCE (SUCH AS A CD PLAYER WHICH GIVES 0.65VRMS AT LINE OUT), AND LISTEN FOR
ANY "CRACKLE" IN THE SOUND, ESPECIALLY THAT WHICH SEEMS TO BE RIDING ON LOW
FREQUENCY SOUNDS. IF A "CRACKLE" IS HEARD THEN REDUCE THE VALUE OF R6 IN VERY
SMALL STEPS, UNTIL THE CRACKLE (CROSSOVER DISTORTION) BECOMES INAUDIBLE (IT
CAN'T BE ELIMINATED, I FEEL).
AS THE OUTPUT OF OPAMP A2 IS BEING PULLED UP BY THE BIASING CIRCUIT, CAPACITOR C5

MUST BE CONNECTED BETWEEN THE OUTPUT OF A2 AND GROUND TO PREVENT THE CIRCUIT
FROM BREAKING INTO OSCILLATIONS. THE VALUE OF C5 IS NOT CRITICAL, ANY VALUE
BETWEEN 22NF TO 100NF WILL DO. THE OPAMP A1 IS A SIMPLE BUFFER WHICH ISOLATES
THE INPUT CIRCUIT FROM THE POWER STAGE. C1 & R1 ARE USED TO SET THE LOWER 3DB
FREQUENCY TO AROUND 15HZ, AND TO OBTAIN AN INPUT IMPEDANCE OF ABOUT 100K. THE
UPPER 3DB FREQUENCY IS DETERMINED BY R4 & C7, WHICH IN THIS CASE IS
APPROXIMATELY 30KHZ. THE SCHEMATIC SHOWS ONLY ONE CHANNEL OF THE STEREO
AMPLIFIER. THE AMPLIFIER CAN BE USED TO DRIVE SPEAKERS WITH IMPEDANCE RANGING
FROM 3 OHMS TO 8 OHMS, HIGHER IMPEDANCE SPEAKERS COULD BE USED BUT THE POWER
OUTPUT WILL BE SUBSTANTIALLY LESS.
THE VOLTAGE GAIN OF THE AMPLIFIER CAN BE INCREASED BY INCREASING R4 OR

DECREASING R3, AS LONG AS THE OUTPUT SWING IS KEPT LESS THAN OR EQUAL TO 3 VOLTS
BELOW THE SUPPLY RAILS. THIS IS DUE TO THE FACT THAT THE MAXIMUM OUTPUT
VOLTAGE OF AN OPAMP IS ALWAYS 2-3 VOLTS LESS THAN THE SUPPLY RAILS, BEFORE IT
CLIPS.
THE VOLTAGE GAIN OF THE AMPLIFIER IS 16 OR 24DB (R3 = 10K & R4 = 150K). ALSO,
NOTE THAT THE VALUES OF R3 & R4 ARE NOT CRITICAL AS FAR AS THEIR ABSOLUTE
VALUES ARE CONCERNED, WHAT IS CRITICAL, HOWEVER, IS THEIR RATIO
(AV = 1 + R4 /
R3). CHOOSE C7 TO GIVE AN UPPER 3DB FREQUENCY OF ABOUT 30KHZ - 50KHZ. I
HAVEN'T MEASURED THE ACTUAL POWER OUTPUT OF THE PROTOTYPE THAT I HAVE BUILT
AS YET, BUT I HAVE PUT IT TO NORMAL USE, NEVERTHELESS.
ANY TRANSISTORS WHICH SATISFY THE FOLLOWING CRITERIA CAN BE USED:

Q1/Q3: VMAX >= 40V, IMAX >= 1A, PMAX > = 5W, HFE > = 25, FT > = 50KHZ
Q2/Q4: VMAX >= 40V, IMAX >= 5A, PMAX > = 40W, HFE > = 20, FT > = 50KHZ
UNIT -8
DC VOLTAGE REGULATORS
Voltage regulators basics
voltage follower regulator
adjustable output regulator
precision voltage regulators
integrated circuit voltage regulators.
OP AMP REGULATOR WITH SERIES-PASS TRANSISTOR
CIRCUIT
WHAT IS THE FUNCTION OF A VOLTAGE REGULATOR CIRCUIT? I T’S BASICALLY THIS -

MAINTAIN A PRECISE VOLTAGE REGARDLESS OF THE CURRENT DRAWN BY THE LOAD. THREE
BASIC COMPONENTS ARE NEEDED TO ACHIEVE GOOD VOLTAGE REGULATION.
1. A PRECISION REFERENCE (ZENER DIODE) TO SET THE OUTPUT VOLTAGE.
2. A MUSCLE COMPONENT (TRANSISTOR) TO DELIVER THE REQUIRED CURRENT.
3. AN AUTOMATIC CONTROLLER (OPAMP) TO ADJUST THE TRANSISTOR DRIVE. THE ―PRIME

DIRECTIVE‖ OF THE OP AMP IS TO ADJUST THE BASE DRIVE OF Q1 DELIVERING THE
REQUIRED LOAD CURRENT WHILE KEEPING THE OUTPUT VOLTAGE AT A FIXED VALUE.
OUTPUT VOLTAGE
RESISTORS RF1 AND RF2 FEED A FRACTION OF THE REGULATOR OUTPUT VO TO THE OP
AMP'S NEGATIVE INPUT V-. THE OP AMP THEN ADJUSTS THE DRIVE TO Q1 SUCH THAT V- IS
EQUAL TO THE ZENER VOLTAGE VZ. WHEN THIS OCCURS, THE OUTPUT VOLTAGE IS
RELATED TO THE ZENER VOLTAGE THROUGH THE RF1, RF2 DIVIDER BY
WITH THE ZENER VOLTAGE AT ABOUT 3V AND RF2=10K, RF1=5K, THE OUTPUT VOLTAGE
SHOULD BE 3 X (1+10/5) = 9V. RUN A SIMULATION. WHAT IS THE OUTPUT VOLTAGE AT
V(2)?
HANDS-ON DESIGN SUPPOSE YOU’RE ASKED TO DESIGN A 12V REGULATOR. WHAT

VALUE OF RF2 WOULD YOU NEED WITH VZ = 3V? CHOOSE A NEW RF2 AND TEST DRIVE
YOUR CIRCUIT.
LOAD REGULATION
HOW WELL DOES THE REGULATOR PERFORM? ONE TEST IS TO APPLY A CHANGE IN THE
LOAD CURRENT AND SEE HOW WELL THE REGULATOR MAINTAINS ITS OUTPUT VOLTAGE.
CURRENT SOURCE IL GENERATES A 1A PULSE STARTING AT 10MS AND ENDING AT 20MS.

PLACE IL IN THE CIRCUIT BY REMOVING THE "*" AT THE BEGINNING OF THE IL STATEMENT.
RUN A SIMULATION AND PLOT THE LOAD CURRENT BY ADDING TRACE I(IL) TO THE PLOT
WINDOW.
THE OUTPUT SHOULD NOT CHANGE MUCH EXCEPT FOR THE APPEARANCE OF 2 SMALL
SPIKES.
THESE SPIKES SHOW THAT THE REGULATOR TAKES SOME FINITE TIME TO RESPOND
WHEN THE LOAD CURRENT CHANGES.
CIRCUIT INSIGHT WANT TO SEE THE AUTOMATIC CONTROLLER (OP AMP) IN ACTION?
PLOT THE Q1 BASE VOLTAGE V(3) TO SEE THE OP AMP INCREASE THE TRANSISTOR ON-
VOLTAGE WHEN THE DURING THE 1A PULSE. YOU CAN ALSO SEE THE OP AMP ACHIEVE ITS
PRIME DIRECTIVE OF MAINTAINING V- = VZ BY PLOTTING V(4) AND V(5).
LINE REGULATION
HOW WELL DOES THE REGULATOR HOLD THE OUTPUT VOLTAGE AS THE INPUT VOLTAGE
CHANGES? THE INPUT VOLTAGE IS A COMBINATION OF VIN (DC SOURCE AT 15V) AND VS
(AC SINEWAVE CURRENTLY SET TO 0V PEAK). TO TEST THE REGULATORS LINE
REGULATION, SET VS TO 1V PEAK BY EDITING THE VS STATEMENT TO LOOK LIKE
VS 1 10 SIN(0 1 1KHZ)
RUN A SIMULATION AND CHECK HOW MUCH VARIATION APPEARS AT V(2). WHAT CAUSES
THESE VARIATIONS? ONE FACTOR IS THE CHANGE IN ZENER VOLTAGE V(4) DUE TO A
CHANGE AT V(1). AS V(1) VARIES, THE CURRENT THROUGH RZ AND CONSEQUENTLY THE
ZENER DIODE VOLTAGE ALSO VARIES.
SIMULATION NOTE
THERE ARE TWO SEMICONDUCTORS MODELED HERE, ZENER DIODE D1N746 AND
TRANSISTOR Q1. THE DIODE PARAMETERS,(IS=5U RS=14 BV=2.81 IBV=5U), CAME FROM
THE MANUFACTURER’S WEB SITE. ACTUALLY THERE ARE MORE PARAMETERS THAN THESE
FOUR LISTED. THE UNLISTED ONES GET SET TO THEIR DEFAULT PARAMETERS. FOR THE
SIMPLE TRANSISTOR Q1 USED, ALL OF THE DEFAULT PARAMETERS ARE USED EXCEPT THE
CURRENT GAIN BF = 100.
CIRCUIT INSIGHT YOU CAN VIEW Q1’S BASE CURRENT BY ADDING IB(Q1) TO THE
PLOT WINDOW. HOW MUCH BASE CURRENT IS REQUIRED DURING THE 1A DRAW OF THE
LOAD? THE OP AMP SUPPLIES THIS CURRENT TO THE TRANSISTOR. HOWEVER, MANY OP
AMPS CAN ONLY DELIVER ABOUT 10MA! IF Q1 IS ASKING FOR MORE, YOU MAY NEED TO
GET AN OP AMP WITH MORE CURRENT OUTPUT MUSCLE OR A TRANSISTOR WITH GREATER
CURRENT GAIN BF. SET BF TO A HIGHER VALUE LIKE 200 AND CHECK IB(Q1) DURING THE
1A LOAD PULSE.
LM317T Variable Voltage Regulator
The LM317T is a adjustable 3 terminal positive voltage regulator capable of supplying in

excess of 1.5 amps over an output range of 1.25 to 37 volts. The device also has built in
current limiting and thermal shutdown which makes it essentially blow-out proof.
Output voltage is set by two resistors R1 and R2 connected as shown below. The voltage
across R1 is a constant 1.25 volts and the adjustment terminal current is less than 100uA.
The output voltage can be closely approximated from Vout=1.25 * (1+(R2/R1)) which
ignores the adjustment terminal current but will be close if the current through R1 and R2
is many times greater. A minimum load of about 10mA is required, so the value for R1
can be selected to drop 1.25 volts at 10mA or 120 ohms. Something less than 120 ohms
can be used to insure the minimum current is greater than 10mA. The example below
shows a LM317 used as 13.6 volt regulator. The 988 ohm resistor for R2 can be obtained
with a standard 910 and 75 ohm in series.
When power is shut off to the regulator the output voltage should fall faster than the
input. In case it doesn't, a diode can be connected across the input/output terminals to
protect the regulator from possible reverse voltages. A 1uF tantalum or 25uF electrolytic
capacitor across the output improves transient response and a small 0.1uF tantalum
capacitor is recommended across the input if the regulator is located an appreciable
distance from the power supply filter. The power transformer should be large enough so
that the regulator input voltage remains 3 volts above the output at full load, or 16.6 volts
for a 13.6 volt output.
LM317 Data Sheet
LM317T Voltage Regulator with Pass Transistor
The LM317T output current can be increased by using an additional power transistor to
share a portion of the total current. The amount of current sharing is established with a
resistor placed in series with the 317 input and a resistor placed in series with the emitter
of the pass transistor. In the figure below, the pass transistor will start conducting when
the LM317 current reaches about 1 amp, due to the voltage drop across the 0.7 ohm
resistor. Current limiting occurs at about 2 amps for the LM317 which will drop about
1.4 volts across the 0.7 ohm resistor and produce a 700 millivolt drop across the 0.3 ohm
emitter resistor. Thus the total current is limited to about 2+ (.7/.3) = 4.3 amps. The input
voltage will need to be about 5.5 volts greater than the output at full load and heat
dissipation at full load would be about 23 watts, so a fairly large heat sink may be needed
for both the regulator and pass transistor. The filter capacitor size can be approximated
from C=IT/E where I is the current, T is the half cycle time (8.33 mS at 60 Hertz), and E
is the fall in voltage that will occur during one half cycle. To keep the ripple voltage
below 1 volt at 4.3 amps, a 36,000 uF or greater filter capacitor is needed. The power
transformer should be large enough so that the peak input voltage to the regulator remains
5.5 volts above the output at full load, or 17.5 volts for a 12 volt output. This allows for a
3 volt drop across the regulator, plus a 1.5 volt drop across the series resistor (0.7 ohm),
and 1 volt of ripple produced by the filter capacitor. A larger filter capacitor will reduce
the input requirements, but not much.
High Current Regulated Supply

The high current regulator below uses an additional winding or a separate transformer to
supply power for the LM317 regulator so that the pass transistors can operate closer to
saturation and improve efficiency. For good efficiency the voltage at the collectors of the
two parallel 2N3055 pass transistors should be close to the output voltage. The LM317
requires a couple extra volts on the input side, plus the emitter/base drop of the 3055s,
plus whatever is lost across the (0.1 ohm) equalizing resistors (1volt at 10 amps), so a
separate transformer and rectifier/filter circuit is used that is a few volts higher than the
output voltage. The LM317 will provide over 1 amp of current to drive the bases of the
pass transistors and assumming a gain of 10 the combination should deliver 15 amps or
more. The LM317 always operates with a voltage difference of 1.2 between the output
terminal and adjustment terminal and requires a minimum load of 10mA, so a 75 ohm
resistor was chosen which will draw (1.2/75 = 16mA). This same current flows through
the emitter resistor of the 2N3904 which produces about a 1 volt drop across the 62 ohm
resistor and 1.7 volts at the base. The output voltage is set with the voltage divider
(1K/560) so that 1.7 volts is applied to the 3904 base when the output is 5 volts. For 13
volt operation, the 1K resistor could be adjusted to around 3.6K. The regulator has no
output short circuit protection so the output probably should be fused.
Simple Adjustable Voltage Source
A simple but less efficient methode of controlling a DC voltage is to use a voltage divider
and transistor emitter follower configuration. The figure below illustrates using a 1K pot
to set the base voltage of a medium power NPN transistor. The collector of the NPN
feeds the base of a larger PNP power transistor which supplies most of the current to the
load. The output voltage will be about 0.7 volts below the voltage of the wiper of the 1K
pot so the output can be adjusted from 0 to the full supply voltage minus 0.7 volts. Using
two transistors provides a current gain of around 1000 or more so that only a couple
milliamps of current is drawn from the voltage divider to supply a couple amps of current
at the output. Note that this circuit is much less efficient than the 555 timer dimmer
circuit using a variabe duty cycle switching approach. In the figure below, the 25 watt/ 12
volt lamp draws about 2 amps at 12 volts and 1 amp at 3 volts so that the power lost when
the lamp is dim is around (12-3 volts * 1 amp) = 9 watts. A fairly large heat sink is
required to prevent the PNP power transistor from overheating. The power consumed by
the lamp will be only (3 volts * 1 amp) = 3 watts which gives us an efficiency factor of
only 25% when the lamp is dimmed. The advantage of the circuit is simplicity, and also
that it doesn't generate any RF interference as a switching regulator does. The circuit can
be used as a voltage regulator if the input voltage remains constant, but it will not
compensate for changes at the input as the LM317 does.
2 Cell Lithium Ion Charger

This circuit was build to charge a couple series Lithium cells (3.6 volts each, 1 Amp Hour
capacity) installed in a portable transistor radio.
The charger operates by supplying a short current pulse through a series resistor and then
monitoring the battery voltage to determine if another pulse is required. The current can
be adjusted by changing the series resistor or adjusting the input voltage. When the
battery is low, the current pulses are spaced close together so that a somewhat constant
current is present. As the batteries reach full charge, the pulses are spaced farther apart
and the full charge condition is indicated by the LED blinking at a slower rate.
A TL431, band gap voltage reference (2.5 volts) is used on pin 6 of the comparator so
that the comparator output will switch low, triggering the 555 timer when the voltage at
pin 7 is less than 2.5 volts. The 555 output turns on the 2 transistors and the batteries
charge for about 30 milliseconds. When the charge pulse ends, the battery voltage is
measured and divided down by the combination 20K, 8.2K and 620 ohm resistors so that
when the battery voltage reaches 8.2 volts, the input at pin 7 of the comparator will rise
slightly above 2.5 volts and the circuit will stop charging.
The circuit could be used to charge other types of batteries such as Ni-Cad, NiMh or lead
acid, but the shut-off voltage will need to be adjusted by changing the 8.2K and 620 ohm
resistors so that the input to the comparator remains at 2.5 volts when the terminal battery
voltage is reached.
For example, to charge a 6 volt lead acid battery to a limit of 7 volts, the current through
the 20K resistor will be (7-2.5)/ 20K = 225 microamps. This means the combination of
the other 2 resistors (8.2K and 620) must be R=E/I = 2.5/ 225 uA = 11,111 ohms. But this
is not a standard value, so you could use a 10K in series with a 1.1K, or some other
values that total 11.11K
Be careful not to overcharge the batteries. I would recommend using a large capacitor in
place of the battery to test the circuit and verify it shuts off at the correct voltage.
Telephone In-Use Indicator
Telephone In-Use Relay Controller
Astable Multivibrator

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LINEAR IC’S AND APPLICATIONS

Department Of EEE, SJBIT Page 1

Sl.no Chapters Page no.

3 SIGNAL PROCESSING CIRCUITS 43 to 55

Department Of EEE, SJBIT Page 2

Capacitor coupled voltage follower

LEVEL SHIFTING STAGE:

Department Of EEE, SJBIT Page 3

An Operational Amplifier, or Op Amp, is a dual-input, single-output linear

Department Of EEE, SJBIT Page 4

Figure 1. Some Common Operational Amplifier Circuits

Another special characteristic of a close-looped op amp with negative feedback is the

Department Of EEE, SJBIT Page 5

INTERNAL CIRCUITRY OF OP-AMP:

CHARACTERISTICS (PARAMETERS) OF AN OP-AMP:

Department Of EEE, SJBIT Page 6

Input offset current (Iio):

Input bias current (IB):

Output offset voltage (VOO):

Common Mode Rejection Ratio (CMRR):

Department Of EEE, SJBIT Page 7

Gain Bandwidth product:

Properties of an ideal op-amp:

Department Of EEE, SJBIT Page 8

Vo= A∙Vid= A∙(V1-V2) = A∙(0-Vs)

Department Of EEE, SJBIT Page 9

Advantages of negative feedback op-amp:

iv. Decreases voltage gain.

Department Of EEE, SJBIT Page 10

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Department Of EEE, SJBIT Page 12

Department Of EEE, SJBIT Page 13

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Department Of EEE, SJBIT Page 15

SUBTRACTOR (INVERTING CONFIGURATION):

Department Of EEE, SJBIT Page 16

Department Of EEE, SJBIT Page 17

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OP AMP STABILITY AND INPUT CAPACITANCE

STABILITY THEORY REVIEW

Department Of EEE, SJBIT Page 21

Department Of EEE, SJBIT Page 22

THE OP AMP’S OPEN-LOOP GAIN AND PHASE (A IN EQUATION 1) ARE

Department Of EEE, SJBIT Page 23

56º AND GO UP TO THE PHASE CURVE INTERSECTION. AT THIS POINT, GO

THE EXTERNAL RESISTORS COME INTO PLAY WHEN THE OP AMP IS

Department Of EEE, SJBIT Page 24

APPROXIMATELY 87º; AND THE PERCENT OVERSHOOT IS NEGLIGIBLE.

ADDED INPUT CAPACITANCE AND ITS EFFECT

THE INPUT CAPACITOR, CIN, IS THE SUMMATION OF ALL THE INVERTING

BECAUSE THE LOW-FREQUENCY RESPONSE IS NOT SHOWN IN FIGURE 2.

Department Of EEE, SJBIT Page 26

OP AMP INPUT BIAS CURRENT

INPUT BIAS CURRENT

AMPLIFIER WITH BIAS CURRENT

Department Of EEE, SJBIT Page 27