IC-Project I-Synthesis
IC-Project I-Synthesis
Outline
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17-01-29
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Create
Netlist
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• If *.db is already available, include them in the link_library and • Every instance becomes unique.
target_library
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Read Design
Clock Defini,on Prepare Syntax- create_clock
Clock Definition
In DC, clock is ideal: no buffers, Specify Clock create_clock
[-period period_value] [-name clock_name]
no DRC, no op,miza,on
[source_objects]
InRequired Defini,ons
DC, clock is ideal: no -period period_value
buffers, no DRC, no The period of the clock waveform in library ,me units.
• clock period
optimization default unit is ns
• clock name -name clock_name
clock source
• Required Specifies the name of the clock being created.
• Definitions
• Duty cycle (50% default) source_objects
Clock period
– A clock constrains ,ming paths
-
A clock constrains
• (Offset/skew) Specifies a list of pins or ports on which to apply this clock.
Clock name between registers.
timing paths
–
– Clock source A design may have several clocks.
between registers. Example: create_clock clk –period 20 -name clk
–
(Duty cycle (50% default))
– Real clock synthesis in place and
(Offset/skew)
-
A design
route may have
several clocks.
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Real clock synthesis
Deepak Dasalukunte, EIT, LTH, Digital IC project and Verification takes place in PnR
Synthesis
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Read Design
Clock skew Synthesis Constraints Prepare
Worst case clock skew needs to be defined High speed vs low-area Specify Clock
• technology and design dependent
• not easy to determine Speed Specify
• Around 2% of clock period Constraints
Area
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Constraining Input Paths
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Needtoto
Need Specify
Specify propagation
propagation Deepak Dasalukunte, EIT, LTH, Digital IC project and Verification Synthesis
delay of external logiclogic
delay of external that that
drives your logic set_input_delay –max 5.6 –clock clk [get_ports A]
drives your logic
Constraining Area
• For a high-speed circuit do not set any area constraint but • The command compile performs logic and gate-level Specify Clock
specify a high clock frequency. synthesis and op,miza,on on the current design.
• Op,miza,on is controlled by user-specified constraints Specify
• For an area op,mized circuit set area to 0 and specify a low • to obtain smallest possible circuit Constraints
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compile [-map_effort low | medium | high] -map_effort All possible viola,ons need to be checked by execu,ng:
report_constraint -all_violators
Rela,ve amount of CPU ,me spent during mapping phase of
compile. Default : Medium effort. Other commands to check design:
report_design
Example: compile -map_effort high report_area –hierarchy report_Xming –max_paths no_of_paths
Thereaser, a netlist can be wriXen in several formats
More switches for compile are available but not scope of this • VHDL
presenta,on!! • Verilog
• db or ddc (Synopsys specific format)
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