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    Gatelevel Modeling

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    Giri Reddy
    This document summarizes gate-level modeling in Verilog. It describes how circuits are specified using logic gates and their interconnections. It lists the 12 basic gate primitives recognized by Verilog and explains gate instantiation. Examples are provided to demonstrate gate-level modeling of half adders, full adders, and multiplexers. Gate delays can also be specified in Verilog.

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    © All Rights Reserved
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    Gatelevel Modeling

    Uploaded by

    Giri Reddy
    73 views13 pages
    This document summarizes gate-level modeling in Verilog. It describes how circuits are specified using logic gates and their interconnections. It lists the 12 basic gate primitives recognized by Verilog and explains gate instantiation. Examples are provided to demonstrate gate-level modeling of half adders, full adders, and multiplexers. Gate delays can also be specified in Verilog.

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    Basics of Gate Level modelling

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    This document summarizes gate-level modeling in Verilog. It describes how circuits are specified using logic gates and their interconnections. It lists the 12 basic gate primitives recognized by Verilog and explains gate instantiation. Examples are provided to demonstrate gate-level modeling of half adders, full adders, and multiplexers. Gate delays can also be specified in Verilog.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    73 views13 pages

    Gatelevel Modeling

    Uploaded by

    Giri Reddy
    This document summarizes gate-level modeling in Verilog. It describes how circuits are specified using logic gates and their interconnections. It lists the 12 basic gate primitives recognized by Verilog and explains gate instantiation. Examples are provided to demonstrate gate-level modeling of half adders, full adders, and multiplexers. Gate delays can also be specified in Verilog.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 13

    Gate-Level Modeling

    A circuit is specified by its logic gates and their


    interconnection.
    Verilog recognizes 12 basic gates as predefined primitives.
    Instantiation is similar to module instantiation. But no
    definition is required.
    Basic gates-primitives
    and
    or
    xor
    nand
    nor
    xnor
    buf
    not
    bufif1, bufif0
    notif1, notif0
    buf/not
    and/or
    (Multiple-
    input gates)
    (Multiple-
    output gates)
    b d
    c
    a
    b
    c
    a
    b
    a
    and 0 1 x z
    0 0 0 0 0
    1 0 1 x x
    x 0 x x x
    z 0 x x x
    or 0 1 x z
    0 0 1 x x
    1 1 1 1 1
    x x 1 x x
    z x 1 x x
    nand 0 1 x z
    0 1 1 1 1
    1 1 0 x x
    x 1 x x x
    z 1 x x x
    nor 0 1 x z
    0 1 0 x x
    1 0 0 0 0
    x x 0 x x
    z x 0 x x
    Truth Table
    tri-state gates: bufif1, bufif0, notif1, notif0
    a
    b
    c
    notif0 (a, b, c)
    e.g.
    bufif1 (a, b, c)
    e.g.
    a
    b
    c
    xor 0 1 x z
    0 0 1 x x
    1 1 0 x x
    x x x x x
    z x x x x
    xnor 0 1 x z
    0 1 0 x x
    1 0 1 x x
    x x x x x
    z x x x x
    buf not
    input output input output
    0 0 0 1
    1 1 1 0
    x x x x
    z x z x
    bufif0 control input
    0 1 x z
    data 0 0 z L L
    input 1 1 z H H
    x x z x x
    z x z x x
    notif0 control input
    0 1 x z
    data 0 1 z H H
    input 1 0 z L L
    x x z x x
    z x z x x
    x={0,1,z} L={0,z} H={1,z}
    bufif1,notif1 ??
    Gate Instantiation of And/Or Gates
    wire OUT, IN1, IN2;
    // basic gate instantiations.
    and a1 (OUT, IN1, IN2);
    nand na1 (OUT, IN1, IN2);
    or or1 (OUT, IN1, IN2);
    nor nor1 (OUT, IN1, IN2);
    xor x1 (OUT, IN1, IN2);
    xnor nx1 (OUT, IN1, IN2);

    // More than two inputs; 3 input nand gate
    nand na1_3inp (OUT, IN1, IN2, IN3);
    // gate instantiation without instance name
    and (OUT, IN1, IN2); // legal for primitive gates
    Array of Instances



    and n_gate[3:0](OUT, IN1, IN2);

    This is equivalent to the following 4 instantiations
    and n_gate0(OUT[0], IN1[0], IN2[0]);
    and n_gate1(OUT[1], IN1[1], IN2[1]);
    and n_gate2(OUT[2], IN1[2], IN2[2]);
    and n_gate3(OUT[3], IN1[3], IN2[3]);

    Examples
    1)Half Adder
    SUM=XY
    CARRY= X.Y
    module add_half ( sum, carry, x, y );
    input x, y;
    output sum, carry;
    xor (sum, x, y);
    and (carry, x, y);
    endmodule
    2)Full Adder(1bit)
    SUM=ABCin
    Cout=A.B+Cin(AB)
    module fullAdder1 ( sum, c_out, a, b, c_in );
    input a, b, c_in;
    output sum, c_out;
    wire n1, n2, n3;
    xor (n1, a, b);
    xor (sum, n1, c_in);
    and (n2, n1, c_in);
    and (n3, a, b);
    or (c_out, n2, n3);
    endmodule
    n1
    n2
    n3
    3) 4bit Full Adder


    w1 w2 w3
    module fullAdder4 ( S, Co, A, B, Ci );
    input [4:1]A, B;
    input Ci;
    output [4:1]S;
    output Co;
    wire w1, w2, w3;
    fullAdder1 fa0( S[1], w1, A[1], B[1], Ci );
    fullAdder1 fa1( S[2], w2, A[2], B[2], w1 );
    fullAdder1 fa2( S[3], w3, A[3], B[3], w2 );
    fullAdder1 fa3( S[4], Co, A[4], B[4], w3 );
    endmodule



    module Stimulus;
    reg [4:1]A, B;
    reg Ci;
    wire [4:1]S;
    wire Co;

    fullAdder4 f1 ( S, Co, A, B, Ci );

    initial
    begin
    $monitor ($time,S=%b Co=%b A=%b B=%b Ci=%b \n, S, Co, A, B, Ci);
    end

    initial
    begin
    A=4d1 ; B=4d0 ; Ci=4d3;
    #2 A=4d1 ; B=4d2; Ci=4d3;
    #5 A=4d4; B=4d0; Ci=4d2;
    #1 A=4d1; B=4d8; Ci=4d1;
    end
    4) 4-1 MUX




    module mux4( out, s, d );
    input[1:0] s;
    input[3:0] d;
    output out;
    wire q1, q2, q3, q4, ns0, ns1;

    not ( ns0, s[0] );
    not ( ns1, s[1] );
    and ( q1, ns0, ns1, d[0] );
    and ( q2, s[0], ns1, d[1] );
    and ( q3, ns0, s[1], d[2] );
    and ( q4, s[0], s[1], d[3] );
    or ( out, q1, q2, q3, q4 );
    endmodule
    Truth Table
    S1 S0 Out
    0 0 d0
    0 1 d1
    1 0 d2
    1 1 d3
    module test_bench;
    reg[1:0] S;
    reg[3:0] D;
    wire OUT;
    mux4 m1(.d(D), .out(OUT), .s(S));
    initial
    begin
    S=2b00;
    D=4b0110;
    #2 $display (OUT=%b \n,OUT);
    S=2b01;
    #3 $display (OUT=%b \n,OUT);
    S=2b10;
    #1 $display (OUT=%b \n,OUT);
    S=2b11;
    #1 $display (OUT=%b \n,OUT);
    end
    endmodule

    $monitor
    Gate Delays
    or #(1) o1(out1, in1, in2); //Delay of 1 for all transitions
    and #(5,6) a2(out, in1, in2); // Rise = 5, Fall = 6
    bufif0 #(1,2,3) b1 (out, in, ctrl); // Rise = 1, Fall = 2, Turn-off = 3

    nand #(5:6:7) n1(out, in1, in2); // mindelay= 5 ,typdelay=6, maxdelay=7

    and #(3:4:5, 5:6:7) a2(out, i1, i2);
    // if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
    //if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
    //if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)

    and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
    //if +mindelays, rise= 2 fall= 3 turn-off = 4
    // if +typdelays, rise= 3 fall= 4 turn-off = 5
    // if +maxdelays, rise= 4 fall= 5 turn-off = 6
    Verilog-XL

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