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    Experiment 6: Adder/subtractor Block Diagram:: VHDL Code: Xor Gate

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    padmavasavi1973
    The document describes an experiment implementing an adder/subtractor circuit using VHDL and Verilog. It includes the block diagram, VHDL code for a half adder, full adder, and top module, as well as Verilog code for the same components. Test benches are provided in both VHDL and Verilog to test the design. Device utilization and timing results are reported.

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    Attribution Non-Commercial (BY-NC)
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    Experiment 6: Adder/subtractor Block Diagram:: VHDL Code: Xor Gate

    Uploaded by

    padmavasavi1973
    55 views7 pages
    The document describes an experiment implementing an adder/subtractor circuit using VHDL and Verilog. It includes the block diagram, VHDL code for a half adder, full adder, and top module, as well as Verilog code for the same components. Test benches are provided in both VHDL and Verilog to test the design. Device utilization and timing results are reported.

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    Expeiment 6

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    The document describes an experiment implementing an adder/subtractor circuit using VHDL and Verilog. It includes the block diagram, VHDL code for a half adder, full adder, and top module, as well as Verilog code for the same components. Test benches are provided in both VHDL and Verilog to test the design. Device utilization and timing results are reported.

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    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    55 views7 pages

    Experiment 6: Adder/subtractor Block Diagram:: VHDL Code: Xor Gate

    Uploaded by

    padmavasavi1973
    The document describes an experiment implementing an adder/subtractor circuit using VHDL and Verilog. It includes the block diagram, VHDL code for a half adder, full adder, and top module, as well as Verilog code for the same components. Test benches are provided in both VHDL and Verilog to test the design. Device utilization and timing results are reported.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 7

    Experiment 6: Adder/subtractor

    Block Diagram:

    Vhdl code:

    Xor gate:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity xorgate is
    port ( a,b:in std_logic;
    z:out std_logic);
    end xorgate;
    architecture Behavioral of xorgate is
    begin
    z <= a xor b;
    end Behavioral;

    Half adder:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity halfadder is
    port(a,b:in std_logic;
    sum,carry:out std_logic);
    end halfadder;
    architecture Behavioral of halfadder is
    begin
    process(a,b)
    begin
    sum <= a xor b;
    carry<= a and b;
    end process;
    end Behavioral;
    Full adder:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity fulladder is
    port(a,b,c:in std_logic;
    sum,carry:out std_logic);
    end fulladder;

    architecture struct of fulladder is


    component halfadder
    port(a,b:in std_logic;
    sum,carry:out std_logic);
    end component;
    signal s1,c1,c2:std_logic;
    begin
    u1:halfadder port map( a,b,s1,c1);
    u2:halfadder port map(c,s1,sum,c2);
    carry<= c1 or c2;
    end struct;

    Top Module:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity add_sub is
    port(a:in std_logic_vector(3 downto 0);
    b:in std_logic_vector(3 downto 0);
    s:in std_logic;
    y:out std_logic_vector(3 downto 0));
    end add_sub;
    architecture struct of add_sub is
    component xorgate port ( a,b:in std_logic;
    z:out std_logic);
    end component;

    component fulladder
    port(a,b,c:in std_logic;
    sum,carry:out std_logic);
    end component ;

    signal x1,x2,x3,x4,c1,c2,c3,c4:std_logic;
    begin
    u1:xorgate port map(b(0),s,x1);
    u2:xorgate port map(b(1),s,x2);
    u3:xorgate port map(b(2),s,x3);
    u4:xorgate port map(b(3),s,x4);
    u5:fulladder port map(s,x1,a(0),y(0),c1);
    u6:fulladder port map(c1,x2,a(1),y(1),c2);
    u7:fulladder port map(c2,x3,a(2),y(2),c3);
    u8:fulladder port map(c3,x4,a(3),y(3),c4);
    end struct;

    Test bench in VHDL:


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    entity add_sub_tb is
    end ;
    architecture test of add_sub_tb is

    component add_sub is
    port(a:in std_logic_vector(3 downto 0);
    b:in std_logic_vector(3 downto 0);
    s:in std_logic;
    y:out std_logic_vector(3 downto 0));
    end component;

    signal a:std_logic_vector(3 downto 0);


    signal b:std_logic_vector(3 downto 0);
    signal s:std_logic;
    signal y:std_logic_vector(3 downto 0);
    begin
    u1:add_sub port map(a,b,s,y);
    process
    begin
    s<='0';a<="1101"; b<="0101";
    wait for 0.5 us;
    s<='1';a<="1101"; b<="0101";
    wait for 0.5 us;
    end process;
    end test;

    Verilog code:

    Half adder:
    module halfadder(sum,carry,a,b);
    input a;
    input b;
    output sum;
    output carry;
    xor x1(sum,a,b);
    and a1(carry,a,b);
    endmodule

    Full adder:
    module fulladder (sum,carry,a,b,c);
    input a;
    input b;
    input c;
    output sum;
    output carry;
    wire s1;
    wire c1;
    wire c2;
    halfadder h1(s1,c1,a,b);
    halfadder h2(sum,c2,s1,c);
    or o1(carry,c1,c2);
    endmodule
    Top Module:
    module addsub(y,a,b,s);
    input s;
    input [3:0]a;
    input [3:0]b;
    output [3:0]y;
    wire [3:0]y;
    wire p1,p2,p3,p4,c1,c2,c3,c4;
    xor x1(p1,b[0],s);
    xor x2(p2,b[1],s);
    xor x3(p3,b[2],s);
    xor x4(p4,b[3],s);

    fulladder f1(y[0],c1,a[0],p1,s);
    fulladder f2(y[1],c2,a[1],p2,c1);
    fulladder f3(y[2],c3,a[2],p3,c2);
    fulladder f4(y[3],c4,a[3],p4,c3);
    endmodule

    Waveform in Xilinx:
    Test bench in verilog:
    `timescale 1us / 1ps
    module add_sub_tb( );
    reg s;
    reg [3:0]a;
    reg [3:0]b;
    wire [3:0]y;
    addsub as(y,a,b,s);
    initial
    begin
    s<=1'b0;a<=4'b1101; b<=4'b0101;
    #4
    s<=1'b1;
    end
    endmodule

    Waveform in Xilinx:

    RTL schematic:
    Device utilization:
    Design Statistics
    # IOs : 13
    Cell Usage :
    # BELS : 21
    # AND2 :6
    # OR2 :3
    # XOR2 : 12
    # IO Buffers : 13
    # IBUF :9
    # OBUF :4
    Total REAL time to Xst completion: 6.00 secs
    Total CPU time to Xst completion: 5.27 secs
    Total memory usage is 233192 kilobytes

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