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    FA Wave

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    Juhi Choudhary
    The VHDL code provides an example of using structural modeling to implement a full adder circuit by defining 3-input XOR, 2-input AND, and 3-input OR gates as components. The full adder entity instantiates these components, mapping inputs and outputs and using internal signals to connect the components. Implementations for each component type are also provided at the bottom using behavioral modeling.

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    FA Wave

    Uploaded by

    Juhi Choudhary
    22 views5 pages
    The VHDL code provides an example of using structural modeling to implement a full adder circuit by defining 3-input XOR, 2-input AND, and 3-input OR gates as components. The full adder entity instantiates these components, mapping inputs and outputs and using internal signals to connect the components. Implementations for each component type are also provided at the bottom using behavioral modeling.

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    The VHDL code provides an example of using structural modeling to implement a full adder circuit by defining 3-input XOR, 2-input AND, and 3-input OR gates as components. The full adder entity instantiates these components, mapping inputs and outputs and using internal signals to connect the components. Implementations for each component type are also provided at the bottom using behavioral modeling.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    22 views5 pages

    FA Wave

    Uploaded by

    Juhi Choudhary
    The VHDL code provides an example of using structural modeling to implement a full adder circuit by defining 3-input XOR, 2-input AND, and 3-input OR gates as components. The full adder entity instantiates these components, mapping inputs and outputs and using internal signals to connect the components. Implementations for each component type are also provided at the bottom using behavioral modeling.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 5

    Q. Write the VHDL Code for using structural modeling.

    Ans.

    VHDL CODE

    library ieee;
    use ieee.std_logic_1164.all;

    entity FA is
    port(a,b,cin:in std_logic;
    sum,carry: out std_logic);
    end FA;

    architecture FA_SM of FA is
    component xor3
    port(a1,b1,c1:in std_logic;
    o1:out std_logic);
    end component;

    component and2
    port(a2,b2:in std_logic;
    o2:out std_logic);
    end component;

    component or3
    port(a3,b3,c3:in std_logic;
    o3:out std_logic);
    end component;

    signal t1,t2,t3:std_logic;
    begin
    U1:xor3 port map(a,b,cin,sum);
    U2:and2 port map(a,b,t1);
    U3:and2 port map(b,cin,t2);
    U4:and2 port map(a,cin,t3);
    U5:or3 port map(t1,t2,t3,carry);
    end FA_SM;

    --Here 3- input XOR gate, 2-input AND gate and 3-input OR gate are used as a
    component.

    --COMPONENT USED:

    -------------
    --xor3
    -------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity xor3 is
    port(a1,b1,c1:in std_logic;
    o1:out std_logic);
    end xor3;

    architecture xor3_DF of xor3 is


    signal s0:std_logic;
    begin
    s0<=a1 xor b1;
    o1<=s0 xor c1;
    end xor3_DF;
    ---------------------------------
    -- and2
    ------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity and2 is
    port(a2,b2:in std_logic;
    o2:out std_logic);
    end and2;

    architecture and2_DF of and2 is


    begin
    o2<=a2 and b2;
    end and2_DF;

    -------------------------
    -- or3
    --------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity or3 is
    port(a3,b3,c3:in std_logic;
    o3:out std_logic);
    end or3;

    architecture or3_DF of or3 is


    signal s1:std_logic;
    begin
    s1<=a3 or b3;
    o3<=s1 or c3;
    end or3_DF;

    WAVE FORM

    Try Yourself:
    Que:1 Write the code for Full Adder Using Half Adder as a component.

    Que:2 Write the the code for Full Adder for given structure.

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