Muratore

A Study of Successive
Approximation Register
ADC Architectures
A Ph.D. Thesis by
Dante Gabriel Muratore
Advisor: Prof. Franco Maloberti

Co-Advisor: Prof. Edoardo Bonizzoni
Integrated Microsystems Lab (IMS)
University of Pavia
2017 – XXIX
To
Claudia
Acknowledgements
First of all I want to thank my advisor Franco Maloberti. He promised me that

this would have been a fun and interesting travel, and I can truly say he was right.
He transmitted to me both technical and intuitive skills during these three years and
provided continuous challenges that helped me to take the most out of my time spent
at the IMS Labs. His love for this job and his enthusiasm are a model to follow for
young researchers like me.
Edoardo Bonizzoni was always there when I needed him and for this I am very
grateful. He advised me on so many different levels that it would be impossible to
list them all. My Ph.D. would have not been the same without the complementary
support and friendship that he provided throughout.
The IMS team contributed immensely to my personal and professional time at
University of Pavia. They have been a source of friendships as well as good advice
and collaboration. Prof. Piero Malcovati was an unlimited source of solutions to all
my Cadence related problems. Alper has been an excellent colleague and I am very
happy he decided to join the Lab for a Ph.D. as well. Alessandro, Marco, Nicola,
Arun, Basak and Claudio made my days a bit less like working and a bit more like
hanging out with friends.
During my first project I had the honour to collaborate with the AMS Italy team
located in Pavia. This experience was of great growth for me and it was possible
thanks to the support of excellent persons like Carlo Fiocchi, Matteo Colombo, Si-
mone Verri and the rest of the group.
My second project made me work with the State Key Laboratory of Analog and
Mixed Signal VLSI of the University of Macau. I would like to thank Terry and
Alpha for the long Skype calls and the invaluable help they provide to my first tape-
out.
During my time at the Massachusetts Institute of Technology I found a great
advisor and a research group that welcomed me as one of them. Working with Prof.
Harry Lee and his group was extremely stimulating and to experience a different
way of working immensely improve my development as a researcher. I would like
to especially thank Sabino for all the support and the coffee breaks during my time
at MIT.
vii
viii Acknowledgements
Lastly, I would like to thank my family for all their love and encouragement.
For my parents who raised me with the importance of pursuing knowledge and
supported me in all my life. For my brother Franco that, even living far away, was
always present and making me feel his backing, you are my best friend. And most of
all for my loving wife Claudia, whose presence constantly reminds me of the beauty
of my life. Thank you.
Dante Gabriel Muratore
University of Pavia
February 2017
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation and Structure of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Data Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Nyquist Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Oversampled ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Data Converter Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 The State of the Art in SAR ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in

65-nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 Circuit Blocks Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.1 Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.2 Bootstraped sampling switch . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.3 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.4 Comparator with built-in preamplification . . . . . . . . . . . . . . . 37
2.3.5 Preamplifier with embedded thresholds generation . . . . . . . . 39
2.3.6 Calibration system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3 A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring . . . . 51

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2.1 Coarse step: 8-channel TI incremental ADC . . . . . . . . . . . . . . 53
3.2.2 Fine step: SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.1 High Voltage Track & Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ix
x Contents
3.3.2 Operational amplifier with chopping technique . . . . . . . . . . . 60

3.3.3 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 A 200 µW 12-b 8 MS/s SAR ADC for Ultrasound Systems . . . . . . . . . . 71

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.1 R-C DAC tradeoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.2 ADC timing and searching algorithm . . . . . . . . . . . . . . . . . . . . 74
4.3.1 Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
List of Figures
1.1 Basic block diagram of the full-flash converter. . . . . . . . . . . . . . . . . . . . 3

1.2 Timing (a) and flow diagram (b) of the successive approximation
technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Basic block diagram of the SAR converter. . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Charge redistribution implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Basic block diagram of the pipeline converter. . . . . . . . . . . . . . . . . . . . 7
1.6 Out-of-band noise rejection and decimation of a noise shaped signal. 8
1.7 Incorporating the quantizer in a feedback loop obtains noise shaping. 9
1.8 (a) Sampled-data first order sigma delta modulator and (b) its linear
model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.9 First-order incremental ADC block diagram. . . . . . . . . . . . . . . . . . . . . . 12
1.10 Second-order incremental ADC block diagram. . . . . . . . . . . . . . . . . . . 12
1.11 ADC architecture comparison, [5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.12 Walden figure of merit at Nyquist (FoMW,h f ) as a function of
the conversion rate (f snyq ) for ADCs presented in the IEEE
International Solid-State Circuits Conference (ISSCC) from 1997
to 2016. Data extrapolated from [58]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Searching algorithm with redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2 Architecture of the proposed Flash-SAR ADC. . . . . . . . . . . . . . . . . . . . 28
2.3 Divider-assisted timing logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Timing diagram of the phases generated by the logic of Fig.2.3. . . . . . 30
2.5 Switch driving registers for the flash section of the capacitive DAC. . 30
2.6 Switch driving registers for the SAR section of the capacitive DAC. . 30
2.7 Description of the bootstrapping technique. . . . . . . . . . . . . . . . . . . . . . . 32
2.8 Schematic view of the bootstrap logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.9 Flash converter architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.10 Comparator input stage in flash ADC for pMOS part. (a) Standard
approach. (b) Proposed solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 Comparator input stage in flash ADC for nMOS part. (a) Standard
xi
xii List of Figures
2.12 Comparison between input stages of dynamic latch and

preamplifier. (a) M0 is a switch. (b) M0 is a current generator. . . . . . . 37
2.13 Improved sense amplifier latch schematic. (a) nMOS input stage.
(b) pMOS input stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.14 Simulated pre-layout time response versus differential input for this
work, the SA latch and the preamplified SA latch. . . . . . . . . . . . . . . . . 38
2.15 Preamplifier with embedded thresholds generation. . . . . . . . . . . . . . . . 39
2.16 Preamplifier schematic with dummy structure and double output
branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.17 Calibration system embedded in the latch. . . . . . . . . . . . . . . . . . . . . . . . 41
2.18 Chip microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.19 Test board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.20 Measured SNDR as a function of the sampling frequency for
different supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.21 Measured DNL and INL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.22 Measured output spectrum at f s = 500 MS/s. (Output decimated by
25x). (a) Input signal at 22 MHz. (b) Input signal at 249 MHz. . . . . . . 44
2.23 Measured output spectrum at f s = 700 MS/s. (Output decimated by
25x).(a) Input signal at 22 MHz. (b) Input signal at 349 MHz. . . . . . . 44
2.24 Measured SNDR as a function of the input frequency for different
sampling frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.25 Power breakdown of the ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.26 Walden figure of merit at Nyquist (FoMW,h f ) as a function of the
conversion rate (f snyq ) for single-channel ADCs with ENOB higher
than 5 bits presented in the IEEE International Solid-State Circuits
Conference (ISSCC) from 1997 to 2016. Data extrapolated from [58]. 47
3.1 Battery monitor architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2 Battery discharge profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Battery monitor during incremental conversion with timing
diagram of the phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4 Battery monitor during SAR phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.5 Mismatch cancellation technique during charge transfer to CS AR .
(a) Auto-zero phase. (b) Charge transfer from incremental channel
to SAR array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.6 CS AR array architecture. 5 bits are implemented in a binary fashion,
and 3 bits use a C-2C structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.7 High-voltage track & hold. (a) Schematic. (b) Offset due to ron . . . . . . 58
3.8 Proposed high-voltage track & hold with dummy structure. . . . . . . . . 58
3.9 Sampling error as a function of the input voltage. (a) Standard
3.10 Schematic view of the operational amplifier with chopping technique. 60
3.11 Chopper technique basic scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.12 Comparator schematic view of the comparator with preamplifier. . . . . 63
3.13 Chip microphotograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List of Figures xiii
3.14 Testing board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.15 Histogram of 300 repeated measures with VIN = VCM . . . . . . . . . . . . . 65
3.16 Measured output spectrum (FFT with 218 points). . . . . . . . . . . . . . . . . 65
3.17 Measured INL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.18 Measured DNL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.19 Measured output (average of 100 measurements) of the ADC when
the same input is applied to all the channels. . . . . . . . . . . . . . . . . . . . . . 67
3.20 Measured battery monitor power breakdown. . . . . . . . . . . . . . . . . . . . . 67
4.1 Architecture of the transcranial Doppler ultrasound system. [1] . . . . . 72

4.2 Architecture of the SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3 Timing diagram of the SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 R-DAC steps for the last 5 LSBs conversion. . . . . . . . . . . . . . . . . . . . . . 75
4.5 Self-timed phase generator. (a) Schematic view. (b) Timing
diagram. (c) Layout view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.6 End of comparison logic block. (a) Schematic view. (b) Layout view. 77
4.7 Shift register block. (a) Schematic view. (b) Layout view. . . . . . . . . . . 77
4.8 Switch driving registers for the capacitive steps of the DAC. (a)
Schematic view. (b) Layout view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.9 Layout view of the switch driving registers and the decoder for the
resistive steps of the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.10 Layout placement of the C-DAC for limiting systematic mismatch. . . 80
4.11 Layout view of the DAC, including the DAC switches and the
bootstrap logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.12 Schematic view of the bootstrap logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.13 Double-tail latch. (a) Schematic view. (b) Layout view. . . . . . . . . . . . . 83
4.14 Post-layout simulated output spectrum for fin = 2.21 MHz and f s =
8 MS/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.15 Post-layout noise-tran simulated output spectrum for fin = 1.8 MHz
and f s = 8 MS/s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.16 Simulated ADC power breakdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
List of Tables
1.1 Comparison of ADC architectures, [5]. . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Latches bank connections to preamplifier outputs. . . . . . . . . . . . . . . . . 41

2.2 Performance summary and comparison table. . . . . . . . . . . . . . . . . . . . . 46
3.1 Performance summary and comparison table. . . . . . . . . . . . . . . . . . . . . 68
4.1 ADC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
xv
Chapter 1
Introduction
1.1 Motivation and Structure of the Thesis
In the era of all-mobile devices and the Internet of Things, power efficient solutions
are required by new applications. Wearables and battery supplied systems are in
high demand, asking designers to come up with new ideas for ultra low-power high-
performances data converters. Among all the possible architectures, SAR ADCs
stand out because of their high efficiency. Besides, the quasi all-digital nature of this
topology greatly adapts to the technological scaling and the simple structure better
suits to more complex system-level designs. Apart from being an excellent choice
as a stand-alone or time-interleaved architecture, SAR ADCs are particularly suited
for hybrid solutions that further pushes away the limits of other types of converters,
such pipeline or oversampled ADCs.
The goal of this thesis is to study the versatility and adaptability of the SAR
algorithm for different applications. In order to do so, 3 different projects carried
out during the Ph.D. activity are presented. These are
1. An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm
CMOS.
2. A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring.
3. A 200 µW 12-b 8 MS/s SAR ADC for Ultrasound Systems.
The presented ADCs highly differ from the performances point of view, but they
all share the fact that they use the SAR algorithm to meet the requirements of the
given application. The first two projects were fabricated and tested, while the third
has been simulated at post-layout level.
Project # 1 is a high-speed single-channel ADC for wireline communications.
The architecture uses a sub-ranging approach with a flash converter and a multi-
bit per cycle SAR ADC. Redundancy is applied to relax the accuracy requirements
of the first stages, and a shift-register free logic is implemented. Thresholds in the
multi-bit per cycle SAR converter are produced by a special preamplifier that uses
an interpolation-like technique. A novel comparator speeds up the overall operation
1
2 1 Introduction
of the converter, by using a built-in preamplifier that initially unbalances the output
of the latch.
Project # 2 implements an extended-range ADC for monitoring the voltages of
a stack of 8 Li-Ion batteries. The system uses an 8-channel TI-incremental ADC
for the coarse conversion of the battery cell voltages, and a single SAR ADC for
the fine conversion. The high-voltage section is limited to 8 switches and a high-
voltage capacitor reducing the cost of the converter. The remaining part of the circuit
operates at a nominal 5-V supply. The time-interleaved structure obtains an almost-
simultaneous sampling of the battery cells, and the single fine converter limits the
mismatch between channels.
Project # 3 is a very compact SAR ADC for ultrasound pixel-arrayed systems.
The ADC is intended to be used in the acquisition channel of a wearable tran-
scranial doppler ultrasound system (TCD) to measure cerebral blood flow veloc-
ity (CBFV) at the middle cerebral artery (MCA). There are 64 such channels, so
area and power constraints are the most stringent specifications. An hybrid resistive-
capacitive structure is used to reduce the area of the DAC, while an asynchronous
logic optimises the timing of the converter and the power consumption.
This chapter introduces to the reader the most common data converter architec-
tures and provides a discussion on the evolution of data converter during the past
years. Finally, a research on the state-of-the-art in SAR ADCs is provided. Chapters
2, 3 and 4 present the three different projects (# 1, # 2 and # 3), while conclusions
are drawn in Chapter 5. The bibliography is dedicated for each chapter in order to
provide a more direct access to the reader.
1.2 Data Converter Architectures
The first specification which defines a data converter is its type. The conversion
algorithm normally provides this kind of information. The types of converters are
classified in two main categories: Nyquist rate and oversampling. This distinguishes
between the following design strategies: using an input that occupies a large frac-
tion of the available bandwidth or using an input-band that only occupies a small
part of the Nyquist range1 . The ratio between the Nyquist limit and the signal band,
f s /2(fB ), is called oversampling ratio (OSR). Converters with a large OSR are called
oversampling converter, whereas Nyquist-rate converters have a small OSR, typi-
cally less than 8.
The main architecture’s way of operation are described below. For a more accu-
rate analysis on ADC specifications and topologies the reader can refer to [1–3].
1 The Nyquist-Shannon sampling theorem states that “A band limited signal, x(t), whose Fourier
spectrum, X(jω), vanishes for angular frequencies | ω |> ω s /2 is fully described by an uniform
sampling x(nT), where T = 2π/ω s .” The Nyquist range becomes [0 - f s ], where f s is the sampling
frequency.
1.2 Data Converter Architectures 3
1.2.1 Nyquist Rate
1.2.1.1 Flash ADCs
The flash architecture uses a parallel conversion algorithm. An n-bit quantizer iden-
tifies 2n bins with 2n - 1 transition points; therefore, the converter requires 2n - 1
reference voltages and 2n - 1 comparators. The output of the comparators will be
logic 1 up to the input level and logic 0 above. A decoder can then translate this
thermometric representation into an n-bit digital output.
Fig. 1.1 shows the basic block diagram of a full-flash ADC, where the reference
voltages are generated by a resistive divider. The input is sampled by a sample &
hold circuit (S&H) into the positive input of the comparator, while the reference
voltage is applied at the negative input. Only one clock cycle is required for the
conversion, as all comparators work at the same time.
Full-flash converters are the optimum for very high-speed, but the resolution can-
not be very high as a number of limits make the implementation unpractical. A first
issue concerns the availability of a reference voltage divider that can operate at very
high-speed and high-resolution. Another practical limit that determines the maxi-
VIN
Vref+
S&H Thermometric Binary
signals signals
RU
Vr(2n-1)
2RU
Vr(2n-2)
2RU
bN-1
DECODER
Vr(2n-3)
bN-2
2RU Digital
bN-3 Output
n-bit
b1
Vr(1)
b0
2RU
Vr(0) N=2n
RU
Vref-
Fig. 1.1 Basic block diagram of the full-flash converter.

4 1 Introduction
mum resolution is the exponential increase of the circuit complexity with the num-
ber of bits: every additional bit doubles both the silicon area and, more importantly,
the power consumption. Furthermore, a larger resolution increases the capacitance
load at the output of the S&H caused by the parasitic capacitance of the compara-
tors. Usually, passive S&H are used in order to reduce power consumption. But,
increasing the input capacitance to the sampler circuit increases linearly the power
consumption consumed by the S&H and limits its speed operation.
The limits discussed above are such that with present technologies it is impracti-
cal to design an 8-bit full flash with conversion speeds higher than 2 GS/s or a 6-bit
flash operating at more than 8 GS/s.
1.2.1.2 SAR ADCs
The successive approximation algorithm performs the A/D conversion over multiple
clock periods by exploiting the knowledge of previously determined bits to find the
next significant bit. The method aims to reduce the circuit complexity and power
consumption using a serial approach and solving one bit per clock period.
For a given dynamic range 0 - VFS , where VFS is the full-scale voltage, the most
significant bit (MSB) distinguishes between input signals that are below or above the
limit VFS /2. Therefore, comparing the sampled input with VFS /2 obtains the first
bit as illustrated by the timing scheme of Fig. 1.2 (a). The knowledge of the MSB
restricts the search for the next bit to either the upper or the lower half of the 0 -
VFS interval. After this, a new threshold is chosen (either VFS /4 or 3VFS /4) and the
next bit can be estimated. The voltages used for the comparisons are generated by
a DAC under the control of a logic system known as the successive approximation
register (SAR) as shown in Fig. 1.2 (b).
Vin
VFS
111 +
VDAC -
VS&H 110
110 VDAC Σ
101
101
100
100 YES NO
011 >0
010
001
0
000
conf SAR reset
new
Sampling MSB Bit #2 LSB guess
(a) (b)
Fig. 1.2 Timing (a) and flow diagram (b) of the successive approximation technique.
47
Successive Approximation Converter (ii)

Vin VS&H
+ Clock
S&H
Vin VS&H . LOGIC S&H
VDAC S&HComp + (SAR)
- LOGIC
DAC
FS&H VDAC (SAR)
-
FDAC
φS&H bit-N-1
φDAC
bit-N-2
DAC
bit-0
DAC
OUT
Fig. 1.3 Basic block diagram of the SAR converter.
The method uses one clock period for the S&H and one clock period for the de-
termination of every bit thus requiring (n+1) clock intervals for an n-bit conversion.
Fig. 1.3 shows a typical block diagram of a SAR converter. The S&H samples the
input during the first clock period and holds it for N successive clock intervals. The
digital logic controls the DAC according to the successive approximation algorithm.
The SAR predicts the next bit, that is then either confirmed or not by the output of
the comparator. At the end of the N comparisons, the output is ready as a binary
code so no decoder is needed.
Fig. 1.4 shows the most common implementation of the successive approxima-
tion algorithm, the charge redistribution method. It uses an array of binary weighted
capacitances and just one comparator as an active element. The sampling phase, φS ,
pre-charges the entire array to the input signal by connecting the bottom plates of
the array to the input and the top plates to the analog ground. After sampling, the
SAR begins the conversion by first connecting the bottom plate of the largest capac-
itance (2n−1 CU ) to the reference voltage, Vre f , and the remaining part of the array to
ground. The superposition principle determines the voltage on the top plate, applied
to the comparator, to be equal to
Vre f
Vcomp (1) = − Vin (1.1)
2
Since this voltage is the difference between the MSB voltage and the input, it
is only necessary to compare it to ground. The comparator result determines the
MSB and enables the SAR to establish the conditions for the next bit calculation. If
the MSB is 1, the connection of (2n−1 CU ) to Vre f is confirmed and the capacitance
(2n−2 CU ) is tentatively connected to Vre f for the second comparison. Depending on
the value of the already determined MSB, the new top plate voltage becomes
3Vre f Vre f
Vcomp (2) = − Vin or Vcomp (2) = − Vin (1.2)
4 4
6 1 Introduction
Comp
φS
+
2n-1CU 2 iC U 2CU CU CU
- to the
φS φn-1 φn-1 φS φi φi φS φ2 φ2 φS φ1 φ1 φS φ1 SAR
Vin
from the
Vref
SAR
Fig. 1.4 Charge redistribution implementation.
for MSB = 1 or MSB = 0, respectively. This voltage is then used to determine the
next bit and the algorithm continues until all the n-bit are generated.
Variations of the scheme of Fig. 1.4 and different applications of the SAR con-
verter will be discussed in Section 1.4.
1.2.1.3 Pipeline ADCs
Pipeline ADCs, similar to pipeline logic blocks, achieve a high throughput by un-
winding over space what should be done over time by a sequential scheme. They use
several stages that process different inputs simultaneously, like in Fig. 1.5. While the
first stage is processing Vin (t), the second stage is processing Vin (t-1), the third stage
Vin (t-2), and so on. Each stage produces two outputs, the digital representation of
the input, Ni , and the residual voltage, Ri . The residual represents the difference be-
tween the input to the stage and the analog version of the output Ni (usually provided
by a DAC) amplified in order to match the next stage input range. It is usually gen-
erated and transferred to the next stage by means of an operational amplifier. The
amplification of the residual relaxes the accuracy requirements of the successive
stages. Ideally, if the input range of the all the stages is the same, the multiplying
factor for the residual voltage is 2ni , where ni is the number of bits solved in the
stage. The total resolution of the pipeline architecture is given by the sum of the bits
solved at each stage.
The generation of the residual voltage in modern technologies has become a
major issue, as low-voltage supply makes operational amplifiers an unsuitable solu-
tion. Another limiting factor is the poor improvement of the bandwidth of op-amp in
modern scaled technologies, if compared to the high-speed performances in digital
circuits. Several techniques have been proposed to overcome this problem. How-
ever, the delay introduced by the residue generator is usually the main limitation to
the speed operation of the converter.
clk clk clk clk

R1 R2 R3
Vin
STAGE 1 STAGE 2 STAGE 3 STAGE k
N1 N2 N3 Nk
clk DIGITAL LOGIC
OUT Nk … N3 N2 N1
Fig. 1.5 Basic block diagram of the pipeline converter.
A difference with other Nyquist rate converters, is the larger latency introduced
by pipeline ADCs. This might become a problem when using the converter in a
feedback loop.
1.2.2 Oversampled ADCs
The key advantage of oversampling is that the signal band occupies a small fraction
of the Nyquist interval making it possible to use digital cancellation on the relatively
large fraction of the quantisation noise that is outside the band of interest. The result
is a lower quantisation noise power in the band of interest and a higher equivalent
number of bits. The use of an ideal digital filter after the A/D conversion removes
the noise from fB to f s /2 and significantly reduces the quantisation noise power by a
factor of f s /(2fB ), leading to
2
Vre
∆2 2 fB f 2 fB
2
Vn,B = · = 2n
· (1.3)
12 f s 12 · 2 fs
where Vre f is the reference voltage, ∆ is the LSB voltage and n is the number of
bits of the quantizer.
The definition of the effective number of bits (ENOB) shows that oversampling
by a factor OSR = f s /(2fB ) potentially improves the number of bits from n to
ENOB = n + 0.5 · log2 (OS R) (1.4)
where OSR is the oversampling ratio.

8 1 Introduction
1.2.2.1 Σ∆ ADCs
The sigma-delta (Σ∆) ADC is the converter of choice for modern voiceband, audio,
and high-resolution precision industrial measurement applications. A Σ∆ ADC con-
tains very simple analog electronics (a comparator, voltage reference, switches, and
one or more integrators and analog summing circuits), and quite complex digital
computational circuitry. This digital circuitry consists of a digital signal processor
(DSP) which acts as a filter (generally, but not invariably, a low pass filter).
If simply oversampling is used to improve resolution, an oversampling factor of
22N is required to obtain an N-bit increase in resolution. The Σ∆ converter does
not need such a high oversampling ratio because it not only limits the signal pass-
band, but also shapes the quantization noise so that most of it falls outside this
passband. Fig. 1.6 shows the noise shaping principle. An input signal with a band-
width equal to fB is oversampled by a noise-shaping A/D with sampling frequency
equal to fN = OSR · fB . The output of the A/D represents the quantised signal, with
a quantisation noise that has been noise-shaped. This noise is high-pass filtered, so
to move its spectral density to the upper part of the Nyquist range, i.e. out-of-band.
A digital filter then filters out the quantised signal in order to reject all the quantisa-
tion noise in the high-frequency zone. Finally, a decimator reduces the output data
rate to the one required by the Nyquist theorem, f’N .
Incorporating the quantizer in a feedback loop as shown in Fig. 1.7 gives rise to
the desired noise shaping. The scheme has a sampled data input that, after the pro-
cessing data block A(z), is converted into digital. For closing the loop it is necessary
to generate the analog representation of the converted signal by means of a DAC.
A second processing block, B(z), is used before the subtracting element. The linear
model of Fig. 1.7 (b) represents the quantization error with the additive noise Q
that is a second input to the circuit.
The goal of the system is to have different transfer functions for the input signal
X and the noise signal Q . These are namely Signal Transfer Function (STF) and
Noise Transfer Function (NTF). By inspection of the scheme it results
2fN 2fN 2f’N

1 2 3 4
Oversampled Digital
Decimator
Sampled-data noise-shaping A/D Filter
n-bit n1-bit n1-bit
Analog
1 2 3 4
ΔfR
fB fN fB fN fB fN f’N
Fig. 1.6 Out-of-band noise rejection and decimation of a noise shaped signal.
εQ
X + Y YD X + Y
Σ A(z) ADC Encoder Σ A(z) Σ
- -
B(z) DAC B(z)
(a) (b)
Fig. 1.7 Incorporating the quantizer in a feedback loop obtains noise shaping.
[X − Y · B(z)] A(z) + Q = Y (1.5)
whose solution yields

X · A(z) Q
Y= + (1.6)
1 + A(z)B(z) 1 + A(z)B(z)
The idea is to provide a low-pass filter function to STF and a high-pass filter
function to NTF, in order to ensure the required noise-shaping. Often, the processing
block B(z) is not used (B(z) = 1), and A(z) is an integrator. This solution is called a
first order Σ∆ modulator.
The input of the modulator can be already in the discrete-time or a S&H is neces-
sary for the data conversion. The former case is called a sampled-data Σ∆, the latter
case corresponds to a continuos-time Σ∆ modulator.
Fig. 1.8 shows the block diagram of a sampled-data Σ∆ that uses
z−1
A(z) = (1.7)
1 − z−1
leading to
Y(z) = X(z) z−1 + Q (z) (1 − z−1 ) (1.8)
The effect of the modulator is to introduce a simple delay to the input signal, while it
can be proven that the noise signal is high-pass filtered. Besides, in [1] the maximum
SNR of the first order Σ∆ modulator, in the case of an ideal filter that removes the
out-of-band noise, is given and it is
S NRΣ∆,1|dB = 6.02n0 + 1.78 − 5.17 + 9.03log2 (OS R) (1.9)
where n’ = log2 k, and k is the number of thresholds used in the quantiser. This leads
to an effective number of bits equal to
ENOB = n0 − 0.86 + 1.5log2 (OS R) (1.10)
where the first term accounts for the SNR improvement due to a multi-level quan-
tiser, and the second term is a fixed cost required to secure an improvement of
10 1 Introduction
Analog Digital
Input Output εQ
X + YD X + Y YD
z-1 n-bit z-1
Σ ADC Σ Σ Encoder
- 1-z-1 - 1-z-1
Y Quantised
n-bit Output
DAC
(a) (b)
Fig. 1.8 (a) Sampled-data first order sigma delta modulator and (b) its linear model.
1.5 bits every doubling of the sampling frequency. If compared to (1.4), for every
doubling of the OSR one extra bit is gained. More complex architectures implement
higher order modulators and achieve better enhancement in the SNR. The reader
can refer to [1, 2] for a deeper insight on the Σ∆ modulator.
Notice that the noise shaping function implemented by the Σ∆ modulator does
not get rid of the quantisation noise, but it only moves its spectral density to the
high frequency part of the Nyquist range. Actually, the effect of the noise shaping
results in a global amplification of the quantisation error power by 2. A digital fil-
ter does need to filter out the high-frequency noise produced by the modulator in
order to achieve the required A/D conversion. In this case, a large OSR relaxes the
filter requirements as it distances the bandwidth from the high-frequency part of the
Nyquist range.
Another remark concerns the linearity and noise specifications of the ADC and
the DAC. The digital signal generated by the ADC is such that any limit affecting it
is relaxed by the feedback loop gain. Indeed, the ADC error must be referred to the
input of the modulator by dividing it by the transfer function of the integrator. Since
at low frequency (which is the region of interest) the integrator has a very large gain,
the error is greatly attenuated in the signal band. The same benefit does not apply to
the DAC as its error is injected directly at the input of the modulator together with
the input.
The benefits provided by oversampling and noise shaping enable the use of a
small number of quantisation levels. However, the noise shaping technique is based
on the white nature of the quantisation noise. This condition applies under a given
set of circumstances:
1. all the quantisation levels are exercised with equal probability;
2. a large number of quantisation levels are used;
3. the quantisation steps are uniform;
4. the quantisation error is not correlated with the input.
Thus, the use of a small number of quantisation levels does not comply with
the conditions necessary for considering Q as white noise. If the signal contains a
dominant DC component, the quantisation noise becomes a repetitive pattern that
produces spectrum tones, and also the 4th condition mentioned above is not longer
observed. A possible solution to this problem, apart from using multi-bit quantisers,
is to implement the dithering technique. Basically, an auxiliary input that eliminates

the correlation between Q and the signal is added. Obviously, the dither must be
effective against the tones and should not alter the signal. For this there are two
possibilities: the first is to inject a sine wave whose frequency is out of the signal
band. The digital filter used to cancel the out-of-band noise then removes the effect
of the dither. The second method utilises a noise-like signal whose contribution does
not degrade the SNR, which can either be thermal noise of the electronics in role or
an external random signal.
It is important to notice that, even with dithering, Σ∆ ADCs cannot provide a de-
terministic measurement of a DC signal, as some information of the past signals will
always be present at the output of the decimator due to the nature of the converter.
1.2.2.2 Incremental ADCs
Instrumentation and measurement applications, such as the readout of bridge trans-

ducers, battery monitoring and biomedical acquisition systems require monotonic
analog-to-digital converters with high resolution, good linearity, low offset and, typ-
ically, low power. Incremental converters, directly derived from Σ∆ schemes, are
particularly suitable for those needs. Although they share the same structure as a
Σ∆ ADC, in an incremental ADC the integrators are reset at the start of each con-
version.
As a result, only the samples of the used set determine the output and no in-
formation about previous samples is used, and so there is no need to describe the
quantisation error as noise and even to talk about noise shaping. Thus an incremental
ADC does not suffer from the limitations of small number of quantisation levels and
does not need dithering to operate with DC input signals. Instead, the input should
be constant or change slowly during the entire conversion, otherwise the digital re-
sult becomes a weighed average of the analog input, in a manner similar to that of a
FIR filter.
The equivalent number of bits of an incremental converter depends on the order
of the scheme, the number of clock cycles per sample, the resolution of the quantiser
and the digital post processing. Generally, to obtain a given resolution, higher order
modulators are more efficient since the required number of clock periods is reduced.
However, when the order of the scheme is higher than two, stability requirements
can limit the effectiveness of the architecture.
Fig. 1.9 shows the block diagram of a first-order incremental ADC. It consists
of a delayed-integrator, a comparator and a 2-level DAC. The operation principle is
as follows: when a new conversion cycle starts, the output of the integrator, Vres , is
reset. Since the frequency of the input signal of incremental ADCs is usually low,
Vin can be regarded as a constant signal. In each clock period, Vin subtracts Vout (the
analog version of Dout ) and the difference is accumulated by the delayed integrator.
At the end of N clock cycles, the residue voltage at the output of the integrator is
given by
12 1 Introduction
N−1
X N−1
X
Vres = Vin (i) − Dout (i)Vre f (1.11)
i=1 i=1
Due to the stability of the feedback loop, the voltage of Vres is limited, namely
−Vre f < Vres < Vre f , where ±Vre f are the reference voltages. The input signal Vin
can be, hence, represented as
PN−1
Dout (i)Vre f
i=1 Vres
Vin = + (1.12)
N −1 N −1
and the resolution of a first-order incremental ADC can be expressed as
R1−ord = log2 (N − 1) (1.13)

Unfortunately, the conversion efficiency of a first-order incremental ADC is low.
Methods for increasing the resolution are by increasing the number of clock periods
RESET
Vin Z-1 Vres Dout


1 ̶ Z-1
Vout
DAC
Fig. 1.9 First-order incremental ADC block diagram.
f1
f2
RESET RESET
Vin Z-1 Z-1 Vres Dout

c1  c2 
1̶Z -1
1 ̶ Z-1
c1
Vout
DAC
Fig. 1.10 Second-order incremental ADC block diagram.

1.3 Data Converter Evolution 13
N and using more effective schemes with cascaded integrators. High-order incre-
mental ADCs, therefore, contain multiple integrators with reset at the beginning of
the conversion cycle. The key points are to increase the accumulation efficiency,
while maintaining the stability of the structure and keeping Vres (N) minimized.
A conventional second-order incremental ADC is discussed here to illustrate how
the conversion efficiency changes compared with the first-order architecture. As
seen in Fig. 1.10, this structure contains two integrators with delay. In the signal
path there are two coefficients c1 and c2 . In order to keep the loop stable, two feed-
forward paths are included with coefficients f1 and f2 . This scheme also employs a
comparator and a 2-level DAC. Using the same mathematical approach employed
for the first order scheme, Vres (N) for this second-order structure can be expressed
as
N−1
XX i−1 N−1
XX i−1
Vres (N) = c1 c2 Vin (i) − c1 c2 Dout ( j)Vre f (1.14)
i=1 j=1 i=1 j=1
Similarly, the resolution of the second-order structure is described as

c1 c2 (N − 1)(N − 2)
R2−ord = log2 (1.15)
2!
To compare the conversion efficiency of first-order and second-order incremental
ADCs, parameters N = 1024, c1,2 = 1, f1 = 1 and f2 = 2 are chosen. According to
(1.13) and (1.15), the first-order scheme can provide 10-bit resolution while the
second-order structure achieves 19 bit. [4]
1.3 Data Converter Evolution
Once upon a time the area of application for different converter types was a well
defined space in the speed/resolution graph as shown in Fig. 1.11 in [5]. The de-
signer’s architectural choice was a simple trade-off between some factors such as
latency, speed, accuracy and area that could all be summarised in a table like in Ta-
ble 1.1. In this particular classification, SAR ADCs were an effective solution for
medium-high resolution converters working at low-medium conversion rate and oc-
cupy the centre of the speed/resolution space. Pipeline ADCs could improve both
resolution and speed, if compared to SAR ADCs, at the cost of extra power and area
consumption and longer latencies. For very high-speed operations folding ADCs
and flash ADCs were the only choice, but the achieved resolution was not too high.
Finally, Σ∆ ADCs occupy the high-resolution low-speed application area.
However, as stated in [6], an interesting consequence of the relentless optimi-
sation and improvements seen [. . . ] is the increasing competition among ADC ar-
chitectures. [. . . ] Today’s ADC designer is confronted with an overlapping design
space offering multiple solutions that are difficult to differentiate in their suitability.
As ADCs can consume a large percentage of power in a receiver, it is of vital
interest to minimize ADC power consumption. Over the years several architectures
have been developed which achieve optimal power consumption for different
sampling rates, and resolutions as shown in Fig. 2.8.
The ADC topologies of Flash, SAR, and Pipelined are reviewed in subsequent
sections as they are essential to understand within the context of this book.
A14detailed discussion of topologies not discussed in this book (Delta Sigma, and
1 Introduction
16–bit
Delta–Sigma
14–bit
ADC
12–bit
Pipeline
SAR ADC
10–bit
ADC
Folding+
resolution
8–bit Interpolating
ADC
6–bit
4–bit
Flash
ADC
2–bit
10k 100k 1M 10M 100M 1G 10G

Sampling rate (samples/second)
Fig.2.8
Fig. 1.11ADC
ADC architecturecomparison
architecture comparison, [5].
Table 1.1 Comparison of ADC architectures, [5].

Architecture Latency Speed Accuracy Area
Flash Low High Low High
SAR Low Low-medium Medium-high Low
Folding + interpolating Low Medium-high Medium High
Delta-sigma High Low High Medium
Pipeline High Medium-high Medium-high Medium
The technological evolution, along with the research activity, is the driven factor
for this new trend. As new technologies improve the switching speed of modern
transistors, the same is not true for their intrinsic gain. This trend favours more
digital based architectures over analog solutions, and requires op-amp free analog-
to-digital converters. As a result, SAR ADCs have played a significant role in ad-
vancing the state of the art over the past years and have been a versatile solution for
ultra low-power to ultra high-speed applications, [7–11].
The impressive scaling adaptability of SAR ADC has pushed its limits outside the
low-power, medium-resolution and medium-speed space, becoming a competitive
solution in applications previously dominated by other architectures. This is the case
for pipeline ADCs and high-speed medium-resolution applications. The research in
pipeline ADCs has focused in new techniques for op-amp-less residue amplification
and a push for low stage count [12], leading to significant reductions in power and
complexity. Passive residue transfer techniques [13] are an interesting idea, but the
1.4 The State of the Art in SAR ADCs 15
advantage of the interstage gain that relaxes the accuracy of successive stages is lost.
Other techniques, like the zero-crossing [14], pulse bucket brigade [15], and ring
amplifiers [16] and fully-dynamic amplification [17] are power efficient alternatives
to op-amps in generating residue. Pipeline ADCs remain the only topology that can
meet the stringent application requirements in high-speed conversion for wireless
infrastructures,reaching astonishing performances like the ones in [18].
For ultra high-resolution oversampling and noise shaping remain the way to
go. The CMOS technology shrinking has enabled larger bandwidth in oversam-
pled ADCs, extending its operating bandwidth up to a few hundreds of MHz with
sampling frequencies as large as 6 GS/s, as proven by [19–22].
Flash ADCs maintain their application target of high-speed low-resolution ap-
plications. As stated in [23], flash ADCs have regained some interest due to the
imminent shift from 2-level to 4-level pulse-amplitude modulation (PAM) signaling
in high-speed data links. The state of the art for flash ADCs exceeds the 1 GS/s
sampling rate, [24, 25].
In order to boost the performances of data converters, two main approaches have
been used: hybrid architectures and time-interleaving solutions. The former aims
to merge different architectures in order to take advantage of main benefits from
each topology. Most common results are flash-SAR Subranging ADCs, [26], SAR-
assisted pipelined ADCs, [27], and extended-range ADCs, [28, 29]. The possible
alternatives in merging different architectures are countless and can involve all dif-
ferent approaches. Anyhow, SAR ADC, because of its simple structure, is the most
suitable topology for such structures. A flash-SAR Subranging ADC is presented in
Chapter 2.
Time-interleaved (TI) architectures increase the conversion rate of a data con-
verter by using a number of converters working in parallel for a simultaneous quan-
tisation of input samples. A suitable combination of the results makes the operation
equivalent to a single converter whose speed has been increased by a factor equal to
the number of parallel elements. Again, SAR ADC appears to be the most suitable
architecture for time-interleaving techniques, as it can reach medium resolution and
speed with low power and low area consumption. Some remarkable results have
been achieved with TI-SAR architectures, like the ones in [30–32]. However, also
other converters lend themselves to time-interleaved solutions, like pipeline ADCs
in [33, 34], or flash ADCs in [35, 36]. A TI-extended-range ADC is presented in
Chapter 3.
1.4 The State of the Art in SAR ADCs
The basic block diagram of the SAR ADC is descrbed in Fig. 1.2. The main blocks
are the S&H, the comparator, the DAC and the SAR logic. This architecture has
been known for decades, [37, 38], but interest in such topology only increased in
recent years. As a result, countless innovative techniques and approaches have been
presented to push the limits of SAR ADCs from the standard low-power medium
16 1 Introduction
resolution and speed operation. To list all of them would be an impossible work,
and it is outside of the intent of this thesis. Instead, some of the most recent and
renowned ideas will be present here, in order to give the lecturer a rough under-
standing on the state-of-the-art on SAR ADCs research activity.
The main limitation on the charge redistribution method proposed by McCreary
and Gray, [37, 38], is the way the DAC is implemented. The capacitive array area
doubles for every extra bit of resolution, limiting the maximum achievable band-
width and increasing the power consumption. To overcome this problem, several
techniques in reducing the capacitive array have been presented, like the C-2C
structure, [39, 40], the split-DAC array, [41, 42], or the resistive-capacitive hybrid
DAC, [43, 44]. All these solutions aim to reduce the array area to the minimum re-
quired by the kT/C noise, independently from the resolution of the ADC. A smaller
array reduces the total capacitance to be switched at each step of the searching al-
gorithm, reducing both the power consumption and the DAC settling time. Moving
the DAC structure from plain-binary to more complex topologies often degrades the
overall linearity of the ADC. The solution in [10] provides a compact and linear
solution for DACs operating at high-speed. Another solution, for reducing the area
of the array in SAR ADCs operating at medium speeds, is to apply noise-shaping to
the DAC in order to improve its resolution, [45].
Another key factor, apart from the DAC structure, is the switching algorithm
that performs the successive approximation. In fact, the standard binary approach
is not very efficient and consumes most of the power in the very first steps. The
solution in [46] improves the efficiency of the switching activity by solving the LSB
first, while the Set-and-Down technique samples the voltages directly onto the top
plates of the DAC performing the first comparison without switching capacitors,
saving time and energy, [47]. Redundant switching sequences are an efficient way
of relaxing the settling constraints of the DAC, [48, 49]. The time saved by relaxing
the DAC settling is generally much larger than the extra cycles needed to resolve all
bits. Some designs use multi-bit per cycle architectures to speed up the searching
algorithm in high-speed applications, [50–52].
Asynchronous clocking, [11, 53, 54], has often been used in recent designs to
shorten the overall conversion time by removing waiting times during SAR oper-
ation. In addition, only one external clock pulse of nominally 12.5% duty cycle is
required to define the sampling window and start the conversion, thus saving power
in the clock distribution.
Recently, more system-oriented designs are being presented, [55]. This is the
case of the study in [56] that uses a loop-embedded input source follower for shield-
ing the large sampling capacitor from the input, making it easier to drive the ADC
linearly up to Nyquist.
Fig. 1.12 shows the achieved Walden figure of merit2 at Nyquist (FoMW,h f ) as
a function of the conversion rate (f snyq ) for ADCs presented in the IEEE Interna-
tional Solid-State Circuits Conference (ISSCC) from 1997 to 2016 (data extrapo-
lated from [58]). SAR and TI-SAR ADCs have been highlighted to better under-
2 The Walden figure of merit is defined as FoMW,h f = P

2ENOB 2 fB
in [57]
1.4 The State of the Art in SAR ADCs 17
1,E+05
SAR ADCs
TI-SAR ADCs
Envelope
1,E+04 ISSCC 1997-2016
FOMW,hf [fJ/conv-step]
1,E+03
1,E+02
1,E+01
1,E+00
1,E+04 1,E+05 1,E+06 1,E+07 1,E+08 1,E+09 1,E+10 1,E+11 1,E+12
fsnyq [Hz]
Fig. 1.12 Walden figure of merit at Nyquist (FoMW,h f ) as a function of the conversion rate (f snyq )
for ADCs presented in the IEEE International Solid-State Circuits Conference (ISSCC) from 1997
to 2016. Data extrapolated from [58].
stand the impact of this architecture in the present state-of-the-art. The resulting
graph shows how successive approximation data converters are the most efficient so-
lution for low-speed applications from tens of kHz up to tens of MHz, [7, 59]. They
are also a very suitable topology for ultra high-speed operation in time-interleaved
ADCs, [30,31]. Even, the cutting edge solution in [60] achieving a figure of merit of
2.6 fJ/conversion-step with a sampling frequency equal to 100 MS/s takes advantage
of the SAR algorithm to implement an hybrid architecture.
18 1 Introduction
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24 1 Introduction
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Chapter 2
An 8-b 700 MS/s Flash-SAR ADC with
86.7 fJ/conversion-step in 65-nm CMOS
Abstract This project, in collaboration with the State Key Laboratory of Analog and
Mixed-Signal VLSI at the University of Macau, foresees the design of a high-speed
medium-resolution ADC. In order to achieve higher bandwidth, a 3 stage multi-bit
per cycle structure was implemented. The studied solution uses a searching algo-
rithm that allows for relaxed accuracy requirements in the early stages of conversion,
and a preamplifier with embedded threshold generation for the multi-bit per cycle
architecture. The achieved measured conversion rate is 700 MS/s, with an ENOB as
high as 7.4 bits and 5.96 mW of power consumption with a nominal supply voltage
of 1.2 V. The measured Walden figure of merit at Nyquist is 86.7 fJ/conversion-step.
The ADC was fabricated in a 65-nm CMOS process and the active area of the chip
is 150 x 220 µm2
2.1 Introduction
The telecommunication industry has experienced a rapid growth in the last few
decades. The wireless mobile communication standards are the major contributors.
This growth has seen many generations from 1G, 2G, 3G, 4G, and even 5G. Each of
these generations drives continuous improvement of wireless technologies, higher
data rates, larger capacities and richer features compare to the previous ones. How-
ever, the capacity requirements and spectrum shortage are increasingly prominent,
with the explosive growth of mobile traffic demand. Thus, the bottleneck of wire-
less bandwidth becomes a key problem of the future wireless mobile communication
networks.
While 5G is still in the process of standardization, the industry agrees that access
to new, high-band spectrum, as well as millimeter wave (mm-Wave) beamforming
and steering, will be fundamental aspects of ultra-dense, high-capacity, low-latency
next-generation network. A new 5G mobile network is expected to operate in a
range of frequency bands between 6 and 100 GHz, including mm-Wave frequen-
cies, which enables very high (up to 10 Gbps) data rates, and in some scenarios, also
25
26 2 An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in 65-nm CMOS
very low end-to-end latencies (less than 5 ms). Therefore, the 5G mobile broadband
system [1] can provide multi-gigabit communication services such as high defini-
tion television (HDTV) and ultra-high definition video (UHDV). Broadband wire-
less standards, i.e., IEEE 802.11ad, or WiGig, using RF frequencies around 60 GHz
require low-to-medium resolution analog-to-digital converters (ADCs) with a sam-
pling rate in the GS/s range.
Ultra high-speed data converters operating at tens of GS/s use time-interleaved
structures for pushing forward the single channel bandwidth limits, [2], [3]. Flash ar-
chitectures for the core ADCs are an unsuitable solution for resolutions above 6 bits.
Instead, the SAR architecture is a convenient choice because of its simple structure
and low power consumption. Moreover, modern technologies allow relatively high
conversion rates.
The speed of an N-channel time-interleaved structure is N times the conversion-
rate of a single channel. A possible strategy is to choose a large interleaving factor.
However, integrating many channels turns problematic the clock distribution with
unavoidable clock skew that limits the resolution and generates spurious tones. The
clock skew causes a non-periodic input sampling and, in order to compensate for the
resulting errors, complex calibration methods must be used, [4]. A more effective
strategy implies the choice of relatively low values of N and pushes the conversion
rate of the single channel to the upper limit allowed by the technology. With 28-nm
and 32-nm CMOS technologies, it is possible to exceed 0.7 GS/s, [9, 10]. The use
of less advanced technology, like the 65-nm CMOS, enables lower conversion rates
(400 MS/s with a two bit/step SAR architecture [11]).
This 65-nm ADC uses a flash-SAR architecture achieving a conversion speed of
700 MS/s with a peak signal to noise and distortion ratio (SNDR) of 47.5 dB. The
result, comparable with the one obtained with smaller line-widths, benefits from an
architecture composed by the cascade of a 4-bit flash and a two-step SAR converter.
Both steps determine 3-bit. The 4+3+3 bits produce the 8-bit output; the applied
redundancy avoids calibration in the flash and in the first step of the SAR. The
active area of the chip is 150 x 220 µm2 and the measured total power consumption
is 5.96 mW.
2.2 Architecture
The converter is composed by the cascade of a 4-bit flash and a two-step SAR con-
verter. Both steps of the SAR determine 3-bit. The 4+3+3 bits produce the 8-bit out-
put. The conversion steps are called coarse, intermediate and fine stages; the applied
redundancy avoids calibration in the flash and in the first step of the SAR. A special
preamplifier generates the thresholds required for the SAR ADC to implement the
multi-bit per cycle conversion.
The coarse stage uses 14 comparators. The thresholds are nominally set at volt-
ages corresponding to the bins (24 + n · 16), with n = 0, · · · , 13. A thermometric
zero at the output identifies the bin interval 0, · · · , 32, the thermometric one iden-
2.2 Architecture 27
tifies 16, · · · , 48 and so forth, as Fig. 2.1 shows. The comparator accuracy must be
±8 LSBs, i.e. ±37.5 mV for 1.2-V pp reference voltage. The margin is large enough
for a properly designed comparator and reasonable clock skew. Therefore, the stage
does not need calibration.
The intermediate stage explores the interval chosen by the coarse conversion,
using 6 thresholds placed at ±10, ±6 and ±2 LSBs from the central point, as Fig. 2.1
shows. The used redundancy allows a ± 2 LSB accuracy. A thermometric code gives
the next interval to explore. Finally, the fine stage uses 7 thresholds placed at ±3, ±2,
±1 and 0 LSBs and requires a full accuracy of ±0.5 LSBs. A logic block combines
the outputs from all the three stages and generates the 8-bit word.
Since the full scale voltage is 1.2 V pp and, consequently, the LSB is about
4.7 mV, a careful design and layout require a foreground calibration only for the
thresholds used in the fine stage.
Fig. 2.2 illustrates the block diagram of the architecture. A fully differential ca-
pacitive array and a single ended flash simultaneously perform the input sampling.
The coarse conversion is carried out by the flash, whose output set the MSBs of the
capacitive array. The generated residual is the input of a special preamplifier that
provides 8+8 differential outputs. Half of these are the input of six fully differential
latches whose outputs determine the three Intermediate Significant Bits (ISBs) of
the first SAR cycle. The ISBs set the LSBs section of the capacitive array. The new
generated residual is fed into the preamplifier and, by using the other outputs, the
remaining 3 bits are obtained.
The capacitive array has two sections, one formed by 14 capacitors of value 4CU ,
the other formed by 8 capacitors of value CU for a total array of 64CU . The structure
implements a 5-bit DAC suitable for the flash and for the first SAR cycle steps.
Since the second SAR cycle determines three bits without using the array, the used
approach reduces the capacitive array from 256CU to 64CU (−75%). The nominal
value of CU to satisfy the kT/C noise requirement is 9 fF (CT OT = 576 fF).
Fig. 2.2 also shows the timing of each stage for a complete conversion cycle. Af-
ter sampling, the flash section carries out the first conversion step. Two subsequent
phases (DAC+SAR) complete the remaining conversion steps. Finally, one time slot
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256
COARSE
STAGE 8
8
8
8
14 Latches
accuracy
±8 LSB
-16 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 16
INTERMEDIATE
STAGE 2
2
2
2
6 Latches
accuracy
conventional
±2 LSB threshold
-4 -3 -2 -1 0 1 2 3 4 actual
FINE
threshold
STAGE 0.5 0.5
7 Latches 0.5 0.5 next
accuracy interval
±0.5 LSB
Fig. 2.1 Searching algorithm with redundancy.

SETTING MSBs SETTING ISBs

S S S S S S
in
VR
0
8 outputs ISB
S 4CU 4CU 4CU CU CU CU Latches
pre OUT
VCM
amp
LOGIC
4CU 4CU 4CU CU CU CU LSB
8 outputs Latches
0
VR From Flash
in
S S S S S S
SETTING MSBs SETTING ISBs
in Flash
S TIMING
CF
SAMPLING FLASH DAC1 SAR1 DAC2 SAR2 OUT
VR
3R 2R 2R 2R 3R
Fig. 2.2 Architecture of the proposed Flash-SAR ADC.
is allocated for the data out. In order to generate all the required phases, the con-
verter needs an input clock and an internal phases generator with frequency twice
the sampling frequency.
2.3 Circuit Blocks Design
In this section, the circuital design of the main blocks of the converter is described.
They are the the digital logic, the bootstrap circuit, the flash ADC, the comparator
and the preamplifier.
2.3.1 Digital Logic
The digital logic provides the phases needed for the converter and the switch driving
registers that control the DAC accordingly to the converter stages output.
Thanks to the reduced number of steps of the ADC, granted by the multi-bit per
cycle approach, a shift register free timing logic can be implemented. The circuit
is based on a frequency divider, as Fig. 2.3 shows. An external clock, CLK EXT,
at twice the sampling frequency is divided into two clock signals running at the
sampling frequency and shifted by 90◦ . A combinatory circuit provides all the
phases required for the converter to work properly, while internal feedbacks en-
sure non-overlapping conditions in the generation of the signals. An external signal,
RES EXT, can reset the timing logic.
2.3 Circuit Blocks Design 29
CLK_2 CLK_2
@ 90° @ 0°
Q D Q D
level level Q D RES_EXT
sensitive sensitive level
latch latch sensitive
Q Q latch
CLK_EXT
{ clock_s1
{
{ clock_s2
{
{ smp_in {
smp_ref
{ clock_fl
{
{ EOC
{
Fig. 2.3 Divider-assisted timing logic.
Apart from the sampling signals, smp in and smp ref, which sample both the
input and the reference for the flash ADC, three clock signals are required for start
each step of the converter. These are clock fl, clock s1 and clock s2. Finally, an
end of conversion signal concludes the conversion cycle, i.e. EOC. Fig. 2.4 shows
the timing diagram of the clock phases.
The switch driving registers introduce a delay in the feedback path of the SAR
converter that is added to the DAC settling time. For this reason, it is required to
keep this delay as small as possible. The implemented logic, in Fig. 2.5 and Fig. 2.6,
introduces a 3-gate delay from when the output of the comparator is ready to when
the actual switch at the bottom plate of the DAC is driven.
In the flash section in Fig. 2.5, the clock signal smp in first sets the outputs such
that the switches at the bottom plates of the DAC are all open. In fact, FL p and FLn
drive the pMOS switches tight to the positive reference, while FL p and FLn drive
the NMOS switches tight to the negative reference. After the sampling, the logic is
ready to sample the output of the flash comparators OP and ON. Based on the latch
decision, either one side or the other is reset choosing which side of the DAC is set
to ’1’ and which is set to ’0’. There are 14 such structures connected between each
comparator of the flash ADC and each capacitor of the flash section in the capacitive
DAC.
TIMING DIAGRAM
CLK_EXT
CLK_2 @ 0°
CLK_2 @ 90°
smp_in
clock_fl
clock_s1
clock_s2
EOC
Fig. 2.4 Timing diagram of the phases generated by the logic of Fig.2.3.
smp_in ON OP smp_in
FLn FLp FLn FLp
Fig. 2.5 Switch driving registers for the flash section of the capacitive DAC.
clock_s1 clock_s1
smp_in smp_in
OP ON
ON OP
clock_fl
clock_s1 clock_s1
SARn SARp SARn SARp
Fig. 2.6 Switch driving registers for the SAR section of the capacitive DAC.
In a similar way, the SAR section is controlled by the circuit in Fig. 2.6. smp in
reset to an open condition the switch drivers. Next, the signal clock fl sets the pos-
itive DAC section to ’1’ and the negative one to ’0’ for the ’test’ step of the SAR
algorithm. Finally, the output of the SAR comparators OP and ON are read. The
nomenclature used is the same as the one used for the flash section. There are 6
such structures connected between each comparator of the first SAR step and each
capacitor of the SAR section in the capacitive DAC. The remaining two unit capac-
itances in the SAR section are connected one to the positive reference and the other
to the negativa one, following the searching algorithm requirements.
The digital logic is completed by a bank of registers that sample the output syn-
chronous to the rising edge of the end of conversion signal, and a decoder that pro-
vides a binary output to the logic analyzer during testing.
2.3.2 Bootstraped sampling switch
Sampling switches in ADCs introduce two main errors, due to charge injection and
non-linearities of the ON resistance of the switch. The first effect mainly results
from the generation and the dissolution of the conductive channel sitting under the
gate when the transistor is in the ON state. The channel charge in a MOS transistor
working in a triode region is equal to
∆Q = WLe f f COX (VGS − Vth ) (2.1)
where W and Le f f are the effective width and length of the transistor, COX is the
oxide capacitance per unit area, and (VGS - Vth ) is the overdrive voltage.
When the switch is turned off, the charge of the channel needs to disappear. The
only nodes where the charges can go are the two terminals of the switch itself. A
fraction of the total charge will affect one terminal, the remaining will influence the
other. The charge going to the sampling capacitance will generate a voltage offset
that depends on many factors: the technology, the sizing of transistors used, the
input voltage, and the clock timing. Most importantly, the offset is input dependant,
which leads to harmonic distortion in the sampling operation.
The second error derives from the dependance from the input signal of the ON
resistance of the switch. In fact, the ON resistance of a MOS switch is equal to
1
Ron = (2.2)
µ WL COX (VGS − Vth )
where µ is the mobility of the charges (either electrons or holes).

In both cases, the overdrive voltage (VGS - Vth ) is a function of the input signal,
being VS = VIN . Bootstrapping is a technique, which ideally removes the signal
dependency of both issues, by ensuring a constant overdrive voltage to the switch.
Fig. 2.7 describes the technique, which is divided into to phases. First, the boot-
strap capacitance CB is pre-charged to VDD and the sampling switch gate is tight
to ground. During the sampling phase, CB is connected between gate and source of
the switch, ensuring a constant overdrive voltage equal to (VDD - Vth ) that is inde-
pendent from the input signal. This ensures a constant ON resistance of the MOS
working in the triode region, and, if the conditions at the node VO does not change,
a constant charge injection of the switch when it opens. Besides, the nMOS sam-
PHASE 1
+
VDD CB
_
VO
VIN
PHASE 2
+
VDD CB
_
VO
VIN
Fig. 2.7 Description of the bootstrapping technique.
pling switch can close also for input signals that are larger than (VDD - Vth ) and no
pass-transistor logic is required.
The bootstrap clock is generated by the circuit in Fig. 2.8, using the structure
presented in [5]. During CLK, the capacitor CB is pre-charged to VDD by M1 and
M2 . M3 and M4 tight to ground the output clock CLKOUT and turn off M8 and M10 ,
while M5 turns off M7 . When CLK goes high, M6 turns on M7 which turns on M8 .
M8 , together with M9 , samples VIN at the bottom plate of CB . This boosts the top
plate of CB to VDD + VIN . M7 provides to the output CLKOUT this value attenuated
by the parasitic capacitance CP . The main contribution to this parasitic is the one of
the bulk parasitic of M7 . Therefore, there is a tradeoff between the effectiveness of
the bootstrap logic and the maximum sampling speed achievable by the circuit. M4
reduces the VDS and VGS applied to M3 during the CLK phase, while M10 ensures
that the VS G of M7 never exceeds VDD . M4 and M3 are made large enough not to
introduce excessive jitter noise in the falling edge of the sampling clock.
The bootstrapped clock is then distributed both to the flash ADC and the ca-
pacitive DAC in the SAR section. Since the flash ADC is single-ended, there is
imbalance between the logic that is connected to the positive and the negative polar-
ities of the input signal. Dummy switches are placed for the negative one, in order
to balance the load seen at CLKOUT and ensure symmetry.
CLK
M2
M7
M4 M3
CP
CB
M5
CLKOUT
CLK
M6 M10
M8
VIN
CLK M1 M9
CLK
Fig. 2.8 Schematic view of the bootstrap logic.
2.3.3 Flash ADC
The flash ADC implements the coarse conversion step in the search algorithm. Thus,
it is required to design a 14-threshold converter, with an accuracy for the thresholds
of ±8 LSBs. A careful design should not ask for calibration, as the resolution re-
quirements are relaxed by a digital correction technique.
The last stages of the converter are implemented by a SAR ADC, which has
a fully-differential rail-to-rail input range. If a similar structure is implemented in
the flash ADC, a fully differential comparator should be designed. This not only
complicates the circuit implementation, but it also increases the power consumption
of the converter. Instead, a single-ended rail-to-rail ADC is used and the input stage
of the comparators are either pMOS or nMOS accordingly to the common-mode
voltage that they are analyzing. This is possible, as the coarse stage does not need
to produce a residual voltage, but only a digital word for the MSBs to be used in
the next stages. Then, moving from a single ended output to a differential one only
requires a logic inverter.
The reduced mobility of holes makes pMOS input-stage comparators slower, re-
quiring larger transistors to meet the speed constraints of the converter. This trans-
lates into larger power consumption, compared to the nMOS counterpart. For this
reason, pMOS comparators are only used for the low input common-mode region.
The presented architecture uses only five pMOS comparators, and nine nMOS ones.
The thresholds are generated with a thermometric resistive ladder. Unsilicided n+
polysilicon resistors are used for achieving high matching accuracy in the resistive
VIN
nMOS
MSB14
nMOS
MSB6
pMOS
MSB5
pMOS
MSB1
clk_fl
Fig. 2.9 Flash converter architecture.
string, [6]. These resistors present a lower sheet resistance compared to the silicided
version. In this way, minimum width resistors can achieve the required unit value
for the resistive string, reducing the area occupied by the flash references. The final
string is composed by 16 unit resistors of 60 Ω.
The resulted architecture is the one in Fig. 2.9. The applied redundancy in the
searching algorithm allows using a very simple structure. Besides, the thermometric
DAC used in the cascaded SAR does not call for a decoder, so that the output of the
comparators are fed directly into the next stage.
Errors in the flash come from three main factors: relative offset between the com-
parators, mismatch errors in the threshold generation, and sampling switch charge
injection imbalance. While the first two can be overcome by a careful design, the
last one might not present a straightforward solution. In fact, in a single-ended so-
lution, the sampling switch is present only in one input of the comparator, while
the other one is directly connected to the resistive string, like in Fig. 2.10 (a) for
an pMOS case. This generates asymmetry in the clock feedthrough seen by the two
inputs of the comparators. The charge injection from the sampling switch gives rise
to a voltage drop at the input node, that can generate an error at the output code.
The error is not negligible as the sampling switches are relatively large, the sam-
pling clock (smp in) is bootstrapped and the sampling capacitance is kept as small
as possible. Normally, this error is treated as an offset of the converter as the charge
M0 latch smpin
ΔQ
Vref M1a M1b VIN
Csmp
Di- Di+ bootstrapped
(a)
smpref M0 latch smpin

ΔQ1 ΔQ2
Vref M1a M1b VIN
Cgd,a Cgd,b
Csmp Csmp
Di- Di+ bootstrapped
(b)
Fig. 2.10 Comparator input stage in flash ADC for pMOS part. (a) Standard approach. (b) Pro-
posed solution.
injection is similar in all the comparators, apart from the sampling switches random
mismatches. Anyway, in order to avoid calibration in the coarse stage, a solution
addressing this problem has been implemented. Symmetry in the proposed structure
was made possible by sampling also the reference voltage, as Fig. 2.10 (b) shows.
The idea is to equalize the charge injection from both sides in order to generate a
common-mode error that is rejected by the differential input pair of the compara-
tor. In order to do so, also the sampling clock for the reference (smp ref ) should
be bootstrapped. This would require a bootstrap circuit for each reference voltage,
which is not affordable due to area and power constraints. Instead, a different sizing
of the sampling switches is done in order to compensate for the overdrive voltage
mismatch.
The charge injection of an nMOS switch opening can be derived from (2.1). The
overdrive voltage in the input sampling switch is constant and, in first approxima-
tion, equal to VDD thanks to the bootstrap circuit, so also the charge injection is
constant and it does not depend from the input signal. Also the charge injection in
the reference sampling switch is constant, but in this case the overdrive voltage is
Di- Di+
smpin
ΔQ
Vref M1a M1b VIN
Csmp
M0 latch
bootstrapped
(a)
Di- Di+
smpref
smpin
Cgd,a Cgd,b
ΔQ1 ΔQ2
Vref M1a M1b VIN
Csmp Csmp
smpref M0 latch
bootstrapped
(b)
Fig. 2.11 Comparator input stage in flash ADC for nMOS part. (a) Standard approach. (b) Pro-
posed solution.
not equal to VDD . Thus, a fine-tuning of the sampling switches can equalize the
charge injection ∆Q1 and ∆Q2 in Fig. 2.10 (b).
In the upper part of the flash ADC, pMOS switches are required for sampling
the reference. Hence, the charge injection is different in polarity as the channel in
pMOS is formed by holes and not by electrons. In this case, pass-transistor gates
are used for equalizing the charge injection, Fig. 2.11. The pMOS switch is used to
properly sample the reference, while the nMOS switch provides the required ∆Q1
for the fine-tuning technique. It is known that this technique works correctly when
the input common mode voltage is around VDD /2, which is not the case here. Thanks
to the low accuracy requirements of the flash ADC, the technique is also effective at
higher common mode voltages.
2.3.4 Comparator with built-in preamplification
The delay of a comparator depends significantly of the differential input amplitude.

For this reason, it might seem beneficial to place a preamplifier driving the latch.
But, the delay introduced by the preamplifier needs to be accounted for, making
the actual benefit in speed negligible. Besides, a preamplifier would increase area
and power consumption of the comaparator. Instead, the idea is to incorporate the
amplification feature into the latch itself, [7].
A comparison of the input stage of a static preamp and the input of the sense
amplifier dynamic latch shows that the circuit are equal, Fig.2.12. The difference is
in the role of the transistor connected to the common sources. In one case it is a
current source, in the other is a switch. This suggest to merge the two functions to
obtain the circuits of Fig. 2.13. The dynamic latch integrates the preamplification
function into the latch itself. The circuit, in the latch phase, works in the same way
as the conventional sense amplifier latch. In the reset phase, the current IS S flows
into the input pair, while the regenerative loop transistors are diode connected by
the reset. The result is a static amplification of the input signal equal to the square
root of the aspect ratios of input transistors and diode connected load. The parasitic
capacitance at the output of the preamplifier is significantly reduced, compared to
the one seen by an extra preamplifier in front of the latch, because it is only due
to the one at nodes Di + and Di −. This increases the speed of the comparator with
respect to an equivalent latch with a preamplifier in front.
The solution was compared to a sense amplifier latch, [8], and the same sense
amplifier latch driven by a preamplifier. The tail current used for the preamplifier
and the proposed solution is the same. Figure 2.14 shows the results. An effective
advantage in terms of speed is achieved by the proposed solution. This is due to two
main reasons. First, the preamplifier is embedded into the latch and this does not
VDD VDD
REGENERATIVE LOAD
LOOP NETWORK
In M1a M1b Ip In M1a M1b Ip
M0 clock M0 VB
(a) (b)
Fig. 2.12 Comparison between input stages of dynamic latch and preamplifier. (a) M0 is a switch.
(b) M0 is a current generator.
VDD
VDD
ISS clock
clock Op clock
On
In Ip
Di- Di+
Di- Di+
In Ip
Op
On
ISS clock clock clock
(a) (b)
Fig. 2.13 Improved sense amplifier latch schematic. (a) nMOS input stage. (b) pMOS input stage.
26
This work
Sense Amplifier Latch
24 Sense Amplifier Latch with Preamp
22
Latch delay [ps]
20
18
16
14
12
10
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
Differential Input Voltage [mV]
Fig. 2.14 Simulated pre-layout time response versus differential input for this work, the SA latch
and the preamplified SA latch.
increase the parasitic capacitance that limits the dynamic gain. Second, the com-
parator starts the latch phase with its outputs already unbalanced like in the case of
a static class AB comparator.
2.3.5 Preamplifier with embedded thresholds generation
The small value of the quantization step in the two phases of the SAR conversion
does not provide a reliable operation for the latches, at the required bandwidth.
Therefore, a preamplifier is required for relaxing the offset specifications of the
comparator. Besides, the need of preamplification has been combined with the need
for generating the thresholds for the converter, reducing notably the power con-
sumption.
Fig. 2.15 describes the conceptual approach. It is a simple differential stage with
resistive load, a circuit solution that grants high speed. The resistive load on the right
branch is divided in two parts, so that equal voltages VA and VC require an input
shift, V sh , across the differential pair. Supposing that the shift causes a negligible
signal current, it is necessary to have
IB
2RT gm V sh ' RX
2
The preamplifier gain is
AP = 2gm RT
The required shift voltage depends on the design quantities W/L, IB , and RX /RT .
Suitable values of those parameters provide V sh = ±1, ±2, ±3, ±6, ±10 LSBs.
The accuracy of the shift depends on the accuracy and linearity of gm , as the
ratio among the resistors is well matched. For the first step of the SAR, the possible
error is compensated for by the redundancy. For the second step, the circuit uses
foreground calibration. The control of the bias current, IB , provides a rough global
calibration, before the fine calibration embedded in the latch. The nominal value of
IB is 500 µA, ensuring very low power operation of the preamplifier.
VDD
RT -RX
IB RT VC IB VA
2 2
RX
output
VA VB VC
Vi,N Vi,P Vsh VB
Vbias IB differential input
Fig. 2.15 Preamplifier with embedded thresholds generation.

First SAR Step Second SAR Step

VDD VDD
VNI-10 VPI-10 VPL-3 VNL-3
SAR1 SAR2 SAR1 SAR2 SAR1 SAR2

Vi,N Vi,P VCM VCM
VB
MAIN DUMMY
Fig. 2.16 Preamplifier schematic with dummy structure and double output branch.
Fig. 2.16 shows the schematic diagram of the multi-output preamplifier. It uses
a single differential pair that can be connected to two resistive string loads, one for
the first step of the SAR, the other for the second one. The values of the resistors
optimize the gain for the two cases. The use of the same differential pair ensures a
good matching of the operational conditions in the two modes. In order to prevent
output voltages switching when the resistive load is not used, a dummy differential
pair replaces the main structure in the disconnected resistive loads.
The output voltages drive the latches following the connection scheme shown in
Table 2.1. The latches used in the SAR section section are again the one presented
in Fig. 2.13(a).
Table 2.1 Latches bank connections to preamplifier outputs.

First SAR step Second SAR step
Vip Vin Vip Vin
latch latch
-10 LSB VPI−0 VNI−10 -3 LSB VPL−0 VNL−3
+2 LSB VPI−2 VNI−0 0 LSB VPL−0 VNL−0
+6 LSB VPI−6 VNI−0 +1 LSB VPL−1 VNL−0
+10 LSB VPI−10 VNI−0 +2 LSB VPL−2 VNL−0
+3 LSB VPL−3 VNL−0
2.3.6 Calibration system
The calibration system is embedded in the latches of the fine step, as shown in
Fig. 2.17. The solution uses an extra differential input pair, connected to an off-chip
differential signal, for forcing an offset to the comparator. A foreground calibration
of CALn and CAL p generates the required offset that compensates for the error in
the threshold generated by the preamplifier. The ratio between the input differential
pair and the auxiliary one is chosen to be 4 in order to guarantee enough trimming
range, without reducing the sensitivity of the comparator to the actual input signal.
VDD
clock Op clock
On
CALn In Ip CALp
ISS clock
Fig. 2.17 Calibration system embedded in the latch.

2.4 Measurement Results
This ADC has been fabricated in a 65-nm 1.2-V CMOS process. The design uses a
standard multi-chip module of 1000 x 1500 µm2 , but the active area of the converter
is 150 x 220 µm2 . Fig. 2.18 depicts the whole chip microphotograph and a magnified
view of the active area where the main circuit blocks have been highlighted. The
track & hold circuit is placed in the top part of the ADC. A tree structure brings the
sampling clock and the input signals to the flash ADC and to the capacitive DAC.
At the bottom, the preamplifier with the latches bank forms the comparators of the
SAR ADC. The logic is distributed along the chip and does not occupy a significant
amount of area. The output is decimated on chip by a factor 25, in order to relax the
measurement equipment operation speed.
T/H
FLASH ADC
CAPACITIVE
DAC
COMPARATORS
Fig. 2.18 Chip microphotograph.
CALIBRATION
NETWORK
DIGITAL
OUTPUT
BUFFER
CHIP
DIFFERENTIAL
INPUT
Fig. 2.19 Test board.

2.4 Measurement Results 43
Fig. 2.19 shows the test board used for measuring the ADC. The chip is directly
bonded to the board in order to reduce the parasitics for the high-speed traces, espe-
cially the one that brings the clock signal. The outputs of the converter are decimated
on-chip, and a buffer in the board connects them to the logic analyzer. The calibra-
tion network is generated on-board by a set of resistive dividers on the top side of
the board. The remaining input signals (voltage references and supply voltages) are
provided directly by the lab instrumentation.
Fig. 2.20 shows the SNDR measured with a full-scale sine wave input signal as
a function of the sampling frequency for different supply voltages. At the nominal
supply voltage (VDD = 1.2 V), the ENOB is 7.5 bits up to f s = 550 MS/s and slightly
drops at higher sampling frequencies. At f s = 700 MS/s, the ENOB is 7.4 bits. The
50
V D D = 1.2 V
V D D = 1.1 V
VDD = 1 V
Measured SNDR [dB]
45
40
35
30
100 200 300 400 500 600 700 800 9001000
Sampling Frequency [MS/s]
Fig. 2.20 Measured SNDR as a function of the sampling frequency for different supply voltages.
DNL Measurements from 16384 Data Points

1
DNL (LSB)
0.5
0
-0.5
-1
50 100 150 200 250
Digital Code
INL Measurements (Best End-Point Fit)
1
INL (LSB)
-1
50 100 150 200 250
Digital Code
Fig. 2.21 Measured DNL and INL.

figure shows that the circuit looses about 0.25 bit at lower supply voltages and shows
a lower speed of operation.
Fig. 2.21 shows the measured DNL ([-0.65 : +0.75] LSBs) and the best fit INL
([-0.79 : +0.94] LSBs). In order to account for possible non-linearities occurring at
high speed, the figures result from the histogram method with a sampling frequency
as high as f s = 700 MS/s.
Fig. 2.22 gives the measured output spectra for f s equal to 500 MS/s when the
input frequency is low (Fig. 2.22(a)) and when it is near Nyquist (Fig. 2.22(b)). The
achieved SNDRs are 47.3 dB and 45.2 dB while the ENOBs are 7.56 bits and 7.22
bits, respectively. Third harmonic tones at −57 dBFS and −52 dBFS limit the spuri-
ous free dynamic range (SFDR). The FFTs have 16384 points and the outputs were
decimated by 25x. Similar tests were performed for f s equal to 700 MS/s, Fig. 2.23.
The achieved SNDRs are 46.4 dB and 41.6 dB while the ENOBs are 7.42 bits and
0 0
SNDR = 47.3dB ENOB = 7.56 bits SNDR = 45.2dB ENOB = 7.22 bits
-10 f = 500 MS/s f = 22 MHz -10 f = 500 MS/s f in = 249 MHz
s in s
-20 -20
-30 -30
PSD [dB]
PSD [dB]
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Frequency [Hz] ×10 6 Frequency [Hz] ×10 6
(a) (b)
Fig. 2.22 Measured output spectrum at f s = 500 MS/s. (Output decimated by 25x). (a) Input signal
at 22 MHz. (b) Input signal at 249 MHz.
0 0
SNDR = 46.4dB ENOB = 7.42 bits SNDR = 41.6dB ENOB = 6.62 bits
-10 f = 700 MS/s f = 22 MHz -10 f = 700 MS/s f in = 349 MHz
s in s
-20 -20
-30 -30
PSD [dB]
PSD [dB]
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
Frequency [Hz] ×10 6 Frequency [Hz] ×10 6
(a) (b)
Fig. 2.23 Measured output spectrum at f s = 700 MS/s. (Output decimated by 25x).(a) Input signal
at 22 MHz. (b) Input signal at 349 MHz.
50
f s = 500 MS/s
f s = 700 MS/s
f s = 800 MS/s
Measured SNDR [dB]

45
40
35
30
10 20 30 40 50 60 70 80 90100 200 300 400
Input Frequency [MHz]
Fig. 2.24 Measured SNDR as a function of the input frequency for different sampling frequencies.
6.62 bits, respectively. Third harmonic tones at −56 dBFS and −47 dBFS limit the
spurious free dynamic range (SFDR).
Fig. 2.24 shows the measured SNDR at the nominal supply voltage as a function
of the input signal frequency for different sampling frequencies. The performances
drop significantly for f s = 800 MS/s for input frequencies higher than 200 MS/s.
The drop at near Nyquist frequencies is due to the jitter noise introduced by the
sampling network.
The total power consumption is 5.96 mW (VDD = 1.2 V). The figure of merit at
f s = 0.7 GS/s is 86.7 fJ/conversion-step. Fig. 2.25 shows the power breakdown of
Analog VDD
0.61 mW (10%)
SAR VREF Digital VDD
0.81 mW (14%) 3.43 mW (57%)
Flash VREF
0.99 mW (17%)
Common-mode VREF
0.12 mW (2%)
Fig. 2.25 Power breakdown of the ADC.

Table 2.2 Performance summary and comparison table.
[9] [10] [11] This Work

Technology 28 nm 32 nm 65 nm 65 nm
Resolution 8 bits
Supply Voltage 1V 1V 1.2 V 1.2 V
SNDR near Nyquist 43.3 dB 39.3 dB 44.5 dB 41.6 dB
Sampling Speed 0.75 GS/s 1.2 GS/s 0.4 GS/s 0.7 GS/s
Power 4.5 mW 3.06 mW 4 mW 5.96 mW
FoM/conv.-step 50 fJ 34 fJ 73 fJ 86.7 fJ
Area 0.004 mm2 0.0015 mm2 0.024 mm2 0.03 mm2
the ADC, identifying in the digital section and the latches as the power hungry part
of the circuit. Scaling down the technology to 32 nm would reduce by a factor 4 that
contribution, with a reduction of the consumed power by about 45%.
Table 2.2 summarises the ADC performance and provides a comparison with
state-of-the-art single channel SAR ADCs. This work results faster than latest single
channel ADCs presented in the same technology node with 8-bit resolution.
2.5 Conclusions
In this chapter, the prototype of a 700 MS/s single channel Flash-SAR ADC in
65-nm CMOS process was presented. A multi-bit per cycle search algorithm is used
in order to speed up the conversion. Redundancy and a novel resistive interpolated
preamplifier are implemented to overcome the thresholds generation limit and to
reduce the calibration procedure complexity. A novel latch structure that shows a
significant improvement in speed was presented. A simple, yet effective solution for
the flash ADC sampling network solves the asymmetry problems in single-ended
architectures. A divider-based phase generator gets rid of the conventional shift reg-
ister approach in the SAR ADC, and a dynamic logic minimizes the feedback loop
delay of the converter.
The main limitation for the achievable bandwidth of the ADC is the sampling
network, while the architecture proves its effectiveness even at higher speeds than
700 MS/s. A technology scaling would be beneficial, especially in the power con-
sumption reduction, as the major contribute to it comes from the digital logic blocks.
Measurement data show competitive results, especially if compared to same tech-
nology node ADCs. The achieved figure of merit at Nyquist is 86.7 fJ/conv-step with
a sampling rate equal to 700 MS/s. This results places itself close to the state-of-the-
art in the FoMW vs fS plot from Murmann’s dataset [12], shown in Fig. 2.26. For fair
2016 IEEE European Solid State Circuits Conference ESSCIRC 2016
September 12–15 | Lausanne, Switzerland
4. MEASUREMENT RESULTS
2.5 Conclusions Single-channel ADCs with ENOB 47>

1,E+05 5bit
FOMW,hf [fJ/conv-step] 1,E+04
1,E+03
65nm
1,E+02
28nm
32nm
1,E+01 ISSCC 1997-2016
40nm VLSI 1997-2016

This Work
1,E+00
1,E+04 1,E+05 1,E+06 1,E+07 1,E+08 1,E+09 1,E+10 1,E+11
fsnyq [Hz] 35
Fig. 2.26 Walden figure of merit at Nyquist (FoMW,h f ) as a function of the conversion rate (f snyq )
for single-channel ADCs with ENOB higher than 5 bits presented in the IEEE International Solid-
State Circuits Conference (ISSCC) from 1997 to 2016. Data extrapolated from [58].
comparison, only single-channel ADCs with ENOB higher than 5 bits are displayed
in the figure.
The description of this ADC appeared in the proceedings of the IEEE European
Solid State Circuits Conference (ESSCIRC) in September 2016, [13].
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International Solid State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 382-383, 2014.
4. P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex,

J. Sitch, S.-C. Wang, J. Wolczanski, “A 24GS/s 6b ADC in 90nm CMOS”, IEEE International
5. M. Dessouky and A. Kaiser, “Input Switch Configuration Suitable for Rail-to-Rail Operation
of Switched Op Amp Circuits,” Electronics Letters, vol. 35, no. 1, pp. 8-10, 1999.
6. M. J. Pelgrom, “Analog-to-Digital Conversion”, New York: Springer, 2013.
7. D.G. Muratore, A. Akdikmen, F. Maloberti, “Very High-Speed CMOS Comparators for Multi-
GS/s A/D Converters”, Proc. of the IEEE Conference on Ph.D. Research in Microelectronics
and Electronics (PRIME), pp. 240-243, 2015.
8. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A Current-Controlled Latch Sense

Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture”, IEEE J.
Solid-State Circuits Conf. Dig. Tech. Papers, vol.28, pp.523-527, Apr. 1993.
9. Y-C. Lien, “A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm
CMOS Technology”, IEEE Symposium on VLSI Circuits (VLSIC), pp. 88-89, 2012.

T. Meyer Andersen, Y. Leblebici,“A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR
References 49
ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS”, IEEE
11. H. Wei, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. Martins, F. Maloberti, “A 0.024mm2
8b 400MS/s SAR ADC with 2b/cycle and Resistive DAC in 65nm CMOS”, IEEE International
12. B. Murmann, “ADC Performance Survey 1997-2016”, [Online]. Available:

http://web.stanford.edu/ murmann/adcsurvey.html.
13. D.G. Muratore, A. Akdikmen, E. Bonizzoni, F. Maloberti, U-F. Chio, S.-W. Sin, R. P.
Martins, “An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology”,
Accepted at IEEE European Solid State Circuits Conference (ESSCIRC) Dig. Tech. Papers, 2016.
Chapter 3
A 14-b 33.6 V DR Extended Range ADC for
Battery Monitoring
Abstract This project was done in collaboration with AMS Italy and its goal was
to design an ADC for monitoring the voltages of a stack of 8 Li-Ion batteries. The
converted voltage range for each battery is 3 - 4.2 V, with a maximum nominal
input voltage of 33.6 V. High-voltage switches and a single high-voltage capacitor
make the high-voltage track & hold. The remaining part of the circuit operates at
a nominal 5-V supply. An interleaved extended-range ADC makes the architecture.
It converts the 8 channels in 720 µs. The battery monitor has been fabricated in a
0.35-µm triple-well 5V HV CMOS process with drain extended MOS high-voltage
devices. The prototype active area is 1300 x 650 µm2 and the measured total power
consumption is 3.64 mW. The measured input referred noise and residual offset are
177.9 µV and 642.5 µV, respectively.
3.1 Introduction
The management of Li-Ion batteries used in electric vehicles requires to measure

the voltage across each battery about every 1 ms with an accuracy of 1 mV or better.
Since the voltage of a Li-Ion cell can go up to 4.2 V, stacking several elements
requires complex high-voltage circuit solutions. This prototype monitors up to 8
batteries, with a relatively simple high-voltage section.
The circuit provides a digital conversion of each single cell voltage for a suitable
processing of the battery monitor. Existing solutions [1–3] employ level shifters and
high-voltage control logic for a sequential sampling of the inputs; then, a SAR or
a Σ∆ ADC estimates the outputs. Having multiple high voltage sections grows the
silicon area; moreover, sampling the inputs sequentially is not optimal since a com-
mon need is to provide the A/D result of (almost) simultaneous samples. The need
of “nearly simultaneous” conversion derives from the high dynamic load changes
seen by the batteries and from the necessity to measure all the cell voltages un-
der the same condition. The solution in [4] uses a parallel approach with multiple
level shifters and multiple ADCs. Although this provides a simultaneous conversion,
51
52 3 A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring
HIGH-VOLTAGE LOW-VOLTAGE
DOMAIN DOMAIN
+
HV
TRACK 8-CHANNEL TI SINGLE
INCREMENTAL DECODER DOUT
+ & SAR ADC
HOLD ADC
BATTERY
STACK
LOGIC
64x8 cycles 64x8 cycles

incremental incremental
TIMING
8 SAR 8 SAR
cycles cycles
Fig. 3.1 Battery monitor architecture.
inter-channel mismatch becomes a major limitation to the achievable resolution in

this kind of architectures.
This design employs the time-interleaving (TI) of 8 extended range ADCs, [5,6],
made by a 6-bit first order incremental converter and an 8-bit SAR. The track & hold
uses only one high-voltage capacitor and 8 high-voltage switches to sample the in-
put, as shown in Fig. 3.1. The architecture shares the comparator used in the incre-
Discharge Profile
4.2
4.0
Voltage (V)
3.8
3.6
3.4
3.2
3.0
2.8
0 20 40 60 80 100
Discharge Capacity (% of nominal)
Fig. 3.2 Battery discharge profile.

3.2 Architecture 53
mental section and uses a single SAR ADC for all the eight channels. The ADC
dynamic range is set accordingly to the Li-Ion battery charge-discharge profile,
Fig. 3.2, resulting in a conversion range from 3 to 4.2 V.
This ADC has been fabricated in a 0.35-µm triple-well 5V HV CMOS pro-
cess with drain extended MOS high-voltage devices. The prototype active area is
1300 x 650 µm2 . The master clock frequency and the measured total power con-
sumption are 1 MHz and 3.64 mW, respectively. The measured input referred noise
is 177.9 µV and the residual offset is 642.5 µV.
3.2 Architecture
The extended-range conversion of this design foresees two steps. First, a coarse
conversion is carried out by an 8-channel time-interleaved first-order incremental
ADC. With an oversampling ratio (OSR) equal to 64, the coarse resolution is 6 bit.
Each incremental step requires 10 clock cycles (1 for reset, 1 for a dummy channel,
and 8 for all the channels), resulting in 640 clock cycles for the coarse stage. Once
the first phase is completed, part of the incremental converter is re-arranged as a
SAR ADC for the residual voltage conversion. The fine conversion is carried out
in 10 clock cycles for each channel, resulting in 80 clock cycles for the whole fine
stage. In total, 720 clock cycles are required for measuring the whole battery stack.
Hence, the sampling rate of the overall ADC is equal to 11.1 kS/s (1.39 kS/s each
channel), if fclk = 1 MHz. In order to achieve the 14-bit resolution required for the
entire ADC, the incremental stage uses a two-stage op-amp with large DC gain
and suitable bandwidth. Simulation results show that a DC gain of 115 dB and a
bandwidth of 20 MHz obtained by a chopper stabilised two-stage amplifier (with a
cascode as first stage) match the requirements. The comparator is a dynamic latch
with a single stage preamplifier.
3.2.1 Coarse step: 8-channel TI incremental ADC
Fig. 3.3 shows the ADC architecture during the incremental phase. A high-voltage
MIM capacitance, CS , works as sampling element of all the channels. CCM provides
a shift equal to VCM,B = 3.6 V, so that a reference voltage of ±0.6 V makes the
conversion range from 3 to 4.2 V. Eight nominally equal feedback capacitors, Cch,i ,
accumulate the charges of the interleaving architecture, and the capacitive bank,
CS AR , made by a combined 5b-binary and 3b-C-2C structure (Fig. 3.6), operates as
an injection element as required by the Σ∆ incremental function. The left plate of
CS steps up by one cell at each cycle and injects into the virtual ground, together
with CCM and CS AR , the charge
VR
Qin j,in = CS VB,i − CCM VCM,B + CS AR (2Di − 1) (3.1)
2
ø3.6 CCM
VCM,B
ø0 Cch,i øinj,1 8 CHANNELS
+
øch,8 øRES 1 DUMMY
+
B8 øch,7 øRES
B7
+
øch,6 = VCM
CP1 CP2
+
B6 øch,5 øinj = GND
B5
+
øch,4 CS øinj ølatch
+
B4 øch,3 øcm OUT
+ Chopper
B3 øch,2 Amplifier DSP
+
B2 øch,1
+VR
+
B1 øS CSAR 2
øinj øinj 1-b
HV SELECTOR
DAC
øcm øcm
- VR
2
TIMING DIAGRAM
set for set for
inj ch1 inj ch2
øRES
øS
øch,1
øch,2
øcm
ø3.6
ø0
øinj
øinj,1
øinj,2
øinj
ølatch
start start
inj ch1 inj ch2
Fig. 3.3 Battery monitor during incremental conversion with timing diagram of the phases.
where Di is the output of the comparator at each cycle, VR = 1.2 V the reference
voltage, and VB,i the battery cell voltage. CCM is implemented as a high-voltage
capacitor in order to be nominally equal to CS , and CS AR is designed to achieve a
gain of the incremental stage equal to 1. A possible gain error is compensated for
by trimming the value of VR .
3.2 Architecture 55
TI architectures that share the op-amp can suffer from crosstalk between the mul-
tiplexed channel. Therefore, it is required to maintain the charge fidelity at the sum-
ming node, which is the input node of the op-amp. A crosstalk problem would rise if
an off-channel injects some charge during the active phase of another channel, typ-
ically due to charge injection of the sampling switch that opens. This architecture
does not suffer from crosstalk because there is only one single injecting element,
named CS , and an approach “set and then inject” is used. Basically, the left plate of
the injecting capacitor is always connected to a fixed voltage, and whenever there is
a switching activity on this side, the injecting switch on the right side is kept open.
This is simply done by adjusting the clock phases in the logic. This means that in
Fig. 3.3, whenever the track&hold phases φch,i are changing, φin j is low and φcm ties
the summing node to the common-mode voltage, avoiding any possible crosstalk.
Before each conversion, all the feedback capacitances are discharged. A dummy
channel captures the charge injected by the feedback reset switch opening. This
avoids a clock feedthrough mismatch on the first battery voltage measurement, VB1 .
CP1 and CP2 avoid the open loop connection by providing a feedback path to the
operational amplifier when no channel capacitor is connected.
Standard solutions call for a low-pass filter in front of the ADC, [1–3]. This is
usually implemented with external components and results into a filter pole in the
range of [0.1 - 10] kHz. In this design, the 64 times sampling of the battery voltage
introduces a low-pass FIR filter with 64 taps. This relaxes the need of using external
components and reduces the cost.
After 64 full cycles, the residual charge stored into each feedback capacitor is
Ninc
X VR
QRES ,i =

CS AR (2Di − 1) − Ninc CS VB,i − CCM VCM,B (3.2)
i=1
2
where Ninc = 64 is the number of incremental cycles.

Since the signal is accumulated 64 times and the noise is quadratically√ super-
posed 64 times, the incremental phase attenuates the kT/C noise request by 64 = 8.
The use of a chopper-stabilised op-amp, [7–10], significantly reduces the input
referred offset. The residual offset is mainly due to the charge injection mismatch
caused by the opening of the switches connected to the virtual ground. A careful
design and layout of the op-amp keeps the error below 0.5 LSB and no calibration
is required.
3.2.2 Fine step: SAR ADC
The 64 x 8 incremental cycles obtain a 6-bit resolution for each channel. The Cch,i
capacitors store the residual charges. For extending the range, the architecture is
re-arranged as in Fig. 3.4 to form a SAR ADC. Fig. 3.5 shows the transfer of the
residual voltage from the Cch,i capacitors to CS AR . The chopper operation is disabled
and the CS AR array is pre-charged to the offset of the op-amp in an auto-zero fashion
ølatch
Chopper OUT
Amplifier DSP
øSAR
VOS
T B 1-b
DAC
CSAR
Fig. 3.4 Battery monitor during SAR phase.
øRES Cch,i
øMIS,i
Chopper Chopper
Amplifier Amplifier
VOS VOS øSMP_SAR

øMIS T B
øMIS T B
CSAR øCM CSAR
(a) (b)
Fig. 3.5 Mismatch cancellation technique during charge transfer to CS AR . (a) Auto-zero phase. (b)
Charge transfer from incremental channel to SAR array.
(Fig. 3.5(a)), [11]. Then, the residual charges are sequentially transferred to CS AR in
order to perform the SAR conversion cycles (Fig. 3.5(b)).
The relaxed accuracy constraints of the second conversion stage allow using a
DAC array, CS AR , made by a combined binary and C-2C structure (Fig. 3.6). The
array is composed by 41 poly capacitors CU of 40 fF. The total capacitance results
in CT OT = 1.64 pF. The SAR uses the same comparator of the incremental converter
and recycles the 1-b DAC to control the bottom plates of the capacitances.
Since both incremental and SAR steps use CS AR for balancing the input, there is
no mismatch between the two phases. Moreover, input sampling and voltage shift
use the same type of high-voltage capacitors. A minor limit can come from the
virtual
T B 1-b
ground DAC
CSAR
T 2CU 2CU 2CU
16CU 8CU 4CU 2CU CU CU CU CU
VIN
VRP
VRN
B
Fig. 3.6 CS AR array architecture. 5 bits are implemented in a binary fashion, and 3 bits use a C-2C
structure.
mismatch between feedback channel capacitors, Cch,i . Their role is to generate the
voltage driving the comparator during the incremental phase. Since the mismatch
changes the amplitude but not the sign, the possible error is in the dynamic output
of the op-amp. It is just necessary to keep the operation in the linear region for
avoiding harmonic distortion.
Apart from the logic generating the control signals for the ADC, the architecture re-
quires only a track & hold, an operational amplifier and a comparator for monitoring
the battery stacks.
3.3.1 High Voltage Track & Hold
Fig. 3.7(a) shows the scheme commonly used for a bi-directional high-voltage
switch driven by a low-voltage logic control. A back-to-back pMOS configuration
with extended drain avoids diode forward biasing when the biasing of the switch re-
verses. In order to turn on the transistors, a low-voltage clock signal, CLK, is used.
When the clock signal is high, the current IS W through the resistor RS W generates
the proper V sg . A high-voltage nMOS transistor, tied to VDD,LV = 5 V, ensures that
VIN
CS
Vsg = RswIsw ron ron
Rsw VIN V’OUT
VDD,LV
CS
CLK Rsw
Isw
Isw
(a) (b)
Fig. 3.7 High-voltage track & hold. (a) Schematic. (b) Offset due to ron .
VIN
Vdmy VOUT
Cd CS
Rsw
VDD,LV
CLK
Isw
Fig. 3.8 Proposed high-voltage track & hold with dummy structure.
the drain node of the low-voltage transistor does not exceed (VDD,LV - Vth ). This
solution is suitable for low accuracy or logic signals. For precise applications, the
current IS W flowing in RS W , used to turn on the transistors, also flows through one
of the two back-to-back p-channel elements and this causes a non-linear drop ∆V
that generates an offset affecting the sampled voltage, Fig. 3.7(b).
The value of V sg chosen to give rise to the on-condition is the RS W IS W product.
The choice of the V sg , the RS W value and the required speed of operation determine
the minimum (non-linear) ron . Indeed, there is a maximum size for the transistors,
since their gate capacitance and the value of RS W give rise to a time constant that
might limit the speed of the switch. It is possible to reduce the time constant with
lower values of RS W but IS W increases and augments the generated offset. The re-
sult is that the speed of operation critically affects the on-resistance of the switch.
Extensive simulations at the transistor level show that the offset (the product of IS W
and the on-resistance) is, for a sampling frequency of 1 MS/s, much larger than the
expected LSB. This circuit solves the problem by using a matched dummy structure
that generates the proper V sg . The control voltage is then used to drive the actual
switch, as shown in Fig. 3.8. In this way, no static current flows through the sampling
switch and the required accuracy is achieved. The non-linearity of the on-resistance
is ineffective if the sampling period is a suitable number of time constants ron CS .
This design uses an optimal power, speed and silicon area trade-off that leads to
IS W = 80 µA, RS W = 50 kΩ and W/L = 10/1 µm/µm. The HV sampling capacitance
is 1.6 pF, the obtained ron is about 5 kΩ leading to a time constant as small as 8 ns.
Fig. 3.9 shows the sampling error as a function of the input voltage for the stan-
dard solution and the actual switch. The error for the circuit in Fig. 3.7 is non linear
and can be as large as 320 mV. In particular, for input voltages lower than 5 V, the
drop across the switch is lower since the low input voltage is pushing the current
mirror implementing the current generator IS W in the triode region, thus decreasing
the IS W value. By contrast, the actual switch works very well. It shows an error that
is a linear function of the input voltage and is just 1.5 µV at the nominal full scale
voltage VIN = 33.6 V.
The simple structure of the switch results in an area-per-switch of 0.006 mm2 ,
significantly smaller than the solutions in [12, 13]. Moreover, the circuit implemen-
tation does not require high-voltage capacitors to operate.
0.32
VIN-V'OUT [V]
0.3
0.28
0.26
5 10 15 20 25 30
1.5
VIN-VOUT [μV]
0.5
0
5 10 15 20 25 30
VIN [V]
Fig. 3.9 Sampling error as a function of the input voltage. (a) Standard approach. (b) Proposed
solution.
3.3.2 Operational amplifier with chopping technique
Fig. 3.10 shows the schematic of the used operational amplifier. It is a two stage
amplifier with a telescopic cascode as the first stage and an inverter with active load
as second stage. The first stage uses a high-compliance current mirror for increasing
the voltage room for the input pair and the current generator. The op-amp is designed
to drive a capacitive load as large as 2 pF.
The amplifier is Miller compensated. A zero-nulling resistance, R0 , further in-
creases the phase margin. C M = 4 pF and R0 = 550 Ω, allow achieving a phase
margin of 65◦ . A biasing current of 100 µA is used and a DC gain of 120 dB and a
bandwidth equal to 20 MHz are obtained.
Equation (3.1) does not account for the offset of the op-amp. When considering
it, (3.1) becomes
V
R
Qin j,in = CS (VB,i − Vos ) + CCM (−VCM,B − Vos ) + CS AR (2Di − 1) − Vos (3.3)
2
In 2
I’n
2
CHOPIN
I’p
Ip 1
VDD
I’n I’p CM
VO
VB1 R0
1
ISS
2 1
2
VB2 CHOPOUT
Fig. 3.10 Schematic view of the operational amplifier with chopping technique.
where Vos is the offset of the op-amp. Assuming, for simplicity, that all the injecting
capacitors CS , CCM and CS AR are equal and called Cin j , then (3.3) becomes
VR
Qin j,in = Cin j VB,i − VCM,B + (2Di − 1) − 3Vos (3.4)
2
and the residual charge would present an error due to the offset injection at each
clock cycle, resulting in
N 
inc
X VR 
QRES ,i = Cin j 

 (2Di − 1) − Ninc VB,i − VCM,B − 3Ninc Vos  (3.5)
i=1
2
The residual voltage is derived from the residual charge, by simply dividing it by
the integrator capacitor, Cch,i . Again for simplicity, this is considered equal to Cin j ,
resulting in a residual voltage equal to
Ninc
X VR
VRES ,i =

(2Di − 1) − Ninc VB,i − VCM,B − 3Ninc Vos (3.6)
i=1
2
This would lead to an error due to the offset that is larger than the LSB. The
cancellation of offset and low-frequency noise is conventionally obtained with auto-
zero, [11], or chopper methods, [7–10]. The proposed solution uses a chopped am-
plifier to deal with this problem.
Fig. 3.11 Chopper technique basic scheme.

The chopper technique transposes the input signal to high frequency by modula-
tion, as done by the multiplier M1 of Fig. 3.11(a), and then demodulates it back to
the baseband with the multiplier M2 after amplification. The modulating signal is a
square-wave signal, m(t) , with period T = fchop 1
. After the first modulation, offset
and 1/ f noise (Vos and Vn , respectively) corrupt the signal, but they are transposed
to high frequency by the action of M2 . Fig. 3.11(b)-(d) depicts the spectra of the
signal involved in the relevant points of the processing chain. The frequency noise
added to input of A1 , modulated by M2 and replicated at multiple of fchop , is lowpass
filtered by the finite bandwidth of A1 . M1 and M2 are implemented in the op-amp
architecture by the CHOPIN and CHOPOUT networks shown in Fig. 3.10.
Due to mismatch in the circuit, there is a residual offset at the end of the conver-
sion, Vos,res , that affects (3.7) in the same way as the original offset
Ninc
X VR
VRES ,i =

(2Di − 1) − Ninc VB,i − VCM,B − 3Ninc Vos,res (3.7)
i=1
2
The input voltage can be derived from 3.7 as

 Ninc 
 P
 (2Di − 1) 

 i=1 VRES ,i
VB,i − VCM,B =   VR − Ninc − 3Vos,res (3.8)

 2Ninc 

where the first term is the digital representation of the input signal, the second one
the quantisation error, and the final one the offset error. Therefore, the residual offset
has to introduce an error that is negligible if compared to the LSB of the SAR stage.
Thus, the residual offset needs to be smaller than
VR
Vos,res < (3.9)
3 · 2NS AR
With VR = 1.2 V and NS AR = 8 bits, the residual offset cannot exceed 1.5 mV. This
is easily achievable with the used chopping technique.
At the end of the incremental phase, the charge stored in the feedback capacitors
is transferred to the DAC array, CS AR . In this case, since the operation is single, the
chopping technique is not effective. Instead, an auto-zero technique is used. In phase
one, Fig. 3.5(a), CS AR is reset to the offset of the op-amp, leading to
QCS AR = VosCS AR (3.10)
QCch,i = QRES ,i (3.11)

CS AR is then connected in feedback and the charge in Cch,i is injected into it, as
shown in Fig. 3.5(b). The final charge in CS AR becomes
QCS AR = QRES + VosCS AR − VosCch,i (3.12)

The error due to the offset, in this phase, is only caused by the mismatch in the
capacitors CS AR and Cch,i , and it can be expressed as
(CS AR − Cch,i )
Verr = Vos (3.13)
CS AR
Choosing a large enough CS AR ensures this error to be negligible.
3.3.3 Voltage Comparator
Fig. 3.12 shows the schematic diagram of the voltage comparator used in this design.
The structure uses a single stage preamplifier for improving the noise performances.
This is a single-ended stage with active load. The latch is a standard sense-amplifier
based latch [14]. A biasing current equal to 25 µA ensures a bandwidth large enough
to accommodate the 1 MHz clock operations.
VDD VDD
Op
clock On clock
ISS
VR VIN VR
clock
Fig. 3.12 Comparator schematic view of the comparator with preamplifier.
3.4 Measurement Results
This ADC has been fabricated in a 0.35-µm triple-well 5V HV CMOS process with
drain extended MOS high-voltage devices. The prototype has been measured with
the nominal supply voltage of 5 V and its active area is 1300 x 650 µm2 . Fig. 3.13
depicts the whole chip microphotograph and a magnified view of the active area,
where the main circuit blocks have been highlighted. The large area occupied by the
high-voltage front-end is due to comply with the minimum ESD distance rules of
the used technology. The low voltage section is formed by the op-amp, the voltage
Active area
Low-voltage
analog circuits
High-voltage Low-voltage
(op-amp, voltage
switches and capacitor digital logic
comparator)
and capacitors
Technology: 0.35-µm triple-well

5V HV CMOS with drain extended
high-voltage MOS devices
Chip size: 2100 µm x 2100 µm

Active area: 1300 µm x 650 µm
Fig. 3.13 Chip microphotograph.
HIGH-VOLTAGE DIGITAL LOW-VOLTAGE

SECTION OUTPUT SECTION
Fig. 3.14 Testing board.
comparator and the capacitors bank (8 channels, 1 dummy channel, 1 SAR/feedback

bank). The capacitor injecting the battery common-mode, CCM , and CS are both
high-voltage with a well matched layout in the HV section. Finally, the low-voltage
digital logic provides all the control signals to the system.
Fig. 3.14 shows the testing board that was implemented for the measurement
setup. The high-voltage section provides the input signals to the battery monitor,
while the low-voltage section generates all the reference voltages (VRP , VRN , VCM
and VCM,B ) and the supply voltages (AVDD and DVDD ) for the ADC. Finally, the
60
Mean Value = 642.5 μV
50 σ = 177.89 μV
40
Samples 30
20
10
0
3 4 5 6 7 8 9 10 11 12 13 14 15
13
(Output Code - 2 ) [LSB@14 bit]
Fig. 3.15 Histogram of 300 repeated measures with VIN = VCM .
-20
-40
PSD [dB]
-60
-80
-100
-120
-140
10 -2 10 -1 10 0 10 1 10 2
Frequency [Hz]
Fig. 3.16 Measured output spectrum (FFT with 218 points).
digital output is collected by means of a logic analyzer and the data is processed in
Matlab environment.
Fig. 3.15 shows the histogram of 300 repeated measurements on channel 1, with
the input shorted to VCM , which is at half scale of the converter. It measures the
input referred noise, whose variance is 177.9 µV, and the residual offset, equal to
642.5 µV.
Fig. 3.16 gives the measured output spectrum with a full scale sine wave (0.6 V
peak value) at 2.78 Hz applied on channel 8. The SNDR is 76.7 dB (12.45 bit). The
harmonic tones amplitude is very low and limits the SFDR at -96 dBFS .
Figg. 3.17 and 3.18 show the measured INL and DNL resulting from the his-
togram of a full scale input sine wave on channel 4. The INL is in the [-2,0.5] LSB
range and the DNL is in the [-1,0.8] LSB range. Similar both static and dynamic
results have been collected from all the channels. The endpoint fit line INL shows
a good linearity of the high-voltage capacitor CS in the ±0.6-V range. The linearity
over the full 33.6-V range depends on the voltage coefficients of the high-voltage
capacitor, CS (V) = CS (0)(1+αV). Fig. 3.19 shows the nonlinearity error of the mea-
0.5
0
INL [LSB@14 bit]
-0.5
-1
-1.5
-2
-2.5
0 5000 10000 15000
Output Code
Fig. 3.17 Measured INL.
1.5
1
DNL [LSB@14 bit]
0.5
-0.5
-1
0 5000 10000 15000
OUTPUT CODE
Fig. 3.18 Measured DNL.

35
OUT CH,i - OUTCH1 [LSBs]

30
25
20
15
10
5
0
1 2 3 4 5 6 7 8
CHANNEL #
Fig. 3.19 Measured output (average of 100 measurements) of the ADC when the same input is
applied to all the channels.
sured outputs (average of 100 measurements) when the same input is applied to all
the channels (VB,i = 3.6 V). The result is the difference with respect to the first chan-
nel output and is expressed in LSBs (14-bit). The figure shows a voltage coefficient
of 96 ppm/V. The error is almost the same for all the available chips and can be
corrected in the digital domain.
Fig. 3.20 shows the system power breakdown with 1 MHz of master clock fre-
quency. The total power consumption is dominated by the digital logic and is equal
to 3.64 mW.
Table 3.1 summarises the battery monitor performances and provides a compar-
ison with existing solutions. The comparison is performed by using the Schreier
figure of merit, FoMS = SNR + 10 log(BW/P), [15]. In this design the SNR, the
bandwidth and the power consumption are 76.7 dB, 700 Hz and 3.64 mW, respec-
tively. The resulting FoMS is 129.5 dB. The achieved results are competitive, con-
Voltage References Digital Logic

0.04 mW (1%) 2.135 mW (59%)
Op-Amp
0.94 mW (26%)
Voltage Comparator
0.125 mW (3%)
High Voltage T/H
0.4 mW (11%)
Fig. 3.20 Measured battery monitor power breakdown.

Table 3.1 Performance summary and comparison table.

This Work [1] [2] [3] [4]
Supply Voltage 5V [7.2 - 27] V [10 - 55] V [8 - 30] V [5.2] V
Cell Input DR 1.2 V 4.5 V 5V 4V 2.5 V
Resolution 214 µV 380 µV 1.5 mV 980µV 2.3 mV
ENOB 12.45 b 13.5 b 11.7 b 12 b 10.1 b
SNR 76.7 dB 83 dB 72.2 dB 74 dB 62.5 dB
Offset 642.5 µV calibrated 500 µV 610 µV -
Measured Cells 8 6 81 6 6
Bandwidth 700 Hz 11.9 kHz 55.5 Hz 83.3 kHz 200 kHz
Total Power
3.64 mW 13.1 mW 10.7 mW 42.5 mW1
1 2 -
Consumption
FoMS 129.5 dB 142.6 dB 109.4 dB 136.9 dB -
1 Reduced to 8 for this comparison. [2] can measure up to 12 cells.
2 Estimated power consumption - 25% of total power consumption
sidering that the works reported in [1] and [3] can measure only up to 6 cells. The
system in [4] implements a parallel solution that uses 6 transimpedance amplifiers
(TA) as level shifters, and 6 Σ∆ ADCs. This overhead in complexity is likely paid in
larger power consumption and occupied area. Besides, the inter-channel matching
becomes a major concern in parallel architectures.
3.5 Conclusions
In this chapter, a battery monitor system was presented. The architecture uses a time-
interleaved incremental converter for coarse conversion and a single SAR ADC for
fine conversion. The use of the same ADC for all the channels in the fine step relaxes
the matching requirements in the time-interleaved structure. A HV track & hold
with low-voltage logic control interfaces the A/D with the battery stack. This so-
lution achieves high linearity and low cost.
The battery monitor has a resolution of about 0.2 mV, consuming 3.64 mW with
an area of 1300 x 650 µm2 . All channels are measured in 720 µs. The measured
residual offset is 642.5 µV. The dynamic input range of the system can be as large
as 33.6 V, and the achieved figure of merit is 141.9 dB.
The description of this ADC and the measurement results were presented in a
paper published in the IEEE Transactions on Circuits and Systems - II: Express
Briefs titled “High-Resolution Time-Interleaved 8-Channel ADC for Li-Ion Battery
Stack”, [16].
References 69
References
1. Texas Instruments, “Stackable HEV/EV Li-Ion Battery Monitor and Protector”,

BQ76PL536A-Q1 datasheet.
2. Linear Technology, “Multicell Battery Stack Monitor”, LTC6803-1/LTC6803-3 datasheet.
3. Analog Devices, “Lithium Ion Battery Monitoring System”, AD7280A datasheet.
4. K. Kadirvel, J. Carpenter, P. Huynh, J. M. Ross, R. Shoemaker, B. Lum-Shue-Chan, “A

Stackable, 6-Cell, Li-Ion, Battery Management IC for Electric Vehicles with 13, 12-bit Σ∆
ADCs, Cell Balancing, and Direct-Connect Current-Mode Communications”, IEEE J. of
Solid-State Circuits, vol. 49, no. 4, pp. 928-934, April 2014.
5. A. Agah, K. Vleugels, P.B. Griffin, M. Ronaghi, J.D. Plummer, and B.A. Wooley, “A High-
Resolution Low-Power Incremental Σ∆ ADC with Extended Range for Biosensor Arrays”,
IEEE J. of Solid-State Circuits, vol. 45, no. 6, pp. 1099-1110, 2010.
6. J. De Maeyer, P. Rombouts, and L. Weyten, “A Double-Sampling Extended-Counting ADC”,

IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 411-418, Mar. 2004.
7. C. C. Enz, E. A. Vittoz, and F. Krummenacher, “A CMOS Chopper Amplifier,” IEEE J.

Solid-State Circuits, vol. SC-22, no. 3, pp. 335-342, Jun. 1987.
8. A. Bakker and J. H. Huijsing, “A CMOS Chopper Opamp with Integrated Low-Pass Filter,”
Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 1997, pp. 200-203.
9. A. Bilotti and G. Monreal, “Chopper-Stabilized Amplifiers with a Track-and-Hold Signal

Demodulator,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 4, pp. 490-495,
Apr. 1999.
10. J. F. Witte, K. A. A. Makinwa, and J. H. Huijsing, “A CMOS Chopper Offset-Stabilized

Opamp,” J. Solid-State Circuits, vol. 42, no. 7, pp. 1529-1535, Jul. 2007.
11. C.C. Enz and G.C. Themes, “Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, Proc.
IEEE, pp. 1584-1614, 1996.
12. L. Xu, B. Gonen, Q. Fan, J.H. Huijsing, and K.A.A. Makinwa, “A 100dB SNR ADC with
±30V Input Common-Mode Range and 8µV Offset for Current Sensing Applications”, IEEE
International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 90-91, Feb.
2015.
13. D. Yilmaz and I. Ozkaya, “25V Sampling Switch for Power Management Data Converters
in 0.35µm CMOS with DNMOS”, Proc. of IEEE European Solid-State Circuits Conference
(ESSCIRC), pp. 136-139, Sept. 2009.
14. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A Current-Controlled Latch Sense

Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture”, IEEE J.
Solid-State Circuits Conf. Dig. Tech. Papers, vol.28, pp.523-527, Apr. 1993.
15. R. Schreier and G.C. Temes, “Understanding Delta-Sigma Data Converters”, New York:
Wiley, 2005
16. D. G. Muratore, E. Bonizzoni, S. Verri, F. Maloberti, “High-Resolution Time-Interleaved 8-

Channel ADC for Li-Ion Battery Stack” IEEE Transactions on Circuits and Systems - II: Ex-
press Briefs, DOI: 10.1109/TCSII.2016.2597358, 2016.
Chapter 4
A 200 µW 12-b 8 MS/s SAR ADC for Ultrasound
Systems
Abstract During the period spent in the Microsystems Technology Laboratories at

the Massachusetts Institute of Technology, a 12-bit 8-MS/s SAR ADC was designed
for a wearable transcranial doppler ultrasound system. This was done in collabo-
ration with the principal investigator of the project, Sabino Joseph Pietrangelo. A
hybrid capacitive and resistive DAC was implemented in order to match the area
constraint for the 64 channels system. Post-layout noise-transient simulation results
show an ENOB equal to 11.3 bits in the band of interest, [1.8 - 2.2] MHz. The
ADC was designed in 65nm LP CMOS Technology, occupies 0.04 µm2 and con-
sumes 200 µW with a nominal supply voltage of 1.2V. The resulted figure of merit
is 9.9 fJ/conversion-step
4.1 Introduction
The project carried out in the Microsystems Technology Laboratories at the Mas-
sachusetts Institute of Technology details the design of a transcranial Doppler
(TCD) ultrasound system to measure cerebral blood flow velocity (CBFV) at the
middle cerebral artery (MCA). TCD sonography has been clinically indicated in a
variety of neurovascular diagnostic applications. Acceptance of conventional TCD
methods, however, has been primarily impeded by several constraints, including re-
strictive system form factors, measurement reliability concerns, and the need for a
highly-skilled operator. The goal of this work is to reduce the effects of such lim-
itations through the development of a highly-compact, wearable TCD ultrasound
system for autonomous CBFV measurement. [1]
Fig. 4.1 shows the architecture used for implementing the transcranial Doppler
ultrasound system. Pulse excitation waveforms are generated in the processing unit
and are relayed to each independent high-voltage (HV) pulser channel. The HV
pulsers transform digital excitation waveforms into HV transmit pulses. Within the
transducer array, each element is connected to a HV pulser channel. The piezoelec-
tric transducer elements convert the HV transmit pulses into acoustic energy, which
71
72 4 A 200 µW 12-b 8 MS/s SAR ADC for Ultrasound Systems
Fig. 4.1 Architecture of the transcranial Doppler ultrasound system. [1]
is radiated into the propagating medium. During transmit, the HV transmit/receive

(T/R) switches - one per transducer element - are open to protect sensitive receive
electronics from HV signals.
During receive mode, acoustic energy is converted into a low-level electrical sig-
nal at each transducer element. The HV T/R switches close, providing a path to
the low noise amplifier (LNA) of the analog front end (AFE), with one AFE per
transducer element. A variable gain amplifier (VGA) further amplifies the received
signals such that signal levels are within the ADC operating range. An anti-aliasing
filter (AAF) is used to low-pass filter the signal so that spectral content beyond the
Nyquist frequency does not result in aliasing. The analog signals are then digitised
and the resulting bitstreams are sent to the processing unit. Receive beamforming
is achieved in post-processing through simple delay and sum methods (i.e., time
delaying each channel and adding the resulting outputs). Data can be further manip-
ulated within the processing unit to obtain velocity estimation, stored to memory, or
transferred to a computer via USB for data collection and further analysis.
The implementation of a discrete prototype of this architecture, done by the main
investigator S. J. Pietrangelo, allowed to extract the specifications for the integration
of the AFE blocks. The data output by the ADC of each channel is decimated and
sum up by the post-processing unit. This allows to relax the requirements on the
non-linearities introduced by the ADC. In particular, only non-harmonic tones in-
troduced into the output spectrum are a problem. These tones are mainly generated
by coupling of the analog blocks of the converter to the supply voltage noise, and by
the noise introduced by the digital clocking. Table 4.1 summarises the specification
requirements for the single-channel ADC described in this chapter.
4.2 Architecture 73
Specification Value
Resolution 12 bits
Sampling Frequency 8 MS/s
Power Consumption <250 µW
SNDR >68 dB
SFDR (non-harmonic) >75 dB
Area <0.05 mm2
Table 4.1 ADC specifications.
4.2 Architecture
Fig. 4.2 shows the architecture of the SAR ADC. A combined resistive and capaci-
tive DAC, [2, 3, 8] reduces the area occupied by the converter. The input is sampled
on the bottom plate of the capacitive section of the DAC (C-DAC). The differential
structure provides the input to the comparator, which is implemented as a double-
tail latch, [9]. The output of the comparator controls the switch driving registers,
that controls the bottom plate of the DAC. A decoder for the resistive steps of the
converter drives the resistive string that implements the R-DAC. A self timing logic
controls the shift register and optimises the phase generation for the converter, im-
plementing an asynchronous ADC, [10]. In order to reduce the power consumption,
a power switch disconnects the string during the first 7 cycles, when the C-DAC is
operating, so that no static current flows through it. The last resistor in the string
is intentionally made smaller , in order to compensate for the on resistance of the
power switch.
4.2.1 R-C DAC tradeoff
The design choices of the C-DAC structure in conventional SAR ADCs depend
on two factors: the kTC noise requirements, and the mismatch accuracy. These con-
straints limit the minimum unit capacitance used in the converter, and the total array
area. While the first factor is an absolute limit on the value of the sampling ca-
pacitance, the second factor is technology related and depends mainly on the area
occupied by the array. In this particular application, the harmonic distortion gener-
ated by the capacitor mismatches is not a major concern. Hence, the only limit in
the choice of the C-DAC array is on the kT C noise.
The LSB value in this ADC is equal to VLS B = 2VNRbit = 293 µV, where the refer-
ence voltage VR is 1.2 V and Nbit = 12 bits. A 7-bits binary capacitive array consists
of 128 unit capacitances. Metal-Insulator-Metal capacitors (MIM) are chosen be-
cause of their reduced parasitics and better mismatch characteristics respect to other
capacitors available in the technology used. The minimum MIM capacitor in this
process is 9.5 fF, which leads to a total sampling capacitance of 1.2 pF. This results
into a kT
C noise contribution equal to 58.8 µV, which is safely below the LSB value.
This choice is compliant with the noise requirements of the system and it is an
optimum trade-off between the area occupied by the C-DAC and the complexity
of the R-DAC decoder. In fact, every extra bit implemented in the R-DAC doubles
the complexity and the area occupied by the decoder of the resistive string, as well
as the area of the resistive string itself. This is true, because the resistive string is
implemented in a thermometric fashion in order to ensure the monotonicity of the
converter.
4.2.2 ADC timing and searching algorithm
This converter uses a standard binary searching algorithm. A self-time logic clocks
the ADC and provides the control signals to the shift register and the comparator. A
delay block allocates a fixed time-slot for the DAC settling. Different sizing for the
switches driving the bottom plates of the C-DAC ensures a similar RC constant time
for each step, thus optimising the time-distribution for this action. After the DAC
settles, the comparator is latched. A digital block senses the output of the comparator
and provides a feedback signal, done, to the self-timing logic that moves on to the
next step of the shift registers. Consequently, the switch driving registers changes
the code of the DAC and the searching algorithm proceeds. The resulting timing
diagram is the one in Fig. 4.3. As explained above, the DACi slots are decided by a
bn<12> bn<11> bn<6> bn<5>
Smp
MUX
Vrp
Vrn
inn
64CU 32CU CU CU Rsw
VCM Smp
SW DRIVING bn<n>
REGISTERS bp<n>
64CU 32CU CU CU
VQ<n>
end of
latch
comparison
inp
done
MUX
Vrn
Vrp SHIFT
Smp REGISTERS
SELF go, stop
Rsw TIMING
bp<12> bp<11> bp<6> bp<5>
Smp
Fig. 4.2 Architecture of the SAR ADC.

4.2 Architecture 75
delay block inside the self-timing that is controlled by the system, while the CMPi
slots are variable and depend on the decision time of the comparator at each cycle.
SAMPLE DAC12 CMP12 DAC11 CMP12 DAC2 CMP2 DAC1 CMP1
Fig. 4.3 Timing diagram of the SAR ADC.
DAC5 DAC4 DAC3 DAC2 DAC1
‘1’ 31/32 VR
‘1’
‘0’ 29/32 VR
‘1’ 27/32 VR
‘1’ ‘0’
‘0’ 25/32 VR
‘1’ 23/32 VR
‘0’ ‘1’
‘0’ 21/32 VR
‘1’
‘1’ 19/32 VR
‘0’
‘0’ 17/32 VR
‘1’ 15/32 VR
‘1’
‘0’ 13/32 VR
‘0’
‘1’ 11/32 VR
‘1’ ‘0’
‘0’ 9/32 VR
‘1’ 7/32 VR
‘0’ ‘1’
‘0’ 5/32 VR
‘1’ 3/32 VR
‘0’
‘0’ 1/32 VR
Fig. 4.4 R-DAC steps for the last 5 LSBs conversion.
The first 7 MSBs of the DAC code, b<12:6> , control the bottom plates of the ca-
pacitive array during the capacitive searching steps. The last 5 LSBs are explored
by the resistive string connected at the bottom of the last unit capacitor of the ca-
pacitive array and follow a binary search like in Fig. 4.4. The reference voltages
of the resistive string are multiplexed by the control signal b<5> . The output of the
multiplexer is then divided by the C-DAC passive network providing the required
steps at the input of the comparator. In particular,
VR−DAC
Vin,cmp = VC−DAC +
27
the voltage on the top plates of the array is equal to the voltage provided by the
C-DAC code plus the voltage provided by the R-DAC attenuated by 27 .
In this section, the circuital design of the main blocks of the converter are described.
They are the digital logic, the DAC and the comparator.
4.3.1 Digital Logic
Fig. 4.5(a) describes the logic circuit that implements the self-timed phase genera-
tion used for this ADC. This block generates the clock of the comparator, latch, and
sets the timing of the converter operation. It also provides two signals, go and stop,
that are needed for starting and stoping the shift register used in the SAR algorithm.
The logic is based on a set/reset latch (SR latch), that is triggered by the signal
done and its delayed version. Basically, every time the latch comparison is finished,
the signal done goes high, and latch is reset. After a controlled delay, the SR latch
is set and a new comparison is done. At the beginning of the conversion cycle, the
latch signal is set by a start strobe generated from the falling edge of the sampling
clock. Either start or done trigger a D-flipflop with its input tight to ’1’, the output,
delayed by a current limited inverter, sets the SR latch. The controls of the latch are
masked by the go and stop in order to leave the latch signal low when the converter is
not running. Fig. 4.5(b) describes the timing diagram of the block, while Fig. 4.5(c)
SMP
D Q stop go
SMP stop
go
RES_EXT
R
EOC start
stop tDAC tDAC
set
S Q latch
D Q SET
NOR
start
done delay done
based
RESET
ctrl R Q latch
R
latch
go
latch
RES_EXT tcmp tcmp
EOC done
(a) (b)
25 μm
4 μm
(c)
Fig. 4.5 Self-timed phase generator. (a) Schematic view. (b) Timing diagram. (c) Layout view.
15 μm
D+
D- done
D Q
5 μm
R
latch
(a) (b)
Fig. 4.6 End of comparison logic block. (a) Schematic view. (b) Layout view.
stop
go stop go go stop
latch latch latch latch latch
latch latch latch latch latch
(a)
VQ<12> VQ<1>
40 μm
4 μm
(b)
Fig. 4.7 Shift register block. (a) Schematic view. (b) Layout view.
shows the layout view of the self-timed phase generator. The simple structure allows
to occupy only an area of 25 x 4 µm2 .
The signal done used in the phase generator is provided by an end of comparison
logic, shown in Fig. 4.6(a). The logic senses when the differential output of the
comparator has settled to either ’10’ or ’01’. In case of metastability, a control path
triggers the done signal and the outcome of the comparator is assumed to be ’0’. The
logic waits a given time, decided by design, before forcing the end of comparison.
The delay is implemented as a chain of inverters, properly sized. The delay and the
comparator are designed such that the probability of metastability is very low in case
of a differential input larger than half LSB. This ensures that an arbitrary decision
on the output of the comparator, in case of metastability, does not introduce an error
larger than the quantization one. Fig. 4.6(b) shows the layout view of the logic (the
comparator is not included). The area occupied is 15 x 5 µm2 .
Fig. 4.7(a) shows the shift register used for implementing the SAR algorithm.
The structure is a delay line clocked by the latch signal. At the end of each con-
Y VQi
VQ12
VQi-1
VQi-1
BPPi BNNi
s
s VQi Y
BNPi BPNi
(a)
45 μm
10 μm
(b)
Fig. 4.8 Switch driving registers for the capacitive steps of the DAC. (a) Schematic view. (b)
Layout view.
version cycle, go and stop reset the shift register to a known starting point. Instead,
at the beginning, a pulse, generated by the feedback path, propagates through the
delay line like in a standard shift register. Extra logic generate the VQ masks that
will be used in the switch driving registers. Fig. 4.7(b) shows the layout view of the
shift register. The area occupied is 40 x 4 µm2
The VQ masks are strobes that are used to time the converter steps. They
are used in the switch driving registers to control both the bottom plates of the
capacitive DAC and the resistive string multiplexer. Fig. 4.8 shows the single cell
of the switch driving register used for the capacitive steps of the DAC. The outputs
of the cell directly control the switches to VRN and VRP at the bottom plates of
the capacitive array. In particular, BPN and BPP control the positive and negative
reference switches of the positive section of the differential DAC, while BNP and
BNN control those of the negative section.
During the input sampling, the signal s resets the decoder and disables all the
reference switches. At the first SAR cycle, the signal V Q<12> sets the positive ar-
ray to VRN and the negative one to VRP according to the SAR searching algorithm.
This is not the case for the cell controlling the capacitor defining the most signifi-
cant bit (MSB), as it has to be set to the opposite values (VRP for the positive array
and VRN for the negative one). At the i step, the signals V Q and V Q set the
i significant bit (iSB) to the test position (VRP for the positive array and VRN for
the negative one). One clock cycle later, at the i − 1 step, the signals V Q<i−1> and
V Q<i−1> capture the output of the comparator Y and Y and store them in the decoder.
The memory function is done by placing a minimum size inverter in positive feed-
back between the BNP and BPP nodes and the intermediate node of the decoding
cell.
This decoder serves the capacitive DAC and helps to implement the conversion
of the 7 MSBs. The remaining 5 least significant bits (LSBs) are explored by the
resistive string connected to the last unity capacitor of the array, as in Fig 4.2. During
this phase, the power switch connects the resistive string to the supply, so that the
reference voltages are available.
60 μm
10 μm
Fig. 4.9 Layout view of the switch driving registers and the decoder for the resistive steps of the
DAC
The structure of the switch driving registers for the resistive DAC is similar to the
one illustrated for the capacitive DAC. The main difference lies in the way the output
of the comparator is masked. If only the signal VQ was necessary before, in this
case, an extra mask is required to recognise the path that the conversion algorithm
has taken. In particular, at each step the R-DAC would step up or down according
to the output of the comparator, following the paths described in Fig. 4.4. For exam-
ple, for i = 3, a positive output of the comparator would move the R-DAC to either
3/8 VR or 7/8 VR . In order to provide the correct code to the DAC, it is necessary to
know the decision made in the previous step. Doing this, an extra mask is generated
for differentiating the two options. The generation of these masks is more compli-
cated as we increase the resolution of the R-DAC. This is the main trade-off in the
division between capacitive and resistive DAC for the converter. The proposed so-
lution does not introduce an excessive overhead for the resistive decoder, as Fig. 4.9
shows. In fact, the area is slightly bigger than the one that it would be required for
only-capacitive switch driving registers. The total area for both the decoder and the
switch driving registers for the resistive steps of the DAC is 60 x 10 µm2 , while the
one occupied by the switch driving registers for the capacitive steps is 45 x 10 µm2 .
Implementing 5 bits with a resistive DAC introduces a negligible overhead, if
compared to the advantage of having a capacitive array that is 32 times smaller.
This solution, if compared to others like split-DAC [4, 5] and C-2C [6, 7], achieves
similar benefits in terms of the area occupied with a simpler structure. Besides, non-
linearities issues are not a major concern in R-C DACs, while they become the main
limiting factor in split-DACs and C-2C DACs.
4.3.2 DAC
The differential C-DAC uses a quasi common-centroid structure that balances as

much as possible the boundary conditions and maintains a simple interconnection
network. In fact, the systematic non-linearities generated by a capacitive DAC de-
pends mainly on the systematic mismatch between the top-to-bottom parasitic ca-
pacitance of each capacitor in the array. The top-to-bottom parasitics come from the
coupling between the top plate and the bottom plate of the same capacitor, or the
ones of adjacent capacitors. Ideally, if every capacitor presents the same boundary
condition, the parasitic capacitance for the array is systematically matched. Yet, the
capacitors at the border of the array present a different condition, as one or two sides
of the capacitor are adjacent to a dummy structure connected to ground. This trans-
lates into a top-to-ground and bottom-to-ground parasitic coupling and introduces a
systematic mismatch in the DAC array. The idea, shown in Fig. 4.10, is to balance
the number of unit capacitors placed at the border of the array in order to improve
the matching. In the proposed solution, the 3-MSB capacitors are matched by en-
suring 28 border connections to 27 CU , 14 to 26 CU and 6 to 25 CU . This approach
allows to reduce the mismatch error in the C-DAC operation well below the LSB
value, and keeps a common-centroid approach for optimum random matching of the
array.
Fig. 4.11 shows the layout view of the implemented DAC. The block is com-
posed by the described differential C-DAC, two thermometric R-DAC, the driving
switches at the bottom plate of the C-DAC, and the sampling and tracking switches
with the bootstrap logic.
The sampling switches connect the top plate of the arrays to the common-mode
voltage during the sample phase, while the tracking switches are connected to the
bottom plates of the arrays and track the input signals. The bootstrap clock is gen-
D D D D D D D D D D D D D D D D D D
D 6 6 6 6 7 7 7 7 5 5 5 7 7 7 7 7 D
D 6 6 6 6 5 5 4 4 4 4 5 7 7 7 7 7 D
D 6 6 6 6 5 7 7 3 3 7 7 7 7 7 7 7 D
D 7 7 6 6 5 7 7 1 2 7 7 7 6 6 7 7 D
D 7 7 6 6 7 7 7 2 0 7 7 5 6 6 7 7 D
D 7 7 7 7 7 7 7 3 3 7 7 5 6 6 6 6 D
D 7 7 7 7 7 5 4 4 4 4 5 5 6 6 6 6 D
D 7 7 7 7 7 5 5 5 7 7 7 7 6 6 6 6 D
D D D D D D D D D D D D D D D D D D
Fig. 4.10 Layout placement of the C-DAC for limiting systematic mismatch.
160 μm
SWITCHES R-DAC
BOOTSTRAP LOGIC
200 μm
C-DAC
SWITCHES R-DAC
Fig. 4.11 Layout view of the DAC, including the DAC switches and the bootstrap logic.
erated by the circuit in Fig. 4.12, presented in [11]. During CLK, the capacitor CB
is pre-charged to VDD by M1 and M2 . M3 and M4 tights to ground the output clock
CLKOUT and turn off M8 and M10 , while M5 turns off M7 . When CLK goes high,
M6 turns on M7 which turns on M8 . M8 , together with M9 , sample VIN at the bottom
plate of CB . This boost the top plate of CB to VDD + VIN . M7 provides to the output
CLKOUT this value attenuated by the parasitic capacitance CP . The main contribu-
tion to this parasitic is the one of the bulk parasitic of M7 . In fact, the maximum
voltage experienced by M7 , as well as by M2 , is not VDD , but the top plate of CB ,
which can rise up to 2VDD . For this reason, the bulk of M7 and M2 are connected
to this node. Therefore, there is a tradeoff between the effectiveness of the bootstrap
logic and the maximum sampling speed achievable by the circuit. In this design, a
bigger CB is used for the tracking switch clocks in order to ensure the required lin-
earity in the sampling period. This is not necessary for the sampling switch clock,
as the switch is connected to a constant reference voltage. M4 reduces the VDS and
VGS applied to M3 during the CLK phase, while M10 ensures that the VS G of M7
never exceed VDD .
CLK
M2
M7
M4 M3
CP
CB
M5
CLKOUT
CLK
M6 M10
M8
VIN
M9
CLK M1
CLK
Fig. 4.12 Schematic view of the bootstrap logic.
The area occupied by the C-DAC, the R-DAC, the switches and the bootstrap
logic is 220 x 160 µm2 .
4.3.3 Comparator
The comparator used in the converter is the one in Fig. 4.13. When the clock signal
is low, the nodes D+ and D− are reset to VDD by the couple M3a−b . The two couple
M7a−b and M8a−b reset to ground the latch formed by M4a−b and M5a−b , M6a−b are
open. When the clock signal goes high, a differential current is generated in the
couple M2a−b that discharges the nodes D+ and D− at a rate proportional to IN+
and IN− . As D+ and D− discharge, M8a−b start to provide current to the latch, that
sense the difference between IN+ and IN− and completes the comparison operation
providing the digital output O+ and O− .
This solution provides two main benefits. The first one consists in the separa-
tion between the input and the output nodes which reduces the kickback noise. The
second is the possibility to generate two different tail currents for the input stage
and the output stage. This is done by properly sizing M1 and M6a−b . In this way, it
can be optimised both the speed of the regenerative loop and the noise and offset
characteristics of the differential input pair. The implemented comparator occupies
an area of 15 x 10 µm2 .
4.4 Simulation Results 83
10 μm
M6a M6b
M5a M5b
M7a M7b
O+ O-
M8a M8b
M4a M4b
15 μm
M3a M3b
D+ D-
CLK
IN+ M2a M2b IN-
CLK M1
(a) (b)
Fig. 4.13 Double-tail latch. (a) Schematic view. (b) Layout view.
4.4 Simulation Results
The ADC has been verified at a simulation transistor level, with a post-layout ex-
tracted view, using a 65-nm technology node. Fig. 4.14 shows the post-layout simu-
lated output spectrum (the fft has 1024 points) for an input frequency fin = 2.21 MHz
and a sampling frequency f s = 8 MS/s. The achieved signal-to-noise-and-distortion
ratio (SNDR) is 72 dB, that results in an effective number of bits (ENOB) equal to
11.7 bits. The spurious free dynamic range is limited by a tone at 3.06 MHz with
amplitude -78 dB. The tone is a non-linear intermodulation between the 5th order in-
put harmonic and the 2nd order sampling harmonic. This distortion derives from the
power supply rejection ratio (PSRR) of the comparator. Anyhow, the tone amplitude
is 3 dB below the specifications so it does not introduce an issue.
Fig. 4.15 shows the post-layout noise-tran simulated output spectrum (the fft
has 1024 points) for an input frequency fin = 1.79 MHz and a sampling frequency
f s = 8 MS/s. The SNDR in presence of thermal noise, in a band of 1 GHz, is de-
graded by less than 3 dB, resulting in an ENOB = 11.3 bits. The SFDR is limited
by a tone at 940 KHz with amplitude -78 dB. As expected, the distortion does not
change in the presence of thermal noise. SNDR and SFDR specifications are met
also in noise-tran simulations.
Fig. 4.16 shows the simulated ADC power breakdown. The total power con-
sumption is 200 µW. Main contribution to this are the reference voltages for the
SNDR = 72 dB - SFDR = 78 dB
0
-10
-20
-30
-40
PSD [dB]
-50
-60
-70
-80
-90
-100
0 0.5 1 1.5 2 2.5 3 3.5 4

Frequency [Hz] #10 6
Fig. 4.14 Post-layout simulated output spectrum for fin = 2.21 MHz and f s = 8 MS/s.
SNDR = 69.7 dB - SFDR = 78 dB

0
-10
-20
-30
-40
PSD [dB]
-50
-60
-70
-80
-90
-100
0 0.5 1 1.5 2 2.5 3 3.5 4

Frequency [Hz] #10 6
Fig. 4.15 Post-layout noise-tran simulated output spectrum for fin = 1.8 MHz and f s = 8 MS/s.
DAC (41%), and the digital logic (32%). The rest of the power is consumed by the
input drivers (18%) and the comparator (9%). The input driver power consumption
is estimated, using ideal voltage generators in the simulation setup and considering
an efficiency of 75%.
4.5 Conclusions 85
Comparator
(17.9 μW - 9%) Reference Voltages
Input Buffers (82.1 μW - 41%)
(35.5 μW - 18%)
Digital Logic
(64.5 μW - 32%)
Fig. 4.16 Simulated ADC power breakdown.
4.5 Conclusions
The design of a compact ADC for a transcranial Doppler ultrasound system to mea-
sure cerebral blood flow velocity has been demonstrated. The most area-hungry
block for a standard SAR ADC is usually the capacitive array implementing the
DAC structure. Taking advantage of the post-processing present in the system, the
matching requirements for it were significantly reduced. A resistive and capacitive
structure was used in order to reduce the area occupied by the DAC. An optimum
trade-off between the two sections has been chosen considering the kT/C require-
ments and the resistive string decoder complexity.
The proposed solution proves the feasibility of using SAR ADCs for analog
front-ends in ultrasound system. In fact, a compact and reliable solution can be pro-
vided with very little design effort. This particular design achieves an SNDR = 69.7 dB
at 8 MS/s, while consuming only 200 µW and it occupies 0.04 mm2 . The resulting
figure of merit is 9.9 fJ/conversion-step.
References
1. S. J. Pietrangelo, “An Electronically Steered, Wearable Transcranial Doppler Ultrasound

System”, Massachusetts Institute of Technology, 2013.
2. B. Fotouhi, and D.A. Hodges, “High Resolution A/D Conversion in MOS/LSI,” IEEE J. Solid
State Circuits, vol. 14, no. 6, pp. 920-926, Jun. 1979.
3. G. Promitzer, “A 12-bit Low Power Fully Differential Switched Capacitor Noncalibrating

Successive Approximation ADC with 1MS/s,” IEEE J. Solid State Ciruits, vol.36, no.7,
pp.1138-1143, Jul. 2001.
4. Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R.P. Martins, and F. Maloberti, “Split-SAR
ADCs: Improved Linearity with Power and Speed Optimization”, IEEE Transactions on Very
Large Scale Integration Systems, Vol. 22, No. 2, pp. 372-383, Feb. 2014.
5. W. Guo and S. Mirabbasi, “A Low-Power 10-bit 50-MS/s SAR ADC Using a Parasitic-
Compensated Split-Capacitor DAC”, Proc. of IEEE International Symposium on Circuits and
Systems (ISCAS), pp. 1275-1278, May 2012.
6. S. P. Singh, A. Prabhakar and A. B. Bhattcharyya, “C-2C Ladder Based D/A Converters for
PCM Codecs”, in IEEE Journal of Solid State Circuits, p. 1197-1200, Dec 1987.
7. L. Cong, “Pseudo C-2C ladder-based data converter technique”, IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing, vol. 48, no. 10, pp. 927-929, 2001.
8. X.Y. Tong, Z.M. Zhu, Y.T. Yang and L.X. Liu, “D/A Conversion Networks for High-Resolution
SAR A/D converters,” Electronics Letters, vol. 47, no. 3, pp. 169 - 171 , Feb. 2011.
9. D. Schinkel, E. Mensink, E. Klumperink, E. vanTuijl, andB. Nauta,“A Double-Tail Latch-Type

Voltage Sense Amplifier with 18 ps Setup & Hold Time,” IEEE ISSCC Dig. Tech. Papers, Feb.
2007, pp. 314-315.
10. S.-W. M. Chen and R.W.Brodersen,“A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in
0.13-µm CMOS”, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669 - 2680, Dec. 2006.
References 87
11. M. Dessouky and A. Kaiser, “Input Switch Configuration Suitable for Rail-to-Rail Operation
of Switched Op Amp Circuits,” Electronics Letters, vol. 35, no. 1, pp. 8-10, 1999.
Chapter 5
Conclusions
Interest in SAR ADCs has increased in recent years, as they stand out as a high-
performing solution for multiple applications. Their versatility and scalability per-
fectly match the new trends in data converter research activities. A look at the state-
of-the-art shows how the SAR algorithm is spreading not only as a stand-alone or
time-interleaved architecture, but also as a hybrid solution that further pushes away
the limits of other types of converters, such as pipeline or oversampled ADCs.
Chapter 1 presented a short overview on the most common ADC architectures
and provided an analysis on the evolution of these topologies in the last decades.
As a result of this study, the SAR algorithm appeared to be a very flexible approach
for applications ranging from ultra low-power to ultra high-speed, always maintain-
ing cutting edge figures of merit. A summary of the state-of-the-art of SAR ADCs
proved this to a be a reasonable outcome, showing stunning results from previous
designs.
From this assumption, this thesis attempt was to explore the intrinsic potential
of the SAR algorithm designing and prototyping three different ADCs, designed
for very different applications. In this way, some of the most promising features
of the SAR algorithm were studied: the high efficiency for high-speed applications,
the possibility to merge easily with other architectures to further improve the perfor-
mances of the converter, and the simplicity and compactness for ultrasound systems.
In Chapter 2, the prototype of a high-speed single channel Flash-SAR ADC in
65-nm CMOS process was presented and the experimental results were illustrated.
The achieved measured figure of merit at Nyquist is 86.7 fJ/conv-step with a sam-
pling rate equal to 700 MS/s and a nominal supply voltage of 1.2 V. The use of
a flash approach for the MSBs conversion and a multi-bit per cycle SAR for the
LSBs increases the speed of operation maintaining a very competitive efficiency.
The thresholds generation in the SAR ADC is done by means of a novel resistive
interpolated preamplifier that reduces the power consumption and relaxes the reso-
lution constraints of the comparator. A divider-based phase generator gets rid of the
conventional shift register approach in the SAR ADC, and a dynamic logic mini-
mizes the feedback loop delay of the converter.
89
90 5 Conclusions
In Chapter 3, a battery monitor system was presented. The SAR approach was
used to extend the dynamic range of a first order time-interleaved incremental ADC.
The use of the same ADC for all the channels in the fine step relaxes the matching re-
quirements in the time-interleaved structure, and allows a high-resolution converter
with very simple analog blocks. A HV track & hold with low-voltage logic control
interfaces the A/D with the battery stack, achieving high linearity and low cost. The
battery monitor has a resolution of about 0.2 mV, consuming 3.64 mW with an area
of 1300 x 650 µm2 . All channels are measured in 720 µs. The measured residual
offset is 642.5 µV. The dynamic input range of the system can be as large as 33.6 V,
and the achieved figure of merit is 141.9 dB.
In Chapter 4, the design of a compact ADC for a transcranial Doppler ultra-
sound system to measure cerebral blood flow velocity has been demonstrated. A
very simple approach with a hybrid resistive-capacitive DAC and a self timed logic
was used. This case study proved the effectiveness of the SAR algorithm for fast
prototyping requirements in modern system-oriented projects. In fact, a compact
and reliable solution can be provided with very little design effort using the count-
less techniques proposed by the research community in this field. This particular
design achieves an SNDR = 69.7 dB at 8 MS/s, while consuming only 200 µW and
it occupies 0.04 mm2 . The resulting figure of merit is 9.9 fJ/conversion-step.
The work done during the Ph.D. activity, between University of Pavia and the
Massachusetts Institute of Technology, focused on interface systems for data acqui-
sition applications, especially on the design of high-performance ADCs. This led to
the fabrication and characterisation of two different chips and the design of another
ADC, and the publication of six papers in conferences and journals listed below.
1. D.G. Muratore, A. Akdikmen, E. Bonizzoni, F. Maloberti, U-F. Chio, S.-W. Sin,
R. P. Martins, “An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm
CMOS Technology”, To appear in the Proc. of IEEE European Solid State Cir-
cuits Conference (ESSCIRC), 2016.
2. D. G. Muratore, E. Bonizzoni, S. Verri, F. Maloberti, “High-Resolution Time-

Interleaved 8-Channel ADC for Li-Ion Battery Stack”, IEEE Transactions
on Circuits and Systems - II: Express Briefs, DOI: 10.1109/TCSII.2016.2597358,
2016.
3. D.G. Muratore, E. Bonizzoni, and F. Maloberti, “A Pipeline ADC for Very

High High Conversion Rates”, Proc. of IEEE International Symposium on
Circuits and Systems (ISCAS), pp. 1446 - 1449, 2016.
4. D.G. Muratore, E. Bonizzoni, F. Maloberti, and Carlo Fiocchi, “A Capaci-

tive Sensor Interface for High-Resolution Acquisitions in Hostile Environ-
ments”, Proc. of IEEE Latin American Symposium on Circuits and Systems
(LASCAS), pp. 167-170, 2016.
5. D.G. Muratore, A. Akdikmen, and F. Maloberti, “Very High-Speed CMOS

Comparators for multi-GS/s A/D Converters”, Proc. of IEEE Conference
5 Conclusions 91
on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 240-243,

2015.
6. D.G. Muratore, E. Bonizzoni, and F. Maloberti, “A Split Transconductor

High-Speed SAR ADC”, Proc. of IEEE International Symposium on Circuits
and Systems (ISCAS), pp. 2433-2436, 2015.

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A Study of Successive

Advisor: Prof. Franco Maloberti

First of all I want to thank my advisor Franco Maloberti. He promised me that

2 An 8-b 700 MS/s Flash-SAR ADC with 86.7 fJ/conversion-step in

3 A 14-b 33.6 V DR Extended Range ADC for Battery Monitoring . . . . 51

3.3.2 Operational amplifier with chopping technique . . . . . . . . . . . 60

4 A 200 µW 12-b 8 MS/s SAR ADC for Ultrasound Systems . . . . . . . . . . 71

1.1 Basic block diagram of the full-flash converter. . . . . . . . . . . . . . . . . . . . 3

2.1 Searching algorithm with redundancy. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.12 Comparison between input stages of dynamic latch and

3.1 Battery monitor architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.14 Testing board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.1 Architecture of the transcranial Doppler ultrasound system. [1] . . . . . 72

1.1 Comparison of ADC architectures, [5]. . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 Latches bank connections to preamplifier outputs. . . . . . . . . . . . . . . . . 41

3.1 Performance summary and comparison table. . . . . . . . . . . . . . . . . . . . . 68

4.1 ADC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

1.1 Motivation and Structure of the Thesis

1.2 Data Converter Architectures

1.2.1 Nyquist Rate

1.2.1.1 Flash ADCs

Fig. 1.1 Basic block diagram of the full-flash converter.

1.2.1.2 SAR ADCs

Successive Approximation Converter (ii)

Fig. 1.3 Basic block diagram of the SAR converter.

Fig. 1.4 Charge redistribution implementation.

1.2.1.3 Pipeline ADCs

clk clk clk clk

Fig. 1.5 Basic block diagram of the pipeline converter.

1.2.2 Oversampled ADCs

ENOB = n + 0.5 · log2 (OS R) (1.4)

where OSR is the oversampling ratio.

2fN 2fN 2f’N

B(z) DAC B(z)

[X − Y · B(z)] A(z) + Q = Y (1.5)

whose solution yields

S NRΣ∆,1|dB = 6.02n0 + 1.78 − 5.17 + 9.03log2 (OS R) (1.9)

ENOB = n0 − 0.86 + 1.5log2 (OS R) (1.10)

is to implement the dithering technique. Basically, an auxiliary input that eliminates

1.2.2.2 Incremental ADCs

Instrumentation and measurement applications, such as the readout of bridge trans-

R1−ord = log2 (N − 1) (1.13)

Vin Z-1 Vres Dout

Fig. 1.9 First-order incremental ADC block diagram.

Vin Z-1 Z-1 Vres Dout

Fig. 1.10 Second-order incremental ADC block diagram.

Similarly, the resolution of the second-order structure is described as

1.3 Data Converter Evolution

10k 100k 1M 10M 100M 1G 10G

Table 1.1 Comparison of ADC architectures, [5].

1.4 The State of the Art in SAR ADCs

2 The Walden figure of merit is defined as FoMW,h f = P

1. F. Maloberti, “Data Converters”, Springer, 2007.

3. M. J. M. Pelgrom, “Analog-to-Digital Conversion”, Springer, 2013.

4. E. Bonizzoni, Y. Liu, and F. Maloberti, “Smart-DEM for energy-efficient incremental ADCs”,

11. L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf,

17. B. Verbruggen, M. Iriguchi, J. Craninckx, “A 1.7mW 11b 250MS/s 2x Interleaved Fully

18. A. M. A. Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, J. Lanford, J.

21. Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D.

25. B. Raghavan, A. Varzaghani, L. Rao, H. Park, X. Yang, Z. Huang, Y. Chen, R. Kattamuri,

[X − Y · B(z)] A(z) + Q = Y (1.5)