MCA Ist Semester

2022

PSCSATC 122 COMPUTER ARCHITECTURE AND VLSI DESIGN

PSCSATC 122 COMPUTER ARCHITECTURE AND
VLSI DESIGN

• UNIT – V VHDL COMPONENTS AND TOOLS

Course Objectives & Learning Outcomes
References
 VHDL
CONCURRENT AND SEQUENTIAL CODE
Hardware Description Languages (HDL)
• In software everything is sequential

• Sequence of statements is significant, since

they are executed in that order

• In hardware events are concurrent, so a

software language cannot be used for
describing and simulating hardware.
Hardware Description Languages (HDL)
• HDL is a specialized computer language used to
program electronic and digital logic circuits.
• The structure, operation and design of the circuits
are programmable using HDL. HDL includes a textual
description consisting of operators, expressions,
statements, inputs and outputs.
• Instead of generating a computer executable file, the
HDL compilers provide a gate map. The gate map
obtained is then downloaded to the programming
device to check the operations of the desired circuit.
Hardware Description Languages (HDL)
• The language helps to describe any digital
circuit in the form of structural, behavioral
and gate level and it is found to be an
excellent programming language for FPGAs
and CPLDs.
Hardware Description Languages (HDL)
• Hardware description languages (HDLs) are
extremely important tools for modern digital
designers.
• HDLs are used for both simulation and
synthesis.
• Logic simulation is a powerful way to test a
system on a computer before it is turned into
hardware.
Hardware Description Languages (HDL)
• Logic synthesis converts the HDL code into
digital logic circuits
• describing real hardware, not writing a
computer program
 Advantages of using HDL
• Designs can be described at various levels of abstraction
• Top-Down Approach and hierarchical designs for large projects
• Functional Simulation at early stage in the Design Flow
• Automatic Conversion of HDL Code to Gates
– With user level control, Consistent quality, Fast.
• Early Testing of Various Design Implementations
– Due to fast synthesis, there is a scope for trying different
implementations.
• Design Reuse
– Technology independence, standardization, portability, ease of
maintenance.

All this results in low risk, high convergence, fast time to

market, more money.
 Features of HDLs
• Concurrent Descriptions
• Synchronizing mechanisms between
concurrent flows
• Event Scheduling
• Special object types and data types
• Hierarchy
 HDL
• VHDL,
• Verilog, and
• System Verilog
– They differ from software programming
languages because they include a means of
describing propagation time and signal strengths.
It is not possible to design a complex system on a
chip (SoC) for a mobile device or any other
consumer electronics product without an HDL.
Each of the three HDLs has its own distinct style.
 VHDLs
• VHSIC Hardware Description Language (VHDL)

• The Very High Speed Integrated Circuit (VHSIC)

Program was a United States Department of
Defense (DOD) research program that ran from 1980 to
1990 with mission to research and develop very high-
speed integrated circuits for the United States Armed
Forces.

• VHSIC was launched in 1980. The program led to

advances in integrated circuit materials, lithography,
packaging, testing, and algorithms, and created
numerous computer-aided design (CAD) tools. A well-
known part of the program's contribution is VHDL (VHSIC
Hardware Description Language), a hardware description
language (HDL).
 VHDL
• VHSIC Hardware Description Language (VHDL) is
a hardware description language (HDL) that can
model the behavior and structure of digital
systems at multiple levels of abstraction, ranging
from the system level down to that of logic gates,
for design entry, documentation, and verification
purposes.
• VHDL and Verilog implement register-transfer-
level (RTL) abstractions.
 HDL - IEEE industry standards
• System Verilog was developed to provide an
evolutionary path from VHDL and Verilog to
support the complexities of SoC designs.
– System Verilog includes capabilities for test bench
development and assertion-based formal verification.
– System Verilog, initially known as SUPERLOG.

• All three are IEEE industry standards ––

– VHDL is IEEE 1076-2008,
– Verilog is IEEE 1364-2005 and
– SystemVerilog is IEEE 1800-2012.
 VHDL - two domains
• A VHDL description has two domains:
a sequential domain and a concurrent domain.

• The sequential domain is represented by a process

or subprogram that contains sequential statements.
These statements are executed in the order in which
they appear within the process or subprogram, as in
programming languages.
The concurrent domain is represented by an architecture
that contains processes, concurrent procedure calls,
concurrent signal assignments, and component
instantiations.
 VHDL and Verilog
• VHDL and Verilog are considered general-purpose digital
design languages, while System Verilog represents an
enhanced version of Verilog.
• Each has its own style and characteristics.
– VHDL has roots in the Ada programming language in both
concept and syntax, while
– Verilog’s roots can be tracked back to an early HDL called Hilo
and the C programming language.
• With Verilog and VHDL,
– desired functionality can be represented as a software
program. Model is simulated to check whether the required
outputs are generated.
– Any problems can be corrected in the model, and simulation will
verify the correction.
 VHDL
• VHDL is a rich and strongly typed language,
deterministic and more verbose than Verilog.
As a result, designs written in VHDL are
considered self-documenting. In VHDL there is
no need to do extra coding to convert from
one data type to another.
• VHDL often catches errors missed by Verilog.
VHDL emphasizes unambiguous semantics
and allows portability between tools.
 GHDL
• GHDL is a VHDL compiler that can execute
(simulate) a VHDL program.
• Features of GHDL:
– GHDL directly translates a VHDL file to machine code
– Faster compilation and analysis of code
– Produces a VCD (value change dump) file which can
be viewed with a wave viewer
– GHDL aims at implementing VHDL as defined by IEEE
1076
– It supports most of the 1987 standard and most
features added by the 1993 standard.
ELEMENTS OF VHDL
 VHDL Identifiers
• Identifiers are used to name items in a VHDL
model.
• A basic identifier may contain only
‘A’ to ‘Z’
‘a’ to ‘z’
‘0’ to ‘9’
underline character ‘_’
– must start with a alphabet
– may not end with an underline character
– must not include two successive underline characters
 Data types
Data types
• VHDL supports a variety of data types and operators.
• VHDL is a strongly typed language
• Users can define their own data types and operators in user
defined packages.
• There are three basic object types in VHDL
– Signal - represents interconnections that connect components
and ports
– Variable – used for local storage within a process.
– Constant - a fixed value
• The object type could be a scalar or an array
(uni-dimensional as well as multidimensional )
 BIT LITERAL
• Used to represent value of a digital system
• Values allowed are ‘0’ and ‘1’
• Bit vector literal is expressed as a string of bit
• literals enclosed in double quotes
– eg ‘1’ ,
‘0’,
“1011” ,
X ”7CEF” (hex),
O ”5673” (octal)
– eg signal valid : bit
 BOOLEAN LITERAL
represents true or false value
values allowed are
true(TRUE, True)
false(FALSE, False)

eg:
signal busactive : boolean;
...
busactive <= true;
...
if (busactive and valid = ‘1’) then
data_out <= din;
valid_out <= ‘1’;
end if;
COMPONENTS OF VHDL
 COMPONENTS OF VHDL
• Entity –A design’s interface signals to the external
circuitry.
• Architecture –Describes a design’s behavior and
functionality.
• Configuration –Binds an entity to an architecture when
there are multiple architectures for a single entity.
• Package –Contains frequently used declarations,
constants, functions, procedures, user data types and
components.
• Library –Consists of all the compiled design units like
entities, architectures, packages and configurations.
 ENTITY
• Entity defines a new component , its I/O connections
and related declarations.
• It can be used as a component in other entities after
being compiled into a library.
• Any data type used in an entity must be previously
declared in a standard or user defined package.
• Using components in an entity helps in reducing the
complexity of a design and assists in building a
hierarchical design.
 ENTITY PORTS
Entity port is a signal with a specified data flow
direction which provides an interconnection between
the component and its environment.

Modes of ports -
IN : input Value can be read but not assigned
OUT : output Value can be assigned but not read
INOUT : bi-directional Value can be read and assigned
BUFFER : out port with read capability. It is an output port
and not a bi-directional port.

The assignment of hardware I/O buffers to the ports (push-pull,

tri-state, differential output, etc.) depends on the
implementation and the target technology.
 ENTITY
Syntax
entity entity_name is
[generic generic_name : data_type [:= initial value ]]
[port port_name : port_direction data_type]
[declarations]
[begin
statements]
end entity_name;
Generics provide a means of passing parameters to a block from its
GENERIC from its environment or during component instantiation.
This allows the same entity/architecture to be used by different
designs by changing the generic value (for eg: bus_width 8/16/32)
Entity declarative part
The entity declarative part may contain declaration of
types, subtypes, constants, signals, etc.
These will be visible to all the
– architectures of this entity. But declarations in the
architecture are
– more commonly used.
Entity statement part
– concurrent assertion statement / passive concurrent
procedure call /
– passive process statement. No signal assignment is
allowed here.
 ARCHITECTURE
• An architecture specifies the behavior, function,
interconnections and the relationship between
the inputs and the outputs of an entity.
• An entity can have more than one architecture .
• There can be no architecture without an entity .
• Each architecture is bound to an entity using the
configuration statement .
 ARCHITECTURE
Architectures can have various
abstraction levels and implementations
to facilitate faster design, better
understanding, better performance and
lesser complexity.
 ARCHITECTURE
Syntax -
architecture architecture_name of entity_name is
[declarations]
begin
[statements]
end [ architecture_name ];

Architecture can contain only concurrent statements

 ARCHITECTURE
BEHAVIORAL STYLE

entity my_and is
port (a, b, c : in std_logic; d : out std_logic);
end my_and;

architecture my_and_beh of my_and is

begin
process(a, b, c)
begin
if (a = ‘1’ and b = ‘1’ and c = ‘1’) then
d <= ‘1’; else d <= ‘0’;
end if;
end process;
end my_and_beh;
 VHDL ARCHITECTURES
VHDL architectures can be classified as -
Behavioral
Defines a sequentially described functioning of the
design.
Structural
Defines interconnections between previously defined
components.
Dataflow
A combination of structural and behavioral
architectures .
 CONFIGURATION
• A configuration statement selects one of several
architectures for a single entity. Components
within architectures can also be chosen.
• Configuration can be used for version control
• Configuration is ignored by the synthesizer.
• Unless specified, the last compiled architecture is
used for simulation
• Configuration saves compile time when some
components need substitution in a large design.
 CONFIGURATION
configuration configuration_name of entity_name is
for architecture_name
for instance_name: component_name
use entity
library_name.entity_name(architecture_name);
end for;
end for;
end configuration_name;
 PACKAGE
A package is collection of commonly used subprograms,
data types and constants.

Package saves coding and promotes code reuse.

STANDARD and TEXTIO are provided in the STD library which defines useful
data types and utilities .

Package consists of two parts :

package header :
This defines the contents of a package which is made
visible after the statement
“use library.package_name.all”
package body :

This provides the implementation details of sub programs.

Items declared in the body is not visible to the user of the package .
 LIBRARY
• Library is a collection of compiled VHDL design units .
• Library promotes sharing of compiled designs and
hides the source code from the users .
• VHDL does not support hierarchical (nested) libraries.
• WORK and STD are the default libraries provided by
the language. They need not be explicitly declared.
• All the compiled designs are put into WORK by default
unless specified otherwise.
• Commonly used functions, procedures and user data
types can be compiled into a user defined library for
use in all designs.
 LIBRARY
• Before accessing any unit in a library it needs to
be declared.

Syntax:
STD and WORK need not be declared. Its syntax is

library library_name ;
components declared inside a library can be accessed by
the ‘USE’ statement

use library_name.package_name.item_name ;
use library_name.item_name ;
CONCURRENT VS SEQUENTIAL STATEMENTS

Concurrent statements
– Simple signal assignment statement
– Conditional signal assignment statement
– Selected signal assignment statement

Sequential Statements
– VHDL process
– Sequential signal assignment statement
– Variable assignment statement
– If statement
– Case statement
– Simple for loop statement
 CONCURRENT STATEMENTS
• Intended only for design of Combinational
circuits
• Three purely concurrent statements , they can
only be used outside sequential code ie
outside process or sub-program –
 When
 Select
 Generate
 SEQUENTIAL STATEMENTS
• Used for design of both Combinational and
Sequential circuits
• Four purely sequential statements, they can
only be used inside sequential code–
 If
 Wait
 Loop
 Case
Integrated Synthesis Environment (ISE)
• ISE enables the developer to synthesize
(compile) their designs, perform timing
analysis, examine RTL diagrams, simulate a
design's reaction to different stimuli, and
configure the target device with
the programmer.

• Xilinx is now part of AMD company.

 Xilinx ISE
• Xilinx ISE -
from Xilinx for synthesis and analysis
of HDL designs, which primarily targets
development of embedded firmware for
Xilinx FPGA (field programmable gate
array) and
CPLD (complex programming logic device)
integrated circuit (IC) product families.
 Vivado Design Suite
• Xilinx ISE a discontinued software tool. It is
succeeded by Xilinx Vivado.
• Vivado Design Suite is a software suite
produced by Xilinx for synthesis and analysis
of hardware description language
(HDL) designs, superseding Xilinx ISE with
additional features for system on a
chip development and high-level synthesis.
 SELF
• VHDL simple program
– AND
– OR