VHDL Lectures

Introduction to VHDL
R.B.Ghongade
Lecture 1
VHDL
What is VHDL?
Digital system design using Hardware
Description Language is an established
methodology in EDA
VHDL stands for
VERY HIGH SPEED INTEGRATED CIRCUITS
HARDWARE DESCRIPTION LANUAGE
EDA stands for ELECTRONIC DESIGN AUTOMATION
FEATURES
VHDL is an amalgamation of following
languages
Concurrent language
Sequential Language
Timing Specification
Simulation Language
Test Language
VHDL has got powerful language

constructs
{ifelse}, {withselect} etc
Design hierarchies to create modular

designs
Supports Design Libraries
Facilitates device independent design and
portability
Concurrent Language
Concurrent statements execute at the same time
in parallel as in hardware
Z <= C + X ;
X <= A + B ;
B
+
C
Sequential Language
Sequential statements execute one at a
time in sequence
As the case with any conventional
programming language the sequence of
statements is important
Z <= C + X ;
X <= A + B;
X <= A + B;
Z <= C + X ;
Sequential statements are required to design sequential circuits
Timing Specification
Providing timing attributes in a sequential digital
design is of prime importance since the
operations are synchronized to a common clock
Example:
process
begin
clk <= 0 ;
wait for 20 ns ;
clk <= 1 ;
wait for 12 ns ;
end process ;
20
32
Timing can be specified in a process only
52
64
84
ns
Simulation language
For analyzing a digital design it is
important the design be simulated
Simulation has different flavours
Functional simulation
Post-synthesis simulation
Post- layout simulation
Any HDL should thus be equipped with

simulation capability for verification and
troubleshooting purposes
Test Language
Testbench
It is a part of a VHDL module that generates a
set of test vectors (test inputs) and sends
them to the module being tested
It collects the responses generated by the
module under test and compares them
against a specification of correct results
Thus testbench is required to ensure that the
design is correct and that the module is
operating as desired
Equivalent to checking of logical errors in any conventional programming
language
Testbench use
Test
tst_a
tst_b
tst_c
ABC_testbench.vhd
MODULE UNDER TEST
ABC.vhd
Equivalent to mechanical test jigs used for testing functionality of mass

produced pcbs as in TV sets or motherboards
Design Hierarchy
Hierarchy can be represented using VHDL
Example
A full adder which is the top level module being
composed of three lower level modules that are; half
adder and OR gate
A
B
Cin
HALF
ADDER
SUM
HALF
ADDER
OR
CARRY
Design hierarchy simplifies the design procedure and manageability in case

of complex designs
Design Libraries
Design Unit
It is any block of VHDL code or collection of VHDL
codes that may be independently analyzed and
inserted into a design library
Design Library
It is a storage facility in which analysed VHDL
descriptions are stored for repeated uses
DESIGN UNIT
Design
Library
2
Analyze
5
Simulator
Logic systems
Need for multi-valued logic system
Conventional logic systems have only three values
i.e. 0, 1, Z
Example
Consider the truth-table for AND gate
A
0
0
1
1
0
B
0
1
0
1
Z
Y
0
0
0
1
?
HOW TO RESOLVE THIS CONDITION ?
For this problem a 9-valued logic system

or package was developed that is called
STD_LOGIC_1164 and it is accepted as
IEEE STD 1164-1993
Multi-valued logic
Unknown: value was known but not anymore
Un-initialized: value was never known
High impedance: net has no driver
Drive strengths: handle different output
drivers
Dont care: value is immaterial
Levels of abstraction
Different styles are adopted for writing VHDL
code
Abstraction defines how much detail about the
design is specified in a particular description
Four levels are:
Layout level
Logic level
Register Transfer level
Behavioral level
BEHAVIORAL
RTL
LOGIC
LAYOUT
Layout Level
This is the lowest level and describes the
CMOS layout level design on silicon
Logic Level
Design has information about
Function
Architecture
Technology
Detailed timings
Layout information and analog effects are

ignored
Register Transfer Level

Using HDL every register in the design
and the logic in between is defined
Design contains:
Architecture information
No details of technology
No specification of absolute timing delays
Behavioral Level
Describing function of a design using HDL
without specifying the architecture of
registers
Contains timing information required to
represent a function
Digital design using VHDL

ST ART
(STEP 1)
CREATE A DIGITAL DESIGN
BY
VHDL CODE
SCHEMATIC ENTRY
STATE DIAGRAM
VHDL Entry
(RTL Level)
Active-HDL
Xilinx ISE
Libero IDE
FPGA Advantage
Compilation
Netlist
(Gate Level)
(STEP 2)
COMPILATION
(STEP 3)
FUNCTIONAL SIMULATION
Active-HDL
Modelsim
(STEP 4)
(SPECIFY TARGET DEVICE)
SYNTHESIS
Xilinx XST
Synplify
Leonardo Spectrum
Synthesis
Simulation
Optimization
Optimized Netlist
(Gate Level)
Simulation
Place & route

(STEP 5)
SIMULATION
(TIMING ASPECTS)
Active-HDL
Modelsim
(STEP 6)
HARDWARE
PROGRAMMING
END
Physical device
Vendors providing programmable

devices
Xilinx
Actel
Altera
Cypruss
Quicklogic
Atmel
Triscend
Lattice
Next class
Elements of VHDL
Elements of VHDL
R.B.Ghongade
Lecture 2
Basic building blocks

LIBRARY
DECLARATIONS
ENTITY
BASIC VHDL CODE
ARCHITECTURE
CONFIGURATION
Overview
Library
It is a collection of compiled VHDL units
It enables sharing of compiled designs and
hides the source code from the users
Commonly used functions, procedures and
user data types can be compiled into a user
defined library for use with all designs
Library should be declared before each
entity declaration even if it is in the same
VHDL file
Library
To declare a library (i.e. to make it visible to the
design) two lines of code are needed , one
containing name of the library, the other a use
clause
A library structure can be as follows:
LIBRARY
PACKAGE
FUNCTIONS
PROCEDURES
TYPES
CONSTANTS
COMPONENTS
Library syntax
LIBRARY library_name ;
USE library_name.package_name.package_parts ;
Example
LIBRARY IEEE ;
-- semicolon indicates
USE IEEE.std_logic_1164.all ; -- end of statement or
-- declaration
LIBRARY work ;
-- double dash (--)
-- indicates a comment
USE work.all ;
Library details
IEEE.MATH_COMPLEX.all
This package defines a standard for designers

to use in describing VHDL models that make
use of common COMPLEX constants and
common COMPLEX mathematical functions and
operators.
IEEE.MATH_REAL.all

to use in describing VHDL models that make
use of common REAL constants and common
REAL elementary mathematical functions.
IEEE.NUMERIC_BIT.all
This package defines numeric types and

arithmetic functions for use with synthesis tools.
Two numeric types are defined:
-- UNSIGNED: represents an UNSIGNED
number in vector form
-- SIGNED: represents a SIGNED number in
vector form
The base element type is type BIT.
Library details
IEEE.NUMERIC_STD.alll
This package defines numeric types and

arithmetic functions for use with synthesis tools.
Two numeric types are defined:
-- UNSIGNED: represents UNSIGNED number in
vector form
-- SIGNED: represents a SIGNED number in
vector form
-- The base element type is type STD_LOGIC.
IEEE.STD_LOGIC_1164.all

to use in describing the interconnection data
types used in VHDL modeling.
Defines multi-value logic types and related
functions.
IEEE.STD_LOGIC_ARITH.all
This package defines a set of arithmetic,

conversion, and comparison functions
for SIGNED, UNSIGNED, SMALL_INT,
INTEGER, STD_ULOGIC, STD_LOGIC, and
STD_LOGIC_VECTOR.
Library details
IEEE.STD_LOGIC_ARITH.all
This package defines a set of arithmetic,

conversion, and comparison functions for
SIGNED, UNSIGNED, SMALL_INT,
INTEGER, STD_ULOGIC, STD_LOGIC,
and
STD_LOGIC_VECTOR. .
IEEE.STD_LOGIC_MISC.alll
This package defines supplemental types,

subtypes, constants, and functions for the
Std_logic_1164 Package.
IEEE.STD_LOGIC_SIGNED.all
This package defines a set of signed

arithmetic, conversion, and comparison
functions for STD_LOGIC_VECTOR.
IEEE.STD_LOGIC_TEXTIO.all
This package overloads the standard

TEXTIO procedures READ and WRITE.
IEEE.STD_LOGIC_UNSIGNED.all This package defines a set of unsigned

arithmetic, conversion and comparison
functions for STD_LOGIC_VECTOR.
Entity
It is the designs interface to the external
circuitry
Equivalent to pinout /package of an IC
VHDL design must include one and only one
entity per module
It can be used as a component in other
entities after being compiled into a library
Entity declaration
Defines the input and output ports of the design
Name of the entity can be anything other than
the reserved VHDL word
Each port in the port list must be allotted:
a name ( should be self-explanatory that provides
information about its function
data flow direction or mode
a type
Ports should be well documented with

comments at the end of line providing additional
information about the signal
Entity syntax
entity entity_name is
port ( port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ) ;
end entity_name ;
Modes
Ports in the portlist have modes which
indicate the driver direction
Mode also indicates whether or not the
port can be read from within the entity
Four modes are available:
Mode IN
Mode OUT
Mode INOUT
Mode BUFFER
Mode IN
Value can be read from but not assigned to (by
the entity)
Port signal A
port ( A : in std_logic ) ;
Drivers reside
outside the entity
ENTITY
Mode OUT
Value can be assigned to but not read from (by
the entity)
port ( B : out std_logic ) ;
Port signal B
Drivers reside
inside the entity
ENTITY
Mode INOUT
Bi-directional , value can be assigned to as well
as read from (by the entity)
Port signal C
port ( C : inout std_logic ) ;
Drivers reside both

inside and
outside the entity
ENTITY
Mode BUFFER
Output port with internal read capability
Drivers reside
inside the entity
Port signal D
port ( D : buffer std_logic ) ;
ENTITY
DO NOT USE UNLESS REQUIRED
Signal can be read inside the entity
Entity example
entity and_gate is
port ( 1A , 2A , 3A, 4A : in std_logic ;
1B , 2B , 3B, 4B : in std_logic ;
1Y , 2Y , 3Y, 4Y : out std_logic ) ;
end and_gate ;
1
2
3
4
5
6
7
1A
VCC
1B
4B
1Y
4A
2A
4Y
2B
3B
2Y
3A
GND
3Y
14
13
12
11
10
9
8
Entity example
entity ALU is
port ( In1 : in std_logic_vector ( 3 downto 0) ; -- 1st operand
In2 ; in std_logic_vector ( 3 downto 0) ; -- 2nd operand
Opsel : in std_logic_vector ( 3 downto 0) ; -- opn select
Cin : in std_logic ;
Mode : in std_logic ;
Result : out std_logic_vector ( 3 downto 0 ) ;
Cout : out std_logic ;
Equal : out std_logic ) ;
end ALU ;
In1
In2
Op
sel
Mode
Cout
Cin
ALU
Result
Equal
Architecture
It specifies
Behaviour
Function
Relationship between inputs and outputs of an entity
Syntax
architecture achitecture_name of entity_name is
[declarations]
-- optional
begin
code
-- concurrent statements only
end achitecture_name ;
Architecture can contain only concurrent

statements
A design can be described in an
architecture using various levels of
abstraction
An entity can have more than one
architectures since a function can be
implemented in a number of ways
There can be no architecture without an
entity
Architectural bodies
Behavioural
It is the high-level description
It contains a set of assignment statements to represent
behaviour
No need to focus on the gate-level implementation of a design
Example:
architecture behave of and_gate is
begin
process ( a, b )
if a=1 and b=1 then
c <= 1 ;
else
c <=0 ;
end if ;
end process ;
end behave ;
Dataflow
It uses concurrent signal assignment
statements
Example:
architecture dataflow of and_gate is
begin
c<= a and b ;
end dataflow ;
Structural
Components from libraries are connected
together
Designs are hierarchical
each component can be individually simulated
it makes use of component instantiation
A
B
Cin
HALF
ADDER
SUM
HALF
ADDER
OR
CARRY
Configuration
Since a number of architectures can exist
for an entity , using configuration
statement we can bind a particular
architecture to the entity
Syntax
configuration CONFIGURATION_NAME of ENTITY_NAME is
for ARCHITECTURE_NAME
end for;
end CONFIGURATION_NAME;
Next class
Language elements
Language Elements I
R.B.Ghongade
Lecture 3
VHDL is a strongly typed language

Designers have to declare the type before
using it
VHDL is not case sensitive ( but avoid

mixed cases as a good programming
practice)
VHDL supports a wide variety of data
types and operators
OBJECTS
OPERATORS
AGGREGATES
Objects
They are used to represent and store the
data in the design being described
Object contains a value of specific type
Class
SIGNAL
Object
COUNT
Data type
: INTEGER
This results in an object called COUNT that holds

INTEGER value that belongs to class SIGNAL
The name given to the object is called as

identifier
Do not use reserved words as identifiers
Each object has a data type and class

Class indicates how the object is used in the
module and what can be done with that object
Type indicates what type of data the object
contains
Each object belongs to one of the following class:
CONSTANT
SIGNAL
VARIABLE
CLASS
CONSTANT
SIGNAL
VARIABLE
Data Types
In order to write VHDL code efficiently it is
necessary to study the specification and use of
data types
Following are the categories of data types:
Pre-defined
Used defined
Subtypes
Arrays
Port arrays
Records
Signed and unsigned
Pre-defined data types

Specified by IEEE 1076 and IEEE 1164
Package
Library Type/Functions
standard
std
BIT, BOOLEAN,
INTEGER, REAL
std_logic_1164
ieee
STD_LOGIC,
STD_ULOGIC
std_logic_arith
ieee
std_logic_signed
std_logic_unsigned
ieee
ieee
SIGNED, UNSIGNED /
data conversion functions
Functions that allow
operations with
STD_LOGIC_VECTOR
BIT (and BIT_VECTOR): 2 level logic (0, 1)
Examples:
SIGNAL X : BIT ;
SIGNAL Y : BIT_VECTOR (3 downto 0);
SIGNAL W : BIT_VECTOR (0 to 7);
X is declared
as a onedigit SIGNAL
of type BIT
Y is 4-bit
vector,
leftmost bit
is MSB
W is 8-bit
vector,
rightmost bit
is MSB
To assign a value to the signal use the

operator < =
Assignment examples:
X <= 1 ;
X is a single bit SIGNAL whose value is 1

Note that single quotes are used for a single bit
Y <= 0111 ;
W <= 01110001 ;
Y is a 4- bit SIGNAL whose value

is 0111 . Note that double
quotes are used for vectors
W is an 8- bit SIGNAL whose
value is 0111001 . MSB is 1
STD_LOGIC (and STD_LOGIC_VECTOR):

8 valued logic (introduced in IEEE 1164 standard)
Symbol
X
0
1
Z
W
L
H
-
Description
Remark
Forcing unknown Synthesizable unknown
Synthesizable logic 0
Forcing low
Synthesizable logic 1
Forcing high
High impedance Synthesizable tri-state buffer
Weak unknown
Weak low
Weak high
Dont care
Examples:
SIGNAL X : STD_LOGIC ;
X is declared as a one-digit
(scalar) SIGNAL of type
STD_LOGIC
SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0);
Y is 4-bit
vector, leftmost
bit is MSB
for (optional)
SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0) : = 0001 initial value use
:=
Most of std_logic levels are intended for simulation

only. However 0, 1 and Z are synthesizable with
no restrictions
With respect to
weak values, they
are resolved in favour
of the forcing values
in multiple-driven
nodes. If any two
std_logic signals are
connected top the
same node, then
conflicting logic levels
are resolved by using
the shown table
X 0 1 Z WL H X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z WL H Z
WX 0 1 W WWWX
L X 0 1 L WL WX
H X 0 1 H WWH X
-
X X X X X X X X
The STD_ULOGIC has 9 valued logic levels : additional

value is U for Un-resolved or Un-initialized
Other types
BOOLEAN
TRUE, FALSE
INTEGER
32-bit integers (from - 2,147,483,647 to +

2,147,483,647
NATURAL
Non-negative numbers (from 0 to

2,147,483,647
REAL
Real numbers (from -1.0E-38 to +1.0E38)
Physical
literals
Used to inform physical quantities like , time,

voltage etc. Useful for simulation but not
synthesizable
Character
literals
SIGNED,
UNSIGNED
Single ASCII character or a string of such

characters. Not synthesizable
They have appearance of
STD_LOGIC_VECTOR, but accept arithmetic
operations which are typical of INTEGER data
type
User defined data types

VHDL allows user defined data types
Two categories of this data type are:
Integer
Enumerated
User defined integer type

TYPE my_integer IS RANGE -32 to +32 ;
TYPE student_grade IS RANGE 0 to 100 ;
User defined enumerated type

TYPE my_logic IS (0, 1, Z );
TYPE my_state IS ( idle, forward, backward, stop) ;
An enumerated type, typically used
in state machines
The encoding of enumerated types is done

sequentially and automatically
Since here there are 4 states only two bits
are required hence 00 is assigned to first
state ( idle), 01 to second state (forward)
and so on.
Subtypes
A SUBTYPE is a TYPE with a constraint
Though operations between data of
different types are not allowed, they are
allowed between the subtype and its
corresponding base type
SUBTYPE sub_state IS my_state RANGE idle to backward ;
This means that the subtype

sub_state =(idle, forward, backward)
Arrays
Arrays are collections of objects of same type
Can be 1-dimensional, 2-dimensionl or
1D X 1D
Higher dimensional arrays are possible but not
synthesizable
0
Scalar
0 1 0 0
1D
1D x 1D
1 1 0 0
1 0 1 0
1 1 0 1
0 1 0 0
2D data array
Array syntax
To specify an array :
TYPE type_name IS ARRAY (specification) OF data_type ;
To use an array :
SIGNAL signal_name : type_name [:= initial_value]
Example : 1D x 1D array
We want to build an array containing 4
vectors, each of size 8 bits
we will call each vector as row and the
complete array as matrix
TYPE row IS ARRAY (7 downto 0 ) OF STD_LOGIC ;
TYPE matrix IS ARRAY (3 downto 0 ) OF row ;
SIGNAL X : matrix ;
1D x 1D SIGNAL
Example : 2D array
This array will be created with scalars only
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0 ) OF STD_LOGIC ;
L
M
ROWS
COLUMNS
Port Arrays
In the specification of the input or output
pins (PORTS) of a circuit (which is made in
the ENTITY), we might need to specify the
ports as arrays of vectors.
Since TYPE declarations are not allowed
in an ENTITY, the solution is to declare
user-defined data types in a PACKAGE,
which will then be visible to the whole
design (thus including the ENTITY)
------- Package: -------------------------LIBRARY ieee;

USE ieee.std_logic_1164.all;
---------------------------PACKAGE my_data_types IS
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR(7 DOWNTO 0);
END my_data_types;
-------------------------------------------------- Main code: ------------------------LIBRARY ieee;
USE work.my_data_types.all; -- user-defined package
--------------------------ENTITY mux IS
PORT (inp: IN VECTOR_ARRAY (0 TO 3);
... );
END mux;
... ;
--------------------------------------------
As can be seen in the example above, a userdefined data type, called vector_array,was
created, which can contain an indefinite number
of vectors of size eight bits each (NATURAL
RANGE <> signifies that the range is not fixed,
with the only restriction that it must fall within the
NATURAL range, which goes from 0 to
+2,147,483,647)
The data type was saved in a PACKAGE called
my_data_types, and later used in an ENTITY to
specify a PORT called inp
Notice in the main code the inclusion of an
additional USE clause to make the user-defined
package my_data_types visible to the design.
Records
Records are similar to arrays, with the only
difference that they contain objects of
different types.
TYPE birthday IS RECORD
day: INTEGER RANGE 1 TO 31;
month: month_name;
END RECORD;
Signed and Unsigned data types

These types are defined in the
std_logic_arith package of the ieee library
Examples:
SIGNAL x: SIGNED (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3);
An UNSIGNED value is a number never lower

than zero. For example, 0101
represents the decimal 5, while 1101 signifies
13.
If type SIGNED is used instead, the value can
be positive or negative (in twos complement
format). Therefore,0101 would represent the
decimal 5, while 1101 would mean 3.
To use SIGNED or UNSIGNED data types, the
std_logic_arith package, of the ieee library, must
be declared
Next class
Language Elements II
Language Elements II
R.B.Ghongade
Lecture 4
Operators
VHDL provides several kinds of predefined operators
Assignment operators
Logical operators
Arithmetic operators
Relational operators
Shift operators
Concatenation operators
Assignment operators
Are used to assign values to signals, variables,
and constants.
<=
:=
=>
Used to assign a value to a SIGNAL

Used to assign a value to a
VARIABLE, CONSTANT, or
GENERIC
Used also for establishing initial values
Used to assign values to individual
vector elements or with OTHERS
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
Then the following assignments are legal:
x <= '1';
-- '1' is assigned to SIGNAL x using "<="
y := "0000"; -- "0000" is assigned to VARIABLE y using
--":="
w <= "10000000"; -- LSB is '1', the others are '0'
w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others
-- are '0'
Logical operators
Used to perform logical operations.
The data must be of type:
BIT, STD_LOGIC
STD_ULOGIC
BIT_VECTOR
STD_LOGIC_VECTOR
STD_ULOGIC_VECTOR
The logical operators

are:
NOT
AND
OR
NAND
NOR
XOR
XNOR
The NOT
operator has
precedence
over the
others
Examples:
y <= NOT a AND b; -- (a'.b)
y <= NOT (a AND b); -- (a.b)'
y <= a NAND b; -- (a.b)'
Arithmetic operators
Used to perform arithmetic operations. The data
can be of type INTEGER, SIGNED, UNSIGNED,
or REAL (the last cannot be synthesized
directly).
Also, if the std_logic_signed or the
std_logic_unsigned package of the ieee library is
used, then STD_LOGIC_VECTOR can also be
employed directly in addition and subtraction
operations
+
*
/
**
MOD
REM
ABS
( Addition)
(Subtraction)
(Multiplication)
(Division)
(Exponentiation)
( Modulus)
( Remainder)
( Absolute value)
For mod, rem, abs , there

generally is little or no
synthesis support
There are no synthesis restrictions regarding addition and

subtraction, and the same is generally true for multiplication
For division, only power of two dividers (shift operation) are
allowed
For exponentiation, only static values of base and exponent
are accepted
Regarding the mod and rem operators, y mod x returns the
remainder of y/x with the signal of x, while y rem x returns the
remainder of y/x with the signal of y
Finally, abs returns the absolute value
Comparison operators
=
/=
<
>
<=
>=
Equal to
Not equal to
Less than
Greater than
Less than or equal to
Greater than or equal to
Also called RELATIONAL

operators
Shift operators
sll
srl
sla
sra
ror
rol
shift left logical

shift right logical
shift left arithmetic
shift right arithmetic
rotate left logical
rotate right logical
LOGICAL
ARITHMETIC
ROTATE
LOGICAL
SHIFTING
0
ARITHMETIC SHIFTING
(retains sign bit)
ROTATE
Concatenation operator
&
Concatenation
Operands can be one-dimensional array type

or element type
& works on vectors only
Example:
SIGNAL
SIGNAL
BEGIN
b <=
a <=
. . .
a : STD_LOGIC_VECTOR ( 5 DOWNTO 0 ) ;
b,c,d : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;
0 & c(1)
c & d ;
& d(2) ;
Operator summary
Operator type
Operators
Data types
NOT, AND, AND

OR, NOR, XOR,
XNOR
BIT, BIT_VECTOR, STD_LOGIC,

STD_LOGIC_VECTOR, STD_ULOGIC,
STD_ULOGIC_VECTOR
Arithmetic
+, -,*,/,**
(mod, rem , abs)
INTEGER, SIGNED, UNSIGNED
Comparison
=, /=, <, >, <=, >=
All above
Shift
sll, srl, sla, sra,

rol, ror
BIT_VECTOR
Concatenation
&, ( , , , )
Same as for logical operators, plus

SIGNED and UNSIGNED
Logical
Operator overloading
Operators can be user-defined
Let us consider the pre-defined arithmetic
operators seen earlier (+,- , *, /, etc.). They
specify arithmetic operations between data
of certain types (INTEGER, for example)
For instance, the pre-defined + operator
does not allow addition between data of
type BIT.
We can define our own operators, using
the same name as the pre-defined ones
For example, we could use + to indicate

a new kind of addition, this time between
values of type BIT_VECTOR. This
technique is called operator overloading
Example: Consider that we want to add an
integer to a binary 1-bit number. Then the
following FUNCTION could be used
FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS
BEGIN
IF (b='1') THEN RETURN a+1;
ELSE RETURN a;
END IF;
END "+";
A call to the function above could thus be the

following:
SIGNAL inp1, outp: INTEGER RANGE 0 TO
15;
SIGNAL inp2: BIT;
(...)
outp <= 3 + inp1 + inp2;
(...)
In outp<=3+inp1+inp2;, the first + is the predefined addition operator (adds two integers),
while the second is the overloaded user-defined
addition operator (adds an integer and a bit).
Aggregates
It assigns values to elements of an array
a <= (OTHERS => 0 ) ;
a <= 0000 ;
We can assign values to some bits in a

vector and use OTHERS clause to assign
default values to remaining bits
a <= (0 => 1, 2 => 1, OTHERS => 0 ) ;
is equivalent to
a <= 00101 ;
Useful when we are

dealing with large vectors
Classes re-visited
Each object has a data type and class
Class indicates how the object is used in the
module and what can be done with that object
Type indicates what type of data the object
contains
Each object belongs to one of the following class:
CONSTANT
CLASS
SIGNAL
VARIABLE
CONSTANT
SIGNAL
VARIABLE
Constants
These are identifiers with fixed values
The value is assigned only once when
declared
Values cannot be changed during
simulation
CONSTANT bus_width : INTEGER :=16 ;
CONSTANT CLK_PERIOD : TIME :=15 ns ;
Constants make the design description

more readable
Design changed at later time becomes
easy
Signals
Example:
architecture and_gate of myand is
signal TEMP : STD_LOGIC ;
begin
U1 : AND2 portmap ( a, b, TEMP ) ;
U2 : AND2 portmap (TEMP, c , d ) ;
Equivalent to wires
within a circuit
end and_gate ;
TEMP
a
b
AND2
d
c
AND2
Thus signals are used :

to connect design entities together and
communicate changes in values within a
design
instead of INOUT mode
Each signal has a history of values i.e.

they hold a list of values which include
current value of the signal and a set of
possible future values that can appear on
the signal
Computed value is assigned to signal after
specified delay called DELTA DELAY
Variables
These are objects with single current
value
They are used to store the intermediate
values between the sequential statements
Variable assignment occurs immediately
Variables can be declared and used inside
the process statement only. But they retain
their value throughout the entire simulation
Example :
process ( a )
variable count : INTEGER : = 1 ;
begin
count : = count+ 1 ;
end process ;
count contains the total

number of events that
occurred on signal a
Next class
Language elements III
Language Elements III

R.B.Ghongade
Lecture 7
Attributes
An attribute is data that are attached to VHDL
objects or predefined data about VHDL objects
Examples are the current drive capability of a
buffer or the maximum operating temperature of
the device
Types are
Data Attributes
Signal Attributes
User-defined Attributes
Data Attributes
The pre-defined, synthesizable data attributes
are the following:
dLOW
: Returns lower array index
dHIGH
: Returns upper array index
dLEFT
: Returns leftmost array index
dRIGHT
: Returns rightmost array index
dLENGTH : Returns vector size
dRANGE
: Returns vector range
dREVERSE_RANGE: Returns vector range
in reverse order
Example
Consider the following signal:
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
Then:
d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0,
d'LENGTH=8, d'RANGE=(7 downto 0),
d'REVERSE_RANGE=(0 to 7)
If the signal is of enumerated type, then:

dVAL(pos) : Returns value in the position
specified
dPOS(value) : Returns position of the
value specified
dLEFTOF(value) : Returns value in the
position to the left of the value specified
dVAL(row, column) : Returns value in the
position specified; etc
There is little or no synthesis support for
enumerated data type attributes
Signal Attributes
Let us consider a signal s
Then:
sEVENT
: Returns true when an event occurs
on s
sSTABLE
: Returns true if no event has
occurred on s
sACTIVE
: Returns true if s = 1
sQUIET <time> : Returns true if no event has
occurred during the time specified
sLAST_EVENT : Returns the time elapsed since last
event
sLAST_ACTIVE: Returns the time elapsed since
last s=1
sLAST_VALUE : Returns the value of s before the
last event; etc.
Example
All four assignments shown below are synthesizable
and equivalent. They return TRUE when an event (a
change) occurs on clk, AND if such event is upward
(in other words, when a rising edge occurs on clk)
IF (clk'EVENT AND clk='1')... -- EVENT attribute
-- used with IF
IF (NOT clk'STABLE AND clk='1')... -- STABLE
--attribute used
-- with IF
WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT
--attribute used
-- with WAIT
IF RISING_EDGE(clk)... -- call to a function
User-defined Attributes
VHDL also allows the construction of user-defined
attributes
To employ a user-defined attribute, it must be
declared and specified
Attribute Declaration:
ATTRIBUTE attribute_name: attribute_type
Attribute Specification:
ATTRIBUTE attribute_name OF target_name: class IS value;
where:
attribute_type: any data type (BIT, INTEGER, STD_LOGIC_VECTOR, etc.)
class: TYPE, SIGNAL, FUNCTION, etc.
value: 0, 27, 00 11 10 01, etc.
Example
ATTRIBUTE number_of_inputs: INTEGER;
ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3;
...
inputs <= nand3'number_of_pins; -- attribute call,
-- returns 3
Generics
As the name suggests, GENERIC is a way
of specifying a generic parameter
a static parameter that can be easily
modified and adapted to different
applications
The purpose is to make the code more
flexible and reusable
must be declared in the ENTITY
More than one GENERIC parameter can
be specified in an ENTITY
Syntax
GENERIC (parameter_name : parameter_type := parameter_value);
Example
The GENERIC statement below specifies a parameter called n, of type
INTEGER, whose default value is 8. Therefore, whenever n is found in
the ENTITY itself or in the ARCHITECTURE (one or more) that follows,
its value will be assumed to be 8
ENTITY my_entity IS
GENERIC (n : INTEGER := 8; vector: BIT_VECTOR := "00001111");
PORT (...);
END my_entity;
ARCHITECTURE my_architecture OF my_entity IS
...
END my_architecture;
Example
ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
....
Delays in VHDL
In VHDL, there are three types of delay
that are encountered
Inertial delay
Transport delay
Delta delay
Inertial Delay
Inertial delay is the default in VHDL
Behaves similarly to the actual device
Output signal of the device has inertia,
which must be overcome for the signal to
change value
The inertial delay model is by far the most
commonly used in all currently available
simulators
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY buf IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END buf;
ARCHITECTURE buf OF buf IS
BEGIN
b <= a AFTER 20 ns;
END buf;
Due to inertial delay pulse is

swallowed up
Inertial delay prevents prolific propagation of

spikes throughout the circuit
Transport Delay
It represents a wire delay in which any
pulse, no matter how small, is propagated
to the output signal delayed by the delay
value specified
Especially useful for modeling delay line
devices, wire delays on a PCB, and path
delays on an ASIC
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END delay_line;
ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;
Pulse is simply delayed
Delta delay
These are used since the PC that
processes and simulates a concurrent
phenomenon is basically a sequential
machine
The simulation program mimics
concurrency by scheduling events in some
order
Simulation deltas are used to order some
types of events during a simulation
Specifically, zero delay events must be
ordered to produce consistent results
Circuit that shows the difference!

A
Assumptions
Zero delay components
CLK=1
A=1
E
CLK
B
DFF
F
CLK
Q'
Problem when no delta delay concept is used

1) A becomes 0
A
A
2) Evaluate inverter
3) B <= 1
4) Evaluate AND with C=1
E
E
CLK
CLK
B
B
DFF
DFF
5) D<=1
F
C
C
D
D
Q
Q
CLK
CLK
Q'
Q'
6) Evaluate NAND
7) C<=0
8) Evaluate AND
9) D<=0
Unwanted D assertion
Problem when no delta delay concept is used

A
1) A becomes 0
2) Evaluate inverter
3) B <= 1
E
CLK
B
DFF
4) Evaluate NAND
FF
CLK
Q'
5) C<=0
6) Evaluate AND
7) D<=0
Delta delay use

10 ns
Delta 1
A<=0
Evaluate inverter
Delta 2
B<=0
Evaluate AND
Evaluate NAND
Delta 3
D<= 1
C <=0
Evaluate AND
Delta 4
D<= 0
11 ns
To summarize, simulation deltas are

an infinitesimal amount of time
used as a synchronization
mechanism when 0 delay events are
present.
Concurrent Statements
and
Constructs
Combinational vs. Sequential Logic

The output of the circuit
depends solely on the
current inputs
Output does depend on

previous inputs hence
storage elements are
required
input
output
Combinational Logic
input
Combinational Logic
output
Present
State
Next
State
Storage
Elements
Concurrent Code
Consider the following
statement:
X=X+Y;
In conventional software
X and Y are register
locations hence contents
of X and Y are added and
stored in X
Register X
Register Y
Difference in VHDL
In VHDL the same statement will mean a
feedback in a purely combinational logic which is
invalid
VHDL code is inherently concurrent (parallel)

Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential
Concurrent code is also called dataflow code
Order does not matter
We can only build combinational logic circuits
with concurrent code
Concurrent assignment produces one driver for
each assignment statement
a
z <= a;
Multiple driver assignment

architecture ABC of XYZ is
signal z,a,b,c,d : std_logic ;
begin
z <= a and b;
z <= c and d; Care has to be taken
to handle such conditions
. . .
with a hi-impedance state
a
b
?
c
d
Next Class
Concurrent constructs
Digital Hardware Revision

R.B.Ghongade
Lecture 6, 7
Digital Logic
Binary system -- 0 & 1, LOW & HIGH, negated
and asserted.
Basic building blocks -- AND, OR, NOT
A1
B1
Z1
A2
B2
Z2
X
Y
XY
X Y + X Y Z
Y
Z
X Y Z
Many representations of digital logic

Transistor-level
circuit diagrams
VCC
B
S
Gate symbols (for simple elements)
Truth tables
T a b le 1 - 1
Truth table for the
multiplexer function.
Logic diagrams
A
SN
ASN
Z
SB
Prepackaged building blocks, e.g. multiplexer

74x157
15
S
A
B
G
S
1A
3
1B
2
5
6
11
10
14
13
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
12
Copyright 2000 by Prentice Hall, Inc.

Digital Design Principles and Practices, 3/e
Equations: Z = S A + S B
module chap1mux
title 'Two-input multiplexer example'
CHAP1MUX device 'P16V8'
Various hardware
description
languages
ABEL
A, B, S
Z
pin 1, 2, 3;
pin 13 istype 'com';
equations
WHEN S == 0 THEN Z = A;
ELSE Z = B;
end chap1mux
Table 1-3
VHDL
VHDL
program for
the multiplexer.
library IEEE;
use IEEE.std_logic_1164.all;
entity Vchap1mux is
port ( A, B, S: in STD_LOGIC;
Z:
out STD_LOGIC );
end Vchap1mux;
Well start with

gates and work
our way up
architecture Vchap1mux_arch of Vchap1mux is

begin
Z <= A when S = ?0? else B;
end Vchap1mux_arch;
Logic levels
Undefined region
is inherent
digital, not analog
amplification,
weak => strong
5.0 V
Logic 1 (HIGH)
3.5 V
undefined
logic level
1.5 V
Logic 0 (LOW)
0.0 V

Switching threshold varies
with
voltage,
Digital Design
Principles
and Practices, temp,
3/e
process
need noise margin
The more you push the technology, the more

analog it becomes.
Logic voltage levels decreasing with process
5 -> 3.3 -> 2.5 -> 1.8 V
MOS Transistors
Voltage-controlled resistance
VIN

Vgs 3/e
Digital Design Principles and Practices,
+
PMOS
gate
source
drain
Voltage-controlled resistance:
decrease Vgs ==> decrease Rds
Note: normally, Vgs 0

NMOS
drain
gate
+
source
Vgs
Voltage-controlled resistance:
increase Vgs ==> decrease Rds
Note: normally, Vgs 0

CMOS Inverter
Switch model
(a)
VIN = L
VDD = +5.0 V
(b)
VOUT = H
VIN = H

VDD = +5.0 V
VOUT = L
Alternate transistor symbols

VDD = +5.0 V
Q2
on when
VIN is low
(p-channel)
VOUT
Q1
VIN
(n-channel)

on when
VIN is high
CMOS Gate Characteristics

No DC current flow into MOS gate terminal
However gate has capacitance ==> current
required for switching (CV2f power)
No current in output structure,

except during switching
Both transistors partially on
Power consumption related
to frequency
Slow input-signal rise times
==> more power
Symmetric output structure

==> equally strong drive in
LOW and HIGH states
VDD = +5.0 V
Q2
on wh
VIN is
(p-channel)
VOUT
Q1
VIN
(n-channel)

on wh
VIN is
CMOS NAND Gates

Use 2n transistors for n-input gate
CMOS NAND -- switch model

VDD
(a)
(b)
(c)
(b)
(c)
Z=H
L
Z=H
2000 by Prentice Hall, Inc.

gn Principles and Practices, 3/e
VDD
DD
VDD
Z=H
L
A
A == H
L
A=H
B
B == H
L
B
B == H
L


CMOS NAND -- more inputs (3)
Inherent inversion.
Non-inverting buffer:
2-input AND gate:

VDD
(a)
(b)
Q2
Q4
Z
A
Q1
Q3
A B
Q1
Q2
Q3
Q4
Q5
Q6 Z
L
L
H
H
off
off
on
on
on
on
off
off
off
on
off
on
on
off
on
off
on
on
on
off
off
off
off
on
Q6
Q5
(c)
L
H
L
H
A
B
L
L
L
H

CMOS NOR Gates

Like NAND -- 2n transistors for n-input gate
VDD
(a)
(b)
Q2
Q4
A B
Q1
Q2
Q3
Q4
L
L
H
H
off
off
on
on
on
on
off
off
off
on
off
on
on
off
on
off
H
L
L
L
L
H
L
H
Q1
Q3
(c)
A
B

NAND vs. NOR

For a given silicon area, PMOS transistors are
weaker than NMOS transistors.
NAND
(a)
NOR
(b)
Q2
Q4
Z
A
VDD
(a) 2000 by Prentice Hall, Inc.

Copyright
VDD
A B
A
Q1
Q2
Q3
Q4 Q2
Z
L
L
H
H
off
off
B
on
on
on
on
off
off
off
on
off
on
on H
off Q4
H
on H
off L
L
H
L
H
A B
Q1
Q2
L
L
H
H
off
off
on
on
on
on
off
off
o
o
o
o
L
H
L
H
Q1
Q1
(b)
Q3
(c)
A
B
Q3
A
B
(c)
Copyright 2000 by Pren

Digital Design Principles and
For a given Si area , n-channel transistor has lower on resistance

than p-channel transistor. Thus when transistors are put in series, a
K n-channel transistors have lower on resistance than K pchannel ones. Hence a K-input NAND gate is generally faster and
preferred over a K- input NOR gate
Result: NAND gates are preferred in CMOS.
Limited # of inputs in one gate

8-input CMOS NAND
I1
I2
I3
I4
OUT
I5
I6
I7
I8
I1
I2
I3
I4
I5
I6
I7
I8

OUT
More complicated
Copyright 2000 by Pre

Digital Design Principles a
VDD
(a)
(b)
A
Q2
Q4
B
Q6
Q2
Q3
Q4
Q5
Q6
L L L off on
CMOSLL AND-ORL L H off on
L L gate
H L off on
INVERT
off
off
off
off
on
on
on
on
off
off
off
off
on
on
on
on
on
on
on
on
off
off
off
off
on
on
on
on
off
off
off
off
off
off
on
on
off
off
on
on
off
off
on
on
Z
off
off
on
on
on
on
off
off
on
on
off
off
on
on
off
off
on
on
off
off
Q8
Z
A
C
Q5
Q3
Q7
Q1
A B C D
C
D
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
Q1
off
off
off
off
off
on
on
on
on
on
on
on
on
on
on
on
on
on
off
off
off
off
off
off
off
off

CMOS Electrical Characteristics

Digital analysis works only if circuits are
operated in spec:
Power supply voltage
Temperature
Input-signal quality
Output loading
Must do some analog analysis to prove that

circuits are operated in spec.
Fanout specs
Timing analysis (setup and hold times)
DC Loading
An output must sink
current from a load
when the output is in
the LOW state.
(a)
An output must source

current to a load when
the output is in the
HIGH state.
(b)
VCC
"sourcing
current"
VCC
CMOS
inverter
CMOS
inverter
Rp
> 1 M
Rp
VOLmax
VIN
Rn
IOLmax
resistive
load
VOHmin
VIN
resistive
load
Rn
> 1 M
IOHmax
"sinking
current"
Output-voltage drops
Resistance of off transistor is > 1 Megohm,
but resistance of on transistor is nonzero,
Voltage drops across on transistor, V = IR
For CMOS loads, current and voltage drop

are negligible.
For TTL inputs, LEDs, terminations, or other
resistive loads, current and voltage drop are
significant and must be calculated.
Example loading calculation

Need to know on and off resistances of
output transistors, and know the
characteristics of the load.
VCC = +5.0 V
VCC = +5.0 V
Thvenin equivalent
of resistive load
(b)
(a)
CMOS
inverter
Rp
CMOS
inverter
VOUT
VIN
Rp
1 k
Rn
VIN
2 k
resistive
load

VOUT
RThev = 667
+
Rn
VThev = 3.33 V
Calculate for LOW state

VCC = +5.0 V
Thvenin equivalent
of resistive load
CMOS
inverter
> 1 M
VIN = +5.0 V
(HIGH)
VOUT = 0.43 V
RThev = 667
(LOW)
100
VThev = 3.33 V

100
Vout = 3.33V
= 0.43V
667 + 100
Calculate for HIGH state

VCC = +5.0 V
Thvenin equivalent
of resistive load
CMOS
inverter
200
VIN = +0.0 V
(LOW)
VOUT = 4.61 V
RThev = 667
(HIGH)
> 1 M
VThev = 3.33 V

667
Vout = (3.33V ) + (5V 3.33V )

= 4.61V
667 + 200
Limitation on DC load
If too much load, output voltage will go outside
of valid logic-voltage range.
VCC
VOHmin
HIGH
VIHmin
0.7 VCC
High-state
DC noise margin
ABNORMAL
VILmax
0.3 VCC
LOW
0
VOLmax

Digital Design
Principles and Practices, 3/e
OHmin
IHmin
V
,V
VOLmax, VILmax
Low-state
DC noise margin
Output-drive specs
VOLmax and VOHmin are specified for certain
output-current values, IOLmax and IOHmax.
No need to know details about the output circuit,
only the load.
(b)
(a)
"sourcing
current"
(b)
VCC
CC
"sourcing
current"
VCC
CMOS
inverter
R pp
> 1 M
VOHmin
OLmax
VIN
IN
resistive
load
R nn
> 1 M
Rp
resistive
load
IIOHmax
OLmax
VIN
resistive
load
"sinking
current"
Rn
>1
Input-loading specs
Each gate input requires a certain amount of
current to drive it in the LOW state and in the
HIGH state.
IIL and IIH
These amounts are specified by the manufacturer.
Fanout calculation
(LOW state) The sum of the IIL values of the driven
inputs may not exceed IOLmax of the driving output.
(HIGH state) The sum of the IIH values of the driven
inputs may not exceed IOHmax of the driving output.
Need to do Thevenin-equivalent calculation for nongate loads (LEDs, termination resistors, etc.)
Manufacturers data sheet

Ta bl e 3 - 3 Manufacturer's data sheet for a typical CMOS device, a 54/74HC00 quad NAND gate.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = 40C to +85C, VCC = 5.0V5%; Military: TA = 55C to +125C, VCC = 5.0 V 10%
Sym.
Test Conditions (1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH level
Guaranteed logic HIGH level
3.15
VIL
Input LOW level
Guaranteed logic LOW level
1.35
IIH
Input HIGH current
VCC = Max., VI = VCC
IIL
Input LOW current
VCC = Max., VI = 0 V
VIK
Clamp diode voltage VCC = Min., IN = 18 mA
0.7
1.2
IIOS
Short-circuit current VCC = Max.,(3) VO = GND
35
mA
VOH
Output HIGH voltage
VOL
Output LOW voltage
ICC
Quiescent power
supply current
VCC = Min.,
VIN = VIL
IOH = 20 A
4.4
4.499
IOH = 4 mA
3.84
4.3
VCC = Min.
VIN = VIH
IOL = 20 A
.001
0.1
0.17
0.33
10
Typ.
Max.
Unit
IOL = 4 mA
VCC = Max.
VIN = GND or VCC, IO = 0
SWITCHING CHARACTERISTICS OVER OPERATING RANGE, CL = 50 pF

Sym.
Parameter (4)
Test Conditions
Min.
TTL Electrical Characteristics

VCC = +5 V
R2
8 k
R1
20 k
R5
120
D1X
Q3
Q4
D1Y
Y
VA
D2X
D2Y
Q2
D3
D4
R6
4 k
R3
12 k
Q5
R4
1.5 k
R7
3 k
Q6
Diode AND gate

and input protection
Phase splitter

Output stage
TTL LOW-State Behavior

VCC = +5 V
R2A
8 k
R5A
120
R1B
20 k
D1XB
0.35 V
Q3A
(OFF)
R2B
8 k
Q4A
(OFF)
D1YB
Q2A
(ON)
D3A
D4A
Q2B
(OFF)
R6A
4 k
2V
D2XB
D2YB
R3B
12 k
Q5A
(ON)
R4A
1.5 k
R7A
3 k
R4B
1.5 k
Q6A
(ON)

TTL HIGH-State Behavior

VCC = +5 V
R2A
8 k
R5A
120
Q3A
(ON)
R1B
20 k
R2B
8 k
D1XB
2.7 V
Q4A
(ON)
D1YB
Q2A
(OFF)
D3A
D4A
Q2B
(ON)
R6A
4 k
2V
D2XB
D2YB
R3B
12 k
Q5A
(OFF)
R4A
1.5 k
Ileak
R7A
3 k
Q6A
(OFF)

R4B
1.5 k
TTL Logic Levels and Noise Margins

Asymmetric, unlike CMOS
VCC = 5 V
HIGH
ABNORMAL
LOW
0
VOHmin = 2.7 V
VIHmin = 2.0 V
High-state
DC noise margin
VILmax = 0.8 V
VOLmax = 0.5 V
Low-state
DC noise margin

CMOS can be made compatible with TTL

T CMOS logic families
CMOS vs. TTL Levels

TTL levels
CMOS levels
VCC
V =5V
VCC
OHmin
HIGH
VCC
0.7 V
CC
0.7 VCC
0.3 VCC
0.3 VCC
0
0
VOHmin
IHmin
High-state
DC noise
HIGH margin
ABNORMAL
VIHmin
High-state
DC noise margin
ABNORMAL
VILmax
HIGH
LOW
LOW
VILmax
V
VOLmax
OLmax0

Copyright
Principles
2000 by Prentice
Hall, Inc.3/e
Digital
Design
and Practices,
CMOS with TTL Levels

-- HCT, FCT, VHCT, etc.
ABNORMAL
Low-state
Low-state
LOW margin
DC noise
noise
margin
DC
VOHmin = 2.7 V
VIHmin = 2.0 V
VILmax = 0.8 V
VOLmax = 0.5 V
TTL differences from CMOS

Asymmetric input and output characteristics.
Inputs source significant current in the LOW
state, leakage current in the HIGH state.
Output can handle much more current in the
LOW state (saturated transistor).
Output can source only limited current in the
HIGH state (resistor plus partially-on transistor).
TTL has difficulty driving pure CMOS inputs
because VOH = 2.4 V (except T CMOS).
AC Loading
AC loading has become a critical design factor
as industry has moved to pure CMOS systems.
CMOS inputs have very high impedance, DC loading
is negligible.
CMOS inputs and related packaging and wiring have
significant capacitance.
Time to charge and discharge capacitance is a major
component of delay.
Transition times
(a)
(b)
tr
(c)
tf
HIGH
VIHmin
LOW
VILmax
tr
tf
Circuit for transition-time analysis

VCC = +5.0 V
Equivalent load for

transition-time analysis
CMOS
inverter
Rp
RL
VOUT
VIN
Rn
CL
VL

HIGH-to-LOW transition
VCC = +5.0 V
(b)
(a)

(b)
>
1 M
200
AC load
ad
00 pF
VCC
VOUT
VOUT
= 5.0 V
VIN
100
> 1 M
VIN
IOUT = 0
IOUT
100 pF
Exponential rise time

Rp
Rn
200
> 1 M
> 1 M
100
5V
3.5 V
VOUT
1.5 V
0V
time
0
tr

pF
LOW-to-HIGH transition
VCC = +5.0 V

(a)
(b)
(b)
> 1 M
200
AC load
VOUT
=0V
VOUT
VIN
100
>
1 M
VIN
IOUT = 0
IOUT
100 pF
Exponential fall time

Rp
Rn
200
> 1 M
> 1 M
100

5V
t = RC time constant
exponential formulas, e-t/RC
3.5 V
VOUT
1.5 V
0V
time
0
tf
Transition-time considerations
Higher capacitance ==> more delay
Higher on-resistance ==> more delay
Lower on-resistance requires bigger
transistors
Slower transition times ==> more power
dissipation (output stage partially shorted)
Faster transition times ==> worse
transmission-line effects (Chapter 11)
Higher capacitance ==> more power
dissipation (CV2f power), regardless of rise
and fall time
Open-drain outputs
No PMOS transistor, use resistor pull-up
VCC
(a)
(b)
Z
A
Q1
Q2
(c)
A B
Q1
Q2
L
L
H
H
off
off
on
on
off
on
off
on
open
open
open
L
L
H
L
H
A
B

What good is it?

Open-drain bus
VCC

DATAOUT
Data1
Enable1
Data3
Enable3
Data5
Enable5
Data7
Enable7
Data2
Enable2
Data4
Enable4
Data6
Enable6
Data8
Enable8
Problem -- really bad rise time
Open-drain transition times

Pull-up resistance is larger than a PMOS
transistors on resistance.
VOUT

5V
3.5 V
1.5 V
0V
0
50
tf
100
150
200
250
tr
Can reduce rise time by reducing pull-up

resistor value
But not too much
300
time
Next Class
Language Elements IV
Concurrent Constructs
R.B.Ghongade
Lecture 8
Types of concurrent constructs
when else
with select
These constructs need not be in the process
whenelse
A concurrent statement which assigns one of
several expressions to a signal, depending on the
values of Boolean conditions which are tested in
sequence
Equivalent to a process containing an if statement
Syntax
[Label:] Target <= [Options]
Expression [after TimeExpression] when Condition
else
Expression [after TimeExpression] when Condition
else
...
Expression [after TimeExpression] [when Condition];
Where to use ?
architecture begin HERE - end
block begin HERE - end
generate begin HERE - end
Rules:
The reserved word guarded may only appear in a
signal assignment within a guarded block. A
guarded assignment only executes when the
guard expression on the surrounding block is
true
An Expression on the right hand side may be
replaced by the reserved word unaffected
Synthesis
Conditional signal assignments are synthesized to
combinational logic
The Expressions on the right hand side are multiplexed
onto the Target signal
The resulting logic will be priority encoded, because the
conditions are tested in sequence
Remarks:
Conditional and selected signal assignments are a
concise way to describe combinational logic in
Register Transfer Level descriptions, although
processes can be easier to read and maintain in some
cases
A conditional assignment is a neat way to convert from
a Boolean condition to the type Std_logic
Example
z <= a when s1=1
else
b when s2=1
else
c ;
c
MUX21
s2
MUX21
a
s1
Example (Tri-state Buffer)

architecture tri_buff of tri_buff_part is
begin
out1 <= in1 when control=1
else
z;
end tri_buff ;
control
in1
out1
withselect
A concurrent statement which assigns
one of several expressions to a signal,
depending on the value of the expression at
the top.
Equivalent to a process containing a case
statement
Syntax
[Label:] with Expression select
Target <= [Options]
Expression [after TimeExpression] when Choices,
Expression [after TimeExpression] when Choices,
Expression when others;
Where to use ?
architecture begin HERE end
block begin HERE end
generate begin HERE end
Rules:
Every case of the Expression at the top must be
covered once and only once by the choices
An Expression on the right hand side may be
replaced by the reserved word unaffected
All possible choices must be enumerated
others clause is important since we have 9valued logic
Synthesis
Selected signal assignments are
synthesized to combinational logic
The Expressions on the right hand side
are multiplexed onto the Target signal
Remarks:
Conditional and selected signal
assignments are a good way to describe
combinational logic in Register Transfer
Level descriptions
Example (Multiplexer)
architecture mux41 of mux is -- Assumptions
begin
-- a,b,c,d,z are
with control select
-- std_logic
z <= a when 00 ,
-- control is
b when 01 ,-- std_logic_vector(1 downto 0)
c when 10 ,
d when 11 ,
Z when others ;
end mux41 ;
a
b
c
d
z
MUX41
control
Block
There are two types of blocks

Simple
Guarded
Simple block
The BLOCK statement, in its simple form,
represents only a way of locally
partitioning the code
It allows a set of concurrent statements to
be clustered into a BLOCK, with the
purpose of turning the overall code more
readable and more manageable (which
might be helpful when dealing with long
codes)
Syntax
label: BLOCK
[declarative part]
BEGIN
(concurrent statements)
END BLOCK label;
General form of
architecture using
block for partitioning
ARCHITECTURE example
...
BEGIN
...
block1: BLOCK
BEGIN
...
END BLOCK block1 ;
...
block2: BLOCK
BEGIN
...
END BLOCK block2 ;
...
END example ;
Block can be nested inside another block

Syntax
label1: BLOCK
[declarative part of top block]
BEGIN
[concurrent statements of top block]
label2: BLOCK
[declarative part nested block]
BEGIN
(concurrent statements of nested block)
END BLOCK label2;
[more concurrent statements of top block]
END BLOCK label1;
Guarded block
A guarded BLOCK is a special kind of
BLOCK, which includes an additional
expression, called guard expression
A guarded statement in a guarded BLOCK is
executed only when the guard expression is
TRUE
Syntax
label: BLOCK (guard expression)
[declarative part]
BEGIN
(concurrent guarded and unguarded statements)
END BLOCK label;
Even though only concurrent statements

can be written within a BLOCK, with a
guarded BLOCK even sequential circuits
can be constructed
LIBRARY ieee;
ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END latch;
ARCHITECTURE latch OF latch IS
BEGIN
b1: BLOCK (clk='1')
BEGIN
q <= GUARDED d;
END BLOCK b1;
END latch;
Latch
LIBRARY ieee;
ENTITY DFF IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END DFF;
DFF
ARCHITECTURE DFF OF DFF IS

BEGIN
b1: BLOCK (clkEVENT AND clk='1')
BEGIN
q <= GUARDED 0 WHEN rst=1 ELSE d;
END BLOCK b1;
END DFF;
Here, a positive-edge sensitive D-type flip-flop, with synchronous
reset, is designed.
In it, clk'EVENT AND clk='1' is the guard expression, while
q <= GUARDED '0 WHEN rst='1' is a guarded statement. Therefore,
q<='0' will occur when the guard expression is true and rst is 1
Homework Problems
1)Generic encoder
2) 8- bit ALU
For ALU in problem 2

sel
Operation
Function
0000 y <= a
Transfer a
0001 y <= a+1
Increment a
0010 y <= a-1
Decrement a
0011 y <= b
Transfer b
0100 y <= b+1
Increment b
0101 y <= b-1
Decrement b
0110 y <= a + b
Add a and b
0111 y <= a + b + cin
Add a and b with carry
1000 y <= NOT a
Complement a
1001 y <= NOT b
Complement b
1010 y <= a AND b
AND
1011 y <= a OR b
OR
1100 y <= a NAND b
NAND
1101 y <= a NOR b
NOR
1110 y <= a XOR b
XOR
1111 y <= a XNOR b
XNOR
Unit
Arithmetic
Logic
3) Priority Encoder
The circuit must encode the address of the input bit of

highest order that is active. 000 should indicate that
there is no request at the input (no bit active)
Expected waveform for Problem 3
Next Class
Component Instantiation
DO NOT MISS
IN ANY CASE !
Component Instantiation
R.B.Ghongade
Lecture 9,10,11
Component
A component is analogous to a chip socket; it gives an
indirect way to use one hierarchical block within another
A component is instantiated within an architecture, and
is associated with a (lower level) entity and architecture
during elaboration using information from a
configuration.
A component declaration is similar in form to an entity
declaration, in that it includes the required ports and
parameters of the component
The difference is that it refers to a design described in a
separate VHDL file
The ports and parameters in the component declaration
may be a subset of those in the component file, but they
must have the same names
Component can be declared in the

main code itself
Component can be declared in a

package
Syntax :
COMPONENT component_name
GENERIC ( parameter_name : string := default_value ;
parameter_name : integer := default_value);
PORT (input_name, input_name : IN STD_LOGIC;
bidir_name, bidir_name : INOUT STD_LOGIC;
output_name, output_name : OUT STD_LOGIC);
END COMPONENT;
Where :
package - <HERE> - end
architecture - is - <HERE> - begin - end
block - <HERE> - begin - end
generate - <HERE> - begin - end
Rules:
For default configuration, the component
name must match the name of the
corresponding entity to be used in its
place, and generics and ports must also
match in name, mode and type
Synthesis:
A component without a corresponding
design entity is synthesized as a black
box
In VHDL'93, components are not necessary. It is
possible instead to directly instantiate an entity
within an architecture.
Example
component Counter
generic (N: INTEGER);
port (Clock, Reset, Enable: in Std_logic;
Q: buffer Std_logic_vector (N-1 downto 0));
end component ;
Instantiation
A concurrent statement used to define the
design hierarchy by making a copy of a
lower level design entity within an
architecture
In VHDL'93, a direct instantiation of an
entity bypasses the component and
configuration
Syntax:
InstanceLabel: [component] ComponentName
[GenericMap] [PortMap];
InstanceLabel: entity
EntityName[(ArchitectureName)]
InstanceLabel: configuration ConfigurationName
Where:
architecture begin - <HERE> - end
block begin - <HERE> - end
generate begin - <HERE> - end
Rules:
An entity, architecture or configuration
must be compiled into a library before the
corresponding instance can be compiled
However, an instance of a component can
be compiled before the corresponding
design entity has even been written
Example :
G1: NAND2 generic map (1.2 ns)
port map (N1, N2, N3);
G2: entity WORK.Counter(RTL)
port map (Clk, Rst, Count);
Generic Map
Used to define the values of generics
Usually given in an Instance, but may also
appear in a configuration
Syntax
generic map ([Formal =>] Actual, ...)
Formal = {either} Name FunctionCall

Actual = Expression
Where :
Label : ComponentName <HERE> port map ();
for - use - <HERE> port map ()
block generic (); <HERE> ; port begin - end
Rules :
The two forms of syntax (ordered list or
explicitly named choices) can be mixed, but the
ordered list must come before the named choices
A generic map does not end with a semicolon!
Example:
architecture Structure of Ent is
component NAND2
generic (TPLH, TPHL: TIME := 0 NS);
port (A, B: in STD_LOGIC;
F : out STD_LOGIC);
end component;
begin
G1: NAND2 generic map (1.9 NS, 2.8 NS)
G2: NAND2 generic map (TPLH => 2 NS, TPHL => 3 NS)
end Structure;
Port Map
A port map is typically used to define the
interconnection between instances in a
structural description (or netlist)
A port map maps signals in an
architecture to ports on an instance within
that architecture
Port maps can also appear in a
configuration or a block
Syntax:
port map ([Formal =>] Actual, ...);
Formal = {either} Name FunctionCall

Actual = {either} Name FunctionCall open
Where:
Label : ComponentName generic map () <HERE>;
for - use - generic map () <HERE>;
block - port () ; <HERE>; - begin - end
Rules:
The two forms of syntax (ordered list or explicitly named
ports) can be mixed, but the ordered list must come
before the named ports
Within an instance, the formals are ports on the
component or entity being instanced, the actuals are
signals visible in the architecture containing the instance
Within a configuration, the formals are ports on the
entity, the actuals are ports on the component
If the actual is a conversion function, this is called
implicitly as values are passed in
If the formal is a conversion function, this is called
implicitly as values are passed out
Use the port names rather than order to improve readability and
reduce the risk of making connection errors
Example:
component COUNTER
port (CLK, RESET: in Std_logic;
UpDown: in Std_logic := '0';-- default value
Q: out Std_logic_vector(3 downto 0));
end component;
...
-- Positional association...
G1: COUNTER port map (Clk32MHz, RST, open, Count);
-- Named association (order doesn't matter)...
G2: COUNTER port map ( RESET => RST,
CLK => Clk32MHz,
Q(3) => Q2MHz,
Q(2) => open, -- unconnected
Q(1 downto 0) => Cnt2,
UpDown => open);
Top Level Entity and Lower Level Entity
RESET
RST
Clk32MHz
Q2MHz
Cnt2
TOP LEVEL ENTITY
COUNT
CLK
Updown
COUNTER
(LOWER LEVEL ENTITY)
RESET => RST

CLK => Clk32MHz
Q(3) => Q2MHz
RST
TOP LEVEL ENTITY
Clk32MHz
Q2MHz
RESET
RESET
CLK
CLK
Cnt2
Q
Updown
Q(3)
G1
Updown
G2
Q(0)
COUNT
UpDown => open
A still simpler example

entity ND4 is
port (in1,in2,in3,in4 : in std_logic ;
z : out std_logic);
end ND4;
architecture ND4_CI of ND4 is
component ND2
port (a , b : in std_logic;
c : out std_logic);
end component ;
signal temp1, temp2 : std_logic;
begin
U1 : ND2 port map (a => in1 , b => in2 , c => temp1);
U2 : ND2 port map (a => in3 , b => in4 , c => temp2);
U3 : ND2 port map (a => temp1 , b => temp2 , c => z);
end ND4_CI ;
infers
ND4
IN1
c => temp1 for U1

a => temp1 for U3
c
b
U1
IN2
a
c
b
U3
IN3
a
c
b
IN4
U2
c => temp2 for U2

b => temp2 for U3
Generate statement
A concurrent statement used to create
regular structures or conditional structures
during elaboration
Used to create multiple copies of
components , processes or blocks
It provides a compact description of
regular structures such as memories ,
registers and counters
Two flavours of generate statement are:

for generate
Number of copies is determined by a discrete
range
if generate
Zero or one copy is made conditionally
Range must be a computable integer in any

of the following forms:
integer_expression to integer_expression
integer_expression downto integer_expression
Each integer_expression evaluates to an integer
Syntax :
Label: for ParameterName in Range generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Label: if Condition generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Where:
architecture begin - <HERE> - end
block begin - <HERE> - end
generate begin - <HERE> - end
Rules :
The Range and Condition must both be
static, i.e. they cannot include signals
The Label at the beginning of the generate
statement cannot be omitted
Synthesis:
Synthesis is straightforward, but not all
synthesis tools support generate!
Example:
architecture ABC of full_add4 is
component full_add
port (PA , PB , PC : in std_logic ;
PCOUT , PSUM : out std_logic) ;
end component ;
signal c: std_logic_vector(4 downto 0);
begin
c(0) <= cin ; -- cin is declared in entity
GK : for k in 3 downto 0 generate
FA :full_add port map(A(k),B(k),C(k),C(k+1),SUM(k);
end generate GK ;
cout <= c(4) ; -- cout is declared in entity
end ABC ;
infers
A(3)
Cout
B(3)
A(2)
FA3
B(1)
C(2)
SUM(2)
A(0)
FA1
FA2
C(3)
SUM(3)
A(1)
B(2)
B(0)
FA0
C(1)
SUM(1)
SUM(0)
Cin
Another example
architecture SHIFTER_ARCH of SHIFTER is
component DFF
port (D , CLK : in std_logic ;
Q : out std_logic) ;
end component ;
begin
GK : for k in 0 to 3 generate
GK0 : IF k=0 generate
DFILPFLOP : DFF port map (count , clock , Q(k));
end generate GK0 ;
GK1_3 : if k > 0 generate
DFILPFLOP : DFF port map (Q(k-1), clock , Q(k));
end generate GK1_3 ;
end generate GK ;
end SHIFTER_ARCH ;
infers
CLOCK
COUNT
DF0
DF2
DF1
Q(0)
Q(1)
DF3
Q(2)
Q(3)
Ways to describe a circuit!

Three types of descriptions possible with
VHDL
Structural
Dataflow
Behavioral
Structural Method
At the structural level, which is the lowest level, you
have to first manually design the circuit.
Use VHDL to specify the components and gates that
are needed by the circuit and how they are
connected together by following your circuit exactly
Synthesizing a structural VHDL description of a
circuit will produce a netlist that is exactly like your
original circuit
The advantage of working at the structural level is
that you have full control as to what components are
used and how they are connected.
But you need to first come up with the circuit and so
the full capabilities of the synthesizer are not utilized
Dataflow Method
At the dataflow level, you use the built-in logical
functions of VHDL in signal assignment statements
to describe a circuit, which again you have to first
design manually
Boolean functions that describe a circuit can be
easily converted to signal assignment statements
using the built-in logical functions
The only drawback is that the built-in logical
functions such as the AND and OR function only
take two operands. This is like having only 2-input
gates to work with !
All the statements use in the structural and dataflow
level are executed concurrently
Behavioral Method
Describing a circuit at the behavioral level is
most similar to writing a computer program
You have all the standard high-level
programming constructs such as the FOR
LOOP, WHILE LOOP, IF THEN ELSE,
CASE, and variable assignments
The statements are enclosed in a process
block and are executed sequentially
Example
BCD to 7- segment display decoder
a
I3
I2
I1
I0
BCD to 7-segment
display decoder
segs(6) {seg 'a'}

segs(5) {seg 'b'}
segs(4) {seg 'c'}
segs(3) {seg 'd'}
segs(2) {seg 'e'}
segs(1) {seg 'f'}
segs(0) {seg 'g'}
b
g
c
d
Truth-table
Logic Equations
a = I 3 + I1 + ( I 2 : I 0 )
b = I 2 + ( I1 : I 0 )
'
c = I 2 + I1 + I 0
'
d = I1I 0 + I 2 I 0 + I 2 I1 + I 2 I1 I 0
'
'
e = I1I 0 + I 2 I 0
'
'
'
'
'
'
f = I 3 + I 2 I1 + I 2 I 0 + I1 I 0
'
'
g = I 3 + ( I 2 I1 ) + I1I 0
'
'
'
Logic gates
Structural VHDL description

ENTITY myxnor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxnor2;
ARCHITECTURE Dataflow OF myxnor2 IS
BEGIN
o <= not(i1 XOR i2);
END Dataflow;
ENTITY myxor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxor2;
ARCHITECTURE Dataflow OF myxor2 IS
BEGIN
o <= i1 XOR i2;
END Dataflow;
ENTITY myand2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myand2;
ARCHITECTURE Dataflow OF myand2 IS
BEGIN
o <= i1 AND i2;
END Dataflow;
ENTITY myand3 IS PORT(i1, i2, i3: IN BIT; o: OUT BIT);

END myand3;
ARCHITECTURE Dataflow OF myand3 IS
BEGIN
o <= (i1 AND i2 AND i3);
END Dataflow;
ENTITY myor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myor2;
ARCHITECTURE Dataflow OF myor2 IS
BEGIN
o <= i1 OR i2;
END Dataflow;
ENTITY myor3 IS PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END myor3;
BEGIN
o <= i1 OR i2 OR i3;
END Dataflow;
ENTITY myor4 IS PORT(i1, i2, i3, i4: IN BIT; o: OUT BIT);

END myor4;
BEGIN
o <= i1 OR i2 OR i3 OR i4;
END Dataflow;
ENTITY inv IS PORT (i: IN BIT; o: OUT BIT);
END inv;
ARCHITECTURE Dataflow OF inv IS
BEGIN
o <= not i;
END Dataflow;
LIBRARY ieee;
ENTITY bcd IS PORT(i0, i1, i2, i3: IN BIT;
a, b, c, d, e, f, g: OUT BIT);
END bcd;
ARCHITECTURE Structural OF bcd IS
COMPONENT inv PORT (i: IN BIT ;o: OUT BIT);
END COMPONENT;
COMPONENT myand2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myand3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor4 PORT(i1, i2, i3, i4: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxnor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
SIGNAL j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z: BIT;

BEGIN
U1: INV port map(i2,j);
U2: INV port map(i1,k);
U3: INV port map(i0,l);
U4: myXNOR2 port map(i2, i0, z);
U5: myOR3 port map(i3, i1, z, a);
U6: myXNOR2 port map(i1, i0, y);
U7: myOR2 port map(j, y, b);
U8: myOR3 port map(i2, k, i0, c);
U9: myAND2 port map(i1, l, x);
U10: myAND2 port map(j, l, w);
U11: myAND2 port map(j, i1, v);
U12: myAND3 port map(i2, k, i0, t);
U13: myOR4 port map(x, w, v, t, d);
U14: myAND2 port map(i1, l, s);
U15: myAND2 port map(j, l, r);
U16: myOR2 port map(s, r, e);
U17: myAND2 port map(i2, k, q);
U18: myAND2 port map(i2, l, p);
U19: myAND2 port map(k, l, o);
U20: myOR4 port map(i3, q, p, o, f);
U21: myXOR2 port map(i2, i1, n);
U22: myAND2 port map(i1, l, m);
U23: myOR3 port map(i3, n, m, g);
END Structural;
Dataflow VHDL description

LIBRARY ieee;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
END bcd;
ARCHITECTURE Dataflow OF bcd IS
BEGIN
Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0)); -- seg a
Segs(2) <= (NOT I(2)) OR NOT (I(1) XOR I(0)); -- seg b
Segs(3) <= I(2) OR (NOT I(1)) OR I(0); -- seg c
Segs(4) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)) -- seg d
OR (NOT I(2) AND I(1)) OR (I(2) AND NOT I(1) AND I(0));
Segs(5) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)); -- seg e
Segs(6) <= I(3) OR (I(2) AND NOT I(1)) -- seg f
OR (I(2) AND NOT I(0)) OR (NOT I(1) AND NOT I(0));
Segs(7) <= I(3) OR (I(2) XOR I(1)) OR (I(1) AND NOT I(0)); -- seg g
END Dataflow;
Behavioral VHDL description

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCD is
port( I : in STD_LOGIC_VECTOR(3 downto 0);
segs : out STD_LOGIC_VECTOR(6 downto 0) );
end BCD;
architecture Behavioral of BCD is
begin
with I select
Segs <= "1111110" when "0000",
"0110000" when "0001",
"1101001" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110011" when "1001",
"0000000" when others;
end
Behavioral;
Output
Assignment No 3
Equations for carry_generate(G) and

carry_propagate(P) for ALU 74181
xi
hsi
yi
si
xi-1
x0
yi-1
ci
Carry Lookahead Logic
g i= x i . y i
pi=xi + yi
y0
c0
ci+1= gi + pi . ci
c1= g0 + p0 . c0
Additional Information
c2= g1 + p1 . g0 + p1.p0.c0
c3= g2 + p2 . g1 + p2.p1.g0+p2.p1.p0.c0
c4= g3 + p3 . g2 + p3.p2.g1+p3.p2.p1.g0+p3.p2.p1.p0.c0
Equations for implementation of G_L , P_L

outputs
G_L= (g3+p3.g2+p3.p2.g1+p3.p2.p1.g0)
P_L=(p3.p2.p1.p0)
Implement the Carry_Generate and Carry_Propagate

outputs also to complete the ALU assignment
Next Class
Sequential Statements
generated doubt !
A[3:0]
B[3:0]
Cin
[3:0]
[3:0]
[0]
[0]
[1]
[1]
[1]
fulladder
PA
PB
PC
PCOUT
PSUM
[1]
[0]
[2]
[2]
[2]
fulladder
PA
PB
PC
PCOUT
PSUM
[2]
[1]
[3]
[3]
[3]
fulladder
PA
PB
PC
PCOUT
PSUM
[3]
[2]
fulladder
PA
PB
PC
PCOUT
PSUM
[4]
[3]
[4]
[3:0]
COUT
SUM[3:0]
[4]
[3:0]
COUT
SUM[3:0]
GK.3.FA
GK.2.FA
GK.1.FA
GK.0.FA
A[3:0]
B[3:0]
Cin
[3:0]
[3:0]
[0]
[0]
[1]
[1]
[1]
fulladder
PA
PB
PC
PCOUT
PSUM
[1]
[0]
[2]
[2]
[2]
fulladder
PA
PB
PC
PCOUT
PSUM
[2]
[1]
[3]
[3]
[3]
fulladder
PA
PB
PC
PCOUT
PSUM
[3]
[2]
fulladder
PA
PB
PC
PCOUT
PSUM
[4]
[3]
GK.3.FA
GK.2.FA
GK.1.FA
GK.0.FA
GK : for k in 3 downto 0 generate
GK : for k in 0 to 3 generate
R.B.Ghongade
Lecture 12
VHDL code is inherently concurrent
Sections of code that are executed
sequentially are :
PROCESS
FUNCTION
PROCEDURE
One important aspect of sequential code is that it is

not limited to sequential logic
We can build sequential circuits as well as
combinational circuits
Sequential code is also called behavioral code
Thus a PROCESS is a concurrent statement which
describes behaviour
Sequential statements are allowed only

inside PROCESSES, FUNCTIONS, or
PROCEDURES
Sequential statements are:
IF
WAIT
CASE
LOOP
VARIABLES are also restricted to be used

in sequential code only
VARIABLE can never be global, so its value
can not be passed out directly
SIGNALS and VARIABLES revisited !

VHDL has two ways of passing non-static values around:
by means of a SIGNAL or by means of a VARIABLE
A SIGNAL can be declared in a PACKAGE, ENTITY or
ARCHITECTURE (in its declarative part), while a
VARIABLE can only be declared inside a piece of
sequential code
SIGNAL is global while VARIABLE is local
The value of a VARIABLE can never be passed out of
the PROCESS directly; if necessary, then it must be
assigned to a SIGNAL
Update of VARIABLE is immediate whereas new value
for SIGNAL is generally only guaranteed to be available
after the conclusion of the present run of the PROCESS
Assignment operator for SIGNAL is <= while that for
VARIABLE is : =
Process
A PROCESS is a sequential section of
VHDL code
It is characterized by the presence of IF,
WAIT, CASE, or LOOP, and by a
sensitivity list (except when WAIT is used)
A PROCESS must be installed in the main
code, and is executed every time a signal
in the sensitivity list changes (or the
condition related to WAIT is fulfilled)
Syntax
[label:] [postponed] PROCESS (sensitivity list)
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)
END [postponed] PROCESS [label];
Where
entity - begin - <HERE> - end
architecture - begin - <HERE> - end
block - begin - <HERE> - end
generate - begin - <HERE> - end
POSTPONED
is a reserved
VHDL word
Rules
A process must contain either a sensitivity
list or wait statements, but not both
Every process executes once during
initialization, before simulation starts
A postponed process is not executed until
the final simulation cycle of a particular
simulation time, and thus sees the stable
values of signals and variables
A process with neither a sensitivity list nor a wait
will loop forever !
Using EVENT attribute

To construct a synchronous circuit,
monitoring a signal (clock, for example) is
necessary
A common way of detecting a signal change
is by means of the EVENT attribute
For instance, if clk is a signal to be
monitored, then clk EVENT returns TRUE
when a change on clk occurs (rising or
falling edge)
IF construct
A sequential statement which executes one
branch from a set of branches dependent
upon the conditions, which are tested in
sequence
Syntax
[Label:] if Condition then
SequentialStatements...
[elsif Condition then
SequentialStatements...]
... {any number of elsif parts}
[else
SequentialStatements...]
end if [Label];
Be careful about the spelling of elsif and end if
Synthesis
Assignments within if statements generally
synthesize to multiplexers
Incomplete assignments, where outputs remain
unchanged for certain input conditions,
synthesize to transparent latches in unclocked
processes, and to flip-flops in clocked
processes
In some circumstances, nested if statements
synthesize to multiple logic levels. This can be
avoided by using a case statement instead
A set of elsif branches can be used to

impart priority to the conditions tested first
To decode a value without giving priority to
certain conditions, use a case statement
instead
Example
IF (x<y) THEN temp:="11111111";
ELSIF (x=y AND w='0') THEN
temp := "11110000";
ELSE temp:=(OTHERS =>'0');
D Flip-Flop with asynchronous reset

A D-type flip-flop is the most basic building block
in sequential logic circuits. In it, the output must
copy the input at either the positive or negative
transition of the clock signal (rising or falling
edge)
If rst = 1, then the output
must be q = 0 ,regardless of
the status of clk.
Otherwise, the output must
copy the input (that is, q = d)
at the positive edge of clk
LIBRARY ieee;
ENTITY dff IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;
Output
clk
d
D[0]
Q[0]
R
rst
Changing the statement

ELSIF (clk'EVENT AND clk=0') THEN
clk
d
D[0]
Q[0]
R
rst
One Digit counter example

Progressive 1-digit
decimal counter
(0 -> 9 ->0)
Single bit input (clk)
and a 4-bit output
(digit).
LIBRARY ieee;
ENTITY counter IS
PORT (clk : IN STD_LOGIC; digit : OUT INTEGER
RANGE 0 TO 9);
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
count: PROCESS (clk)
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
IF (clk'EVENT AND clk='1') THEN
temp := temp + 1;
IF (temp=10) THEN temp := 0;
END IF;
END IF;
digit <= temp;
END PROCESS count;
END counter;
Output
In a counter like circuits always use comparison

statements with constant values
This ensures simple comparator inference as against
full comparator inference for comparison with unknown
values
[3]
digit[3:0]
[1]
[32]
[0]
[31]
[31]
[29]
count.un9_temp
[1]
[3]
temp_3[1]
[1]
[32]
D[3:0]
Q[3:0]
count.temp[3:0]
[3:0]
[3:0]
[29]
un2_temp[29:32]
[31:32]
clk
[29]
[3]
temp_3[3]
Changing the statement IF (temp>=10) THEN temp := 0;

[3]
[30]
[1]
[32]
[29:32]
1010
<
count.un1_temp
[31]
[1]
temp_3[1]
clk
Extra Hardware
[29]
[3]
temp_3[3]
[3]
[30]
[1]
[32]
D[3:0]
Q[3:0]
count.temp[3:0]
[3:0]
[3:0]
1
[29:32]
un2_temp[29:32]
digit[3:0]
Next Class
Sequential Statements cont..
Sequential Statements II
R.B.Ghongade
Lecture 13
Wait statement
The operation of WAIT is sometimes
similar to that of IF
PROCESS cannot have a sensitivity list
when WAIT is employed
Three flavours of WAIT statements are:
WAIT UNTIL
WAIT ON
WAIT FOR
Syntax
WAIT UNTIL signal_condition;

The WAIT UNTIL statement accepts only one signal,
thus being more appropriate for synchronous code
than asynchronous
Since the PROCESS has no sensitivity list in this
case, WAIT UNTIL must be the first statement in the
PROCESS
The PROCESS will be executed every time the
condition is met
Example ( 8-bit register )

PROCESS -- no sensitivity list
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
IF (rst='1') THEN
op <= "00000000";
op <= inp;
END IF;
END PROCESS;
Output and Inference
Output changes
only with clk
clk
inp[7:0]
rst
[7:0]
[7:0]
D[7:0]
R
Q[7:0]
op[7:0]
[7:0]
[7:0]
op[7:0]
Syntax
WAIT ON signal1 [, signal2, ... ];
The WAIT ON statement accepts multiple

signals
The PROCESS is put on hold until any of the
signals listed changes
Example ( 8-bit register )

PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
op <= "00000000";
op <= inp;
END IF;
END PROCESS;
Output changes
with clk and rst
clk
inp[7:0]
[7:0]
[7:0]
D[7:0]
Q[7:0]
R
rst
op[7:0]
[7:0]
[7:0]
op[7:0]
DFF revisited with WAIT!

LIBRARY ieee;
ENTITY dff IS
PORT (d, clk, rst: IN STD_LOGIC; q: OUT
STD_LOGIC);
END dff;
ARCHITECTURE dff OF dff IS
BEGIN
PROCESS
BEGIN
WAIT ON rst, clk;
IF (rst='1') THEN
q <= '0';
q <= d;
END IF;
END PROCESS;
END dff;
clk
d
D[0]
Q[0]
R
rst
Infers exactly the same hardware as the earlier design

As a homework problem repeat the one digit counter with WAIT statement
Syntax
WAIT FOR time;

WAIT FOR is intended for simulation only
(waveform generation for test-benches)
Case statement
CASE is another statement intended exclusively
for sequential code
The CASE statement (sequential) is very similar
to WHEN (combinational)
All permutations must be tested, so the keyword
OTHERS is often helpful
Another important keyword is NULL (the
counterpart of UNAFFECTED), which should be
used when no action is to take place
CASE allows multiple assignments for each test
condition while WHEN allows only one
Syntax
[Label:] case Expression is
when Choices =>
when Choices =>
... {any number of when parts}
end case [Label];
Choices = Choice | Choice | ...

Choice = {either}
ConstantExpression
Range
others {the last branch}
Where
process begin - <HERE> - end
function begin - <HERE> - end
procedure begin - <HERE> - end
if then - <HERE> - elsif then - <HERE>else - <HERE> - end
case - => - <HERE> - when - => - <HERE>end
loop-<HERE>-end
Rules
The Expression must not be enclosed in
parenthesis
The type of the Expression must be
enumeration, integer, physical, or a one
dimensional array
Every case of the Expression must be
covered once and only once by the
Choices
Synthesis
Assignments within case statements
generally synthesize to multiplexers
Incomplete assignments (i.e. where
outputs remain unassigned for certain
input conditions) in unclocked processes
synthesize to transparent latches
Incomplete assignments in clocked
processes synthesize to recirculation
around registers
Example
case ADDRESS
when 0 => -A <= '1';
when 1 =>
A <= '1'; --B <= '1';
when 2 to 15
is
Select a single value
More than one statement in a

branch
=> -- Select a range of ADDRESS
-- values
C <= '1';
when 16 | 20 | 24 => -- Pick out several
-- ADDRESS values
B <= '1';
C <= '1';
D <= '1';
when others => -- Mop up the rest
null;
end case;
2 - digit counter with SSD output

a
a
f
g
e
c
d
c
d
CLK
COUNTER
7 BITSDIGIT 2
DIGIT 1
RST
Progressive 2-digit decimal counter

(0-> 99-> 0) , with external asynchronous
reset plus binary-coded decimal (BCD) to
seven-segment display (SSD) conversion
LIBRARY ieee;
ENTITY counter IS
PORT (clk, rst : IN STD_LOGIC;
digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
PROCESS (clk, rst)
VARIABLE temp1: INTEGER RANGE 0 TO 10;
VARIABLE temp2: INTEGER RANGE 0 TO 10;
BEGIN
IF (rst='1') THEN
temp1 := 0;
temp2 := 0;
temp1 := temp1 + 1;
IF (temp1=10) THEN
temp1 := 0;
temp2 := temp2 + 1;
IF (temp2=10) THEN
temp2 := 0;
END IF;
END IF;
END IF;
CASE temp1 IS
WHEN 0 => digit1 <= "1111110"; --7E
WHEN 1 => digit1 <= "0110000"; --30
WHEN 2 => digit1 <= "1101101"; --6D
WHEN 3 => digit1 <= "1111001"; --79
WHEN 4 => digit1 <= "0110011"; --33
WHEN 5 => digit1 <= "1011011"; --5B
WHEN 6 => digit1 <= "1011111"; --5F
WHEN 7 => digit1 <= "1110000"; --70
WHEN 8 => digit1 <= "1111111"; --7F
WHEN 9 => digit1 <= "1111011"; --7B
WHEN OTHERS => NULL;
END CASE;
CASE temp2 IS
WHEN 0 => digit2 <= "1111110"; --7E
WHEN 1 => digit2 <= "0110000"; --30
WHEN 2 => digit2 <= "1101101"; --6D
WHEN 3 => digit2 <= "1111001"; --79
WHEN 4 => digit2 <= "0110011"; --33
WHEN 5 => digit2 <= "1011011"; --5B
WHEN 6 => digit2 <= "1011111"; --5F
WHEN 7 => digit2 <= "1110000"; --70
WHEN 8 => digit2 <= "1111111"; --7F
WHEN 9 => digit2 <= "1111011"; --7B
END CASE;
END PROCESS;
END counter;
Output
Inference
DO NOT TRY TO WORK OUT HOW

THIS CIRCUIT WORKS !!!
Next Class
Test !!!
Sequential Statements III

R.B.Ghongade
Lecture 14
Loop statement
LOOP is useful when a piece of code must
be instantiated several times
Like IF, WAIT, and CASE, LOOP is
intended exclusively for sequential code,
so it too can only be used inside a
PROCESS, FUNCTION, or
PROCEDURE.
There are several ways of using LOOP
A loop is an infinite loop (and thus an
error) unless it contains an exit or wait
statement
Syntax
[label:] LOOP
(SequentialStatements)
END LOOP [label];
FOR / LOOP: The loop is repeated a fixed number of
times
[label:] FOR identifier IN range LOOP
(sequential statements)
END LOOP [label];
WHILE / LOOP: The loop is repeated until a condition no
longer holds
[label:] WHILE condition LOOP
END LOOP [label];
WAIT : Continue looping until..
EXIT: Used for ending the loop

[label:] EXIT [label] [WHEN condition];
NEXT: Used for skipping loop steps

[label:] NEXT [loop_label] [WHEN condition];
Example of FOR / LOOP:
The loop will be repeated

unconditionally until i
reaches 5
(that is, six times)
FOR i IN 0 TO 5 LOOP
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
One important remark regarding FOR /

LOOP is that both limits of the range must
be static
Thus a declaration of the type
"FOR i IN 0 TO choice LOOP",
where choice is an input (non-static)
parameter, is generally not synthesizable
Example of WHILE / LOOP:

WHILE (i < 10) LOOP
WAIT UNTIL clk'EVENT AND clk='1';
(other statements)
END LOOP;
Example of WAIT in LOOP :

LOOP
WAIT UNTIL Clock = '1';
EXIT WHEN Reset = '1';
Div2 <= NOT Div2;
END LOOP;
In this example, LOOP

will keep repeating
while i < 10
Example of EXIT :
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count:=count+1;
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
EXIT implies not an escape from the current iteration of

the loop, but rather a definite exit (that is, even if i is still
within the data range, the LOOP statement will be
considered as concluded).
In this case, the loop will end as soon as a value
different from 0 is found in the data vector
Example with NEXT:

FOR i IN 0 TO 15 LOOP
NEXT WHEN i=skip; -- jumps to next iteration
(...)
END LOOP;
NEXT causes LOOP to skip one iteration

when i = skip
Synthesis
Not generally synthesizable. Some tools
do allow loops containing wait statements
to describe implicit finite state machines,
but this is not a recommended practice
Example : 8-bit unsigned Carry Ripple Adder

LOWER LEVEL
b
TOP LEVEL
cin
cout
a
a0 b0
cin
c0
s0
a1 b1
c1
a7 b7
c2
c7
s1
s
sj = aj XOR bj XOR cj
cj+1 = (aj AND bj) OR (aj AND cj) OR (bj AND cj)
s7
c8
cout
LIBRARY ieee;
ENTITY adder IS
GENERIC (length : INTEGER := 8);
PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cin: IN STD_LOGIC; s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0);
cout: OUT STD_LOGIC);
END adder;
ARCHITECTURE adder OF adder IS
BEGIN
PROCESS (a, b, cin)
VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0);
BEGIN
carry(0) := cin;
FOR i IN 0 TO length-1 LOOP
s(i) <= a(i) XOR b(i) XOR carry(i);
carry(i+1) := (a(i) AND b(i)) OR (a(i) AND
carry(i)) OR (b(i) AND carry(i));
END LOOP;
cout <= carry(length);
END PROCESS;
END adder;
Output
Example: Leading Zeros

The circuit should count the
number of leading zeros in
a binary vector, starting from
the left end
0 0 0 1 1 0 0 0
3
2
1
0
LIBRARY ieee;
ENTITY LeadingZeros IS
PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
zeros: OUT INTEGER RANGE 0 TO 8);
END LeadingZeros;
ARCHITECTURE behavior OF LeadingZeros IS
BEGIN
PROCESS (data)
VARIABLE count: INTEGER RANGE 0 TO 8;
BEGIN
count := 0;
FOR i IN data'RANGE LOOP
CASE data(i) IS
WHEN '0' => count := count + 1;
WHEN OTHERS => EXIT;
END CASE;
END LOOP;
zeros <= count;
END PROCESS;
END behavior;
Output
Modify the design for trailing zeros !
Comparison between
Concurrent and Sequential
Constructs
R.B.Ghongade
Lecture 15
CASE versus IF
Though in principle the presence of ELSE in the
IF/ELSE statement might infer the
implementation of a priority decoder (which
would never occur with CASE), this will generally
not happen
When IF (a sequential statement) is used to
implement a fully combinational circuit, a
multiplexer might be inferred instead
Therefore, after optimization, the general
tendency is for a circuit synthesized from a
VHDL code based on IF not to differ from that
based on CASE
Same inference !
---- With IF: -------------IF (sel="00") THEN x<=a;
ELSIF (sel="01") THEN x<=b;
ELSIF (sel="10") THEN x<=c;
ELSE x<=d;
---- With CASE: -----------CASE sel IS
WHEN "00" => x<=a;
WHEN "01" => x<=b;
WHEN "10" => x<=c;
WHEN OTHERS => x<=d;
END CASE;
CASE versus WHEN

CASE and WHEN are very similar. However,
while one is concurrent (WHEN), the other is
sequential (CASE)
WHEN
CASE
Statement type
Concurrent
Sequential
Usage
Only outside
PROCESSES,
FUNCTIONS, or
PROCEDURES
Only inside
PROCESSES,
FUNCTIONS, or
PROCEDURES
All permutations must

be tested
Yes for
WITH/SELECT/WHEN
Yes
Max. # of assignments
per test
No-action keyword
One
Any
UNAFFECTED
NULL
Same functionality !
---- With WHEN: ---------------WITH sel SELECT
x <= aWHEN "000",
b WHEN "001",
c WHEN "010",
UNAFFECTED WHEN OTHERS;
---- With CASE: ---------------CASE sel IS
WHEN "000" => x<=a;
WHEN "001" => x<=b;
WHEN "010" => x<=c;
END CASE;
Using Sequential Code to Design

Combinational Circuits
Sequential code can be used to implement
either sequential or combinational circuits
Registers are for sequential circuits necessary,
so will be inferred by the compiler
This should not happen for combinational
circuits
Also for a combinational circuit, the complete
truth-table should be clearly specified in the
code
Rules to be followed while using sequential

code for designing combinational circuits
Rule 1: Make sure that all input signals used
(read) in the PROCESS appear in its sensitivity
list
Rule 2: Make sure that all combinations of the
input/output signals are included in the code;
that is, make sure that, by looking at the code,
the circuits complete truth-table can be obtained
(indeed, this is true for both sequential as well as
concurrent code)
Failing to comply with rule 1 will generally cause

the compiler to simply issue a warning saying
that a given input signal was not included in the
sensitivity list, and then proceed as if the signal
were included. Even though no damage is
caused to the design in this case, it is a good
design practice to always take rule 1 into
consideration
With respect to rule 2, however, the
consequences can be more serious because
incomplete specifications of the output signals
might cause the synthesizer to infer latches in
order to hold their previous values
Bad Combinational Design
x should behave as a multiplexer; that is, should

be equal to the input selected by sel;
y, on the other hand, should be equal to 0 when
sel = 00, or 1 if sel = 01
LIBRARY ieee;
ENTITY example IS
PORT (a, b, c, d: IN STD_LOGIC; sel: IN INTEGER RANGE 0 TO 3;
x,y: OUT STD_LOGIC);
END example;
ARCHITECTURE example OF example IS
BEGIN
PROCESS (a, b, c, d, sel)
BEGIN
IF (sel=0) THEN
x<=a;
y<=0;
ELSIF (sel=1) THEN
x<=b;
y<=1;
ELSIF (sel=2) THEN
x<=c;
ELSE
x<=d;
END IF;
END PROCESS;
END example;
Output
Value of y remains 1 which is not expected
Cure for the problem: y<='X'; must be included for

other conditions of sel i.e. 2 & 3
Some templates for use!

process (Inputs) -- All inputs in sensitivity list
begin
... -- Outputs assigned for all input conditions
... -- No feedback
end process; -- Gives pure combinational logic
process (Inputs) -- All inputs in sensitivity list

begin
if Enable = '1' then
... -- Latched actions
end if;
end process; -- Gives transparent latches + logic
process (Clock) -- Clock only in sensitivity list

begin
if Rising_edge(Clock) then -- Test clock edge only
... -- Synchronous actions
end if;
end process; -- Gives flipflops + logic
process (Clock, Reset) -- Clock and reset only in

-- sensitivity list
begin
if Reset = '0' then -- Test active level of
-- asynchronous reset
... -- Asynchronous actions
elsif Rising_edge(Clock) then -- Test clock edge
-- only
end if;
process -- No sensitivity list

begin
wait until Rising_edge(Clock);
Implementing RAM
The circuit has a data input bus (data_in), a data output bus
(data_out), an address bus (addr), plus clock (clk) and write
enable (wr_ena) pins
When wr_ena is asserted, at the next rising edge of clk the
vector present at data_in must be stored in the position
specified by addr
The output, data_out, on the other hand, must constantly
display the data selected by addr
LIBRARY ieee;
ENTITY ram IS
GENERIC ( bits: INTEGER := 8; -- # of bits per word
words: INTEGER := 16); -- # of words in the memory
PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 TO words-1;
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
ARCHITECTURE ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='1') THEN
IF (clk'EVENT AND clk='1') THEN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= memory(addr);
END ram;
Output
data_in[7:0]
addr[3:0]
wr_ena
clk
RADDR[3:0]
[7:0]
DATA[7:0]
[7:0]
[3:0]
[3:0]
ram1
[3:0]
WADDR[3:0]
WE[0]
CLK
DOUT[7:0]
memory[7:0]
[7:0]
[7:0]
data_out[7:0]
Packages, Functions and

Procedures
R.B.Ghongade
Lecture 16,17
Fundamental units of VHDL code
COVERED SO FAR
Packages
Frequently used pieces of VHDL code are usually written
in the form of COMPONENTS, FUNCTIONS, or
PROCEDURES
Such codes are then placed inside a PACKAGE and
compiled into the destination LIBRARY
Packages allow code partitioning, code sharing, and
code reuse
Besides COMPONENTS, FUNCTIONS, and
PROCEDURES, it can also contain TYPE and
CONSTANT definitions
A package is split into a declaration and a body
The package declaration defines the external interface to
the package, the package body typically contains the
bodies of any functions or procedures defined in the
package declaration
Syntax
{declaration}
package PackageName is
Declarations...
end [package] [PackageName];
{body}
package body PackageName is
Declarations...
end [package body] [PackageName];
REMEMBER THIS !
Where a function or procedure is placed in

a package, the declaration and body must
conform, i.e. the parameters must be
identical between the two
Only definitions placed in the package
declaration are visible outside the package
Common, shared declarations of types, subtypes, constants,
procedures, functions and components are best put in a
package
A simple package
LIBRARY ieee;
PACKAGE my_package IS
TYPE state IS (st1, st2, st3, st4);
TYPE color IS (red, green, blue);
CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";
END my_package;
The example above shows a PACKAGE called my_package. It contains

only TYPE and CONSTANT declarations, so a PACKAGE BODY is not
necessary
Example
LIBRARY ieee;
TYPE state IS (st1, st2, st3, st4);
TYPE color IS (red, green, blue);
CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN;
END my_package;
PACKAGE BODY my_package IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND s='1');
END positive_edge;
END my_package;
This example contains, besides TYPE and CONSTANT

declarations, a FUNCTION.
Therefore, a PACKAGE BODY is now needed
This function returns TRUE when a positive edge occurs on clk
Any of the PACKAGES in the previous examples can

now be compiled, becoming then part of our work
LIBRARY (or any other)
To make use of it in a VHDL code, we have to add a new
USE clause to the main code
(USE work.my_package.all), as shown below:
LIBRARY ieee;
USE work.my_package.all;
ENTITY
...
...
ARCHITECTURE
...
...
Functions & Procedures

FUNCTIONS and PROCEDURES are
collectively called subprograms
They are very similar to a PROCESS , for they
are the only pieces of sequential VHDL code,
and thus employ the same sequential
statements (IF, CASE, and LOOP; WAIT is not
allowed)
PROCESS is intended for immediate use in the
main code, FUNCTIONS & PROCEDURED are
intended mainly for LIBRARY allocation, that is,
their purpose is to store commonly used pieces
of code, so they can be reused or shared by
other projects.
A FUNCTION or PROCEDURE can also be
installed in the main code itself
Functions
Used to group together executable,
sequential statements to define new
mathematical or logical functions
Also used to define bus resolution
functions, operators, and conversion
functions between data types
When defined in a package, the function
must be split into a declaration and a body
Syntax: Function Body

FUNCTION function_name [<parameter list>] RETURN data_type IS
[declarations]
BEGIN
END function_name;
<parameter list> = [CONSTANT] constant_name : constant_type ;

or
<parameter list> = SIGNAL signal_name : signal_type ;
Where :(FUNCTION DECLARATION)

package - <HERE> - end
package body - <HERE> - end
entity is - <HERE> - begin - end
architecture is - <HERE> - begin- end
block - <HERE> - begin - end
generate - <HERE> - begin - end
process - <HERE> - begin - end
function is - <HERE> - begin - end
procedure is - <HERE> - begin - end
Function Body is NOT allowed inside a Package
Rules :
The function_name may be an identifier or
an operator
Functions cannot assign signals or
variables defined outside themselves, nor
can then contain wait statements
A function must execute a return
statement
Pure functions cannot have side effects they must do nothing but return a value
There can be any number of such parameters

(even zero), can only be CONSTANT (default)
or SIGNAL (VARIABLES are not allowed).
Their types can be any of the synthesizable
data types (BOOLEAN,STD_LOGIC,
INTEGER, etc.)
No range specification should be included
(for example, do not enter RANGE when
using INTEGER, or TO/DOWNTO when using
STD_LOGIC_VECTOR)
On the other hand, there is only one return
value, whose type is specified by data_type
REMEMBER THIS !
The return type must be a name; it cannot

include a constraint
Variables defined inside a function are
initialized each time the function is called
The declaration and body must conform,
i.e. the parameters and return type must
be identical between the two
The function declaration ends with a ";",
whereas the function body has is at the
corresponding point in the syntax
Synthesis :
Each call to a function is synthesized as a separate
block of combinational logic
Example :
FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)
RETURN BOOLEAN IS
BEGIN
END f1;
The function, named f1, receives three parameters (a, b, and c)

a and b are CONSTANTS (notice that the word CONSTANT can be
omitted, for it is the default object), while c is a SIGNAL.
a and b are of type INTEGER, while c is of type STD_LOGIC_VECTOR
Notice that neither RANGE nor DOWNTO was specified.
The output parameter (there can be only one) is of type BOOLEAN
Function Call
A function is called as part of an expression. The
expression can obviously appear by itself or
associated to a statement (either concurrent or
sequential)
Examples of function calls:
x <= conv_integer(a); -- converts a to an integer
-- (expression appears by
-- itself)
y <= maximum(a, b); -- returns the largest of a
-- and b
-- (expression appears by itself)
IF x > maximum(a, b) ... -- compares x to the
-- largest of a, b
-- (expression associated to a
-- statement)
Function positive_edge( )
The FUNCTION below detects a positive
(rising) clock edge.
It is similar to the
IF (clkEVENT and clk = 1) statement
------ Function body: ----------------------------FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN
BOOLEAN IS
BEGIN
RETURN (s'EVENT AND s='1');
END positive_edge;
------ Function call: ----------------------------...
IF positive_edge(clk) THEN...
...
Function locations
PACKAGE
+
(PACKAGE BODY)
LIBRARY
FUNCTION/PROCEDURE
LOCATION
ENTITY
MAIN CODE
ARCHITECTURE
DECLARATIVE
PART
Though a FUNCTION is usually placed in a

PACKAGE (for code partitioning, code reuse,
and code sharing purposes), it can also be
located in the main code (either inside the
ARCHITECTURE or inside the ENTITY)
When placed in a PACKAGE, then a

PACKAGE BODY is necessary, which must
contain the body of each FUNCTION (or
PROCEDURE) declared in the declarative
part of the PACKAGE
FUNCTION Located in the Main Code

LIBRARY ieee;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);
END dff;
ARCHITECTURE my_arch OF dff IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC)
RETURN BOOLEAN IS
BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d;
END IF;
END PROCESS;
END my_arch;
FUNCTION Located in a PACKAGE

LIBRARY ieee;
FUNCTION positive_edge(SIGNAL s:
STD_LOGIC) RETURN BOOLEAN;
END my_package;
FUNCTION positive_edge(SIGNAL s: STD_LOGIC)
RETURN BOOLEAN IS
BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;
END my_package;
LIBRARY ieee;
WORK DESIGN SPACE

SHOULD BE VISIBLE TO
THE TOP-LEVEL ENTITY
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE my_arch OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d;
END IF;
END PROCESS;
END my_arch;
Function conv_integer( )
conv_integer( ) function converts

a STD_LOGIC_VECTOR value
into an INTEGER value
LIBRARY ieee;
FUNCTION conv_integer (SIGNAL vector:
STD_LOGIC_VECTOR) RETURN INTEGER;
END my_package;
FUNCTION conv_integer (SIGNAL vector:
STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result: INTEGER RANGE 0 TO 2**vector'LENGTH-1;
BEGIN
IF (vector ( vector'HIGH )='1') THEN result:=1;
ELSE result:=0;
END IF;
FOR i IN (vector'HIGH-1) DOWNTO (vector'LOW) LOOP
result:=result*2;
IF(vector(i)='1') THEN result:=result+1;
END IF;
END LOOP;
RETURN result;
END conv_integer;
END my_package;
Algorithm
3
vectorLENGTH=4
vectorHIGH=3
vector ( vector'HIGH )= 0
vector
Since vector ( vector'HIGH )= 0
result=0
Iteration 1:
3 downto 0 ( i = 2 to start with )

result= 0 x 2
result= 0 + 1
since vector(2)= 1
( i = 1)
Iteration 2:
result= 1 x 2
result= 2 + 0
since vector(1)= 0
( i = 0)
Iteration 3:
result= 2 x 2
result= 4 + 1
RETURNED : result = 5
since vector(0)= 1
LIBRARY ieee;
ENTITY conv_int2 IS
PORT ( a: IN STD_LOGIC_VECTOR(0 TO 3);
y: OUT INTEGER RANGE 0 TO 15);
END conv_int2;
ARCHITECTURE my_arch OF conv_int2 IS
BEGIN
y <= conv_integer(a);
END my_arch;
PROCEDURE
A PROCEDURE is very similar to a FUNCTION
and has the same basic purposes
A procedure can return more than one value
Like a FUNCTION, two parts are necessary to
construct and use a PROCEDURE:
the procedure itself (procedure body)
procedure call
Procedure Body
PROCEDURE procedure_name [<parameter list>] IS
[declarations]
BEGIN
END procedure_name;
<parameter list> = [CONSTANT] constant_name: mode type;

<parameter list> = SIGNAL signal_name: mode type;
<parameter list> = VARIABLE variable_name: mode type;
A PROCEDURE can have any number of IN, OUT, or

INOUT parameters, which can be SIGNALS,
VARIABLES, or CONSTANTS. For input signals
(mode IN), the default is CONSTANT, whereas for
output signals (mode OUT or INOUT) the default is
VARIABLE
WAIT, SIGNAL declarations, and COMPONENTS are
not synthesizable when used in a FUNCTION. The
same is true for a PROCEDURE, with the exception
that a SIGNAL can be declared, but then the
PROCEDURE must be declared in a PROCESS.
Moreover, besides WAIT, any other edge detection is
also not synthesizable with a PROCEDURE (that is,
contrary to a function, a synthesizable procedure
should not infer registers)
Example
PROCEDURE my_procedure ( a: IN BIT; SIGNAL b,
c: IN BIT;
SIGNAL x: OUT BIT_VECTOR(7 DOWNTO 0);
SIGNAL y: INOUT INTEGER RANGE 0 TO 99) IS
BEGIN
...
END my_procedure;
The PROCEDURE has three inputs, a, b, and c (mode IN)

a is a CONSTANT of type BIT, while b and c are SIGNALS, also
of type BIT. Notice that the word CONSTANT can be omitted
for input parameters, for it is the default object (recall,
however, that for outputs the default object is VARIABLE)
There are also two return signals, x (mode OUT, type
BIT_VECTOR) and y (mode INOUT, type INTEGER)
Procedure Call
Contrary to a FUNCTION, which is called as
part of an expression, a PROCEDURE call is a
statement on its own
It can appear by itself or associated to a
statement (either concurrent or sequential)
Examples of procedure calls:
compute_min_max(in1, in2, 1n3, out1, out2);
-- statement by itself
divide (dividend, divisor, quotient, remainder);
-- statement by itself
IF (a>b) THEN compute_min_max(in1, in2, 1n3,
out1, out2);
-- procedure call
-- associated to another
-- statement
Test benches in VHDL
R.B.Ghongade
Lecture 18,19
Copyright, R.B.Ghongade
Introduction
A design is always incomplete without
verification
There are several ways to verify VHDL
designs
Test benches are one of them
Test benches are also called Test cases
A testbench is an environment, where a

design ( called design or unit under test
UUT) is checked by applying signals
(stimuli) and monitoring its responses by
signal probes and monitors.
Thus
a testbench substitutes the
designs environment in such a way that
the behaviour of the design can be
observed and analyzed.
A testbench always consists of following

elements:
a socket for the unit under test (UUT)
a stimuli generator (a subsystem that
applies stimuli to UUT, either generating
them internally or reading from an
external source)
tools for observing UUT responses to the
stimuli
Concept of Testbench
Elements of a VHDL Test Bench

A VHDL test bench is just another specification with
its own entity and architecture
It has, however, a special structure with some
elements that are characteristic to this type of
specification:
Test bench entity has no ports,
UUT component instantiation - the relationship
between the test bench and UUT is specified through
component instantiation and structural-type
specification,
stimuli - it is a set of signals that are declared
internally in the test bench architecture and assigned
to UUT's ports in its instantiation. The stimuli are
defined as waveforms in one or more behavioral
processes.
Using Test Benches

The design must be verifiable.
It is much more convenient to use a test bench for
design verification.
Writing a test bench may be a very complex task
hence it is desired to write some guidelines for future
stimuli development as you progress with the design.
It is the test bench which is simulated, not the unit
under test.
The UUT is only one of the components instantiated
in a test bench.
There is no limitation on the test bench size.
The only limitation is the VHDL simulator used
capability.
Writing
stimuli
can be
performed
Simulation
of the
test bench
is the
last
DESIGN phaseconcurrently
with
of a design process.
Here youwriting
specifications
fortoeach
new design
will receive
an answer
the question;
When
stimuliThe
are specified,
aset
test should
block.
stimuli
Design
Specification
"does the system behave as
bench
specification
can
be written
contain
such
set
of
input
(and state)
expected?"
Remember
that
the
answer
It will
contain
the stimuli
and an as much
signal
values
that
covers
received
from simulating
test bench is
instantiation
of
the
designed
realonly
life
situations
asdetermined
possible.
The design
process
consists
of design
and
VERIFICATION
reliable
to
the
extent
under test).
It isfirst
the one is
verification system
phases (unit
The objective
of the
bytest
thebench
test bench
accuracy
and
and
not
design
that
will the
to create a new VHDL specification that
meets
coverage
area. during
The better
a test bench
be simulated
the verification
Stimuli
Definitions
system requirements.
is,phase.
the more confident you can be that
your system is properly designed.
Test bench Specifications

Test bench Simulation
Example : Multiplexer
Example : J-K FlipFlop
Closer look at Testbench

UUT: 2- bit Multiplexer
Testbench
Waveforms
Testbench : Using assertreport
Waveforms
Error Report
SUMMARY
A Test bench thus is an effective builtin tool for verifying VHDL designs
Troubleshooting becomes easier and
faster because of the ASSERTREPORT
clause
Automation of verification is possible
because of the seamless integration of
language elements.
THANK YOU!!!
SIMULATION ISSUES
R.B.Ghongade
Lecture 20,21,22
SIMULATION ISSUES
SIMULATION
SIMULATION PROCESS
DELAY MODELING
TYPES OF SIMULATION
Simulation
Simulation is a functional emulation of a
circuit design through software programs,
that use models to replicate how a device
will perform in terms of timing and results
Simulation
Simulation eliminates the time-consuming
need for constant physical prototyping
Simulation can be performed during ALL
stages of verification
Motivation of simulation comes from the
need to verify that the HDL code is
correctly implementing the design
Simply verify that the design meets its
required specification
Flavours of Simulation
Functional Simulation: Is functional verification
of the design without any delays
Pre- Layout simulation: Is functional verification
of the design including logic cell delays
Post- Layout simulation: Is performed after
physical place and route( interconnect delays are
taken into account)
Simulation at different Levels
0
a1 Vcc1 b1
a2
b2
a3
b3
a4 GND b4
0
1
2
3
4
0
1
2
3
4
a1
Vcc1
b1
a2
b2
a3
b3
a4
GND
b4
5
6
7
1
2
3
4
0
a1 Vcc1 b1
a2
b2
a3
b3
a4 GND b4
0
5
6
7
8
1
2
3
4
0
a1 Vcc1 b1
a2
b2
a3
b3
a4 GND b4
0
5
6
7
8
Register
5
6
7
8
Q1
Q4
ENB
Long card
Module
Subsystem
Chip
System
Comparison for simulation

Module
Difficult
Higher
Subsystem
Chip
Stimuli Development
Easier
Simulation Efficiency
Low
Nature of detected problems

Low level
Low
Early
System
Bug correction time

Time in project
All kinds
Higher
Late
Steps in simulation
ELABORATION
INITIALISATION
EXECUTION
Steps in Simulation
COMPILATION
* Checks VHDL source code to check syntax and
semantic rules of VHDL
* If a syntax or semantic error occurs, then the
compiler flags off an error message
* Else the compiler generates an intermediate
MECHANISM
code
SEMANTICS
SCIENCE OF
MEANING
SYNTAX
OF
LANGUAGE
Steps in Simulation
cont...
ELABORATION
* Ports are created for each instance of a
component
* Memory storage is allocated for the required
signal
* Interconnections among the port signals are
specified
* Mechanism is established for executing the
VHDL process in proper sequence
Steps in Simulation
cont...
INITIALIZATION
* Initial values preset in the declarations
statements are assigned to signals/variables
Steps in Simulation
cont...
EXECUTION
* Every process is executed until it suspends.
Signal values are updated only after this.
* Simulator accepts simulation commands
like: RUN, ASSIGN,WATCH , which
control the simulation of the system
* Simulation ends when all signals have been
updated and new values have been assigned
to the signals
SIMULATION PROCESS
BASIC DEFINITIONS
EVENT
A CHANGE ON COMPONENT OUTPUT THAT
WILL BE PROPAGATED
TRANSACTION
A CHANGE ON COMPONENT INPUT THAT
DOES NOT PROPAGATE
SIMULATION PROCESS
BASIC DEFINITIONS
cont.
SCHEDULING
FUTURE EVENTS GENERATED BY
EVALUATION OF A PROCESS
EVALUATION
CALCULATING THE OUTPUTS OF
COMPONENTS BASED ON INPUTS AND
CURRENT STATE
SIMULATION PROCESS
Time Jargon
Real Time
(As it happens)
Simulation Time
(Relative to some arbitrary t=0)
SIMULATION PROCESS
Simulation executes as follows:
At t=0 , all gate outputs are set to an unknown value
Two queues are set up
SIGNALS TO BE UPDATED
PROCESSES TO BE EXECUTED
SIMULATION PROCESS
When Simulation time is incremented :
Signal is updated
All processes sensitive to that signal are
placed on the process execution queue
One loop is
called DELTA
CYCLE
Each resumed process is executed until it suspends

Effects of the logic changes that have
occurred as a result of process execution
are evaluated
Simulation time is set to the next event in queue or
halted if simulation time gets exhausted
SIMULATION DELTA
What is simulation delta?
Several logic changes occur simultaneously in a circuit
(concurrent operations)
But simulator being run by a sequential machine,
hence it cannot process events concurrently.
To take care this, time is frozen within the simulator.
The real time the simulator takes to complete all
concurrent operations in the queue is called
SIMULATION DELTA
SIMULATION DELTA
Zero simulation time
t=0 ns
t=1 ns
t=2 ns
t=3 ns
t=4 ns
Many delta cycles can occur
Real Time
The minimum time interval possible for the simulator is

assumed to be 1 ns here
SIMULATION DELTA
SUMMARY
Simulation deltas allow ordering of events that occur
at the same simulation time during simulation
Simulation deltas are infinitesimal amount of time used
as synchronism mechanism when zero delay events are
present
DELAY MODELING
Delays are timing parameters given by the user for
modeling physical characteristics of hardware
Types of delays
INERTIAL DELAY
TRANSPORT DELAY
Delays are specified in signal assignment statements only

Delays should NOT be used in variable assignments
INERTIAL DELAY
It is used to model the inherent inertia of
physical devices
Example:
The input value must be stable for a specified
minimum pulse duration before the value is
allowed to propagate to the output
If the input is not stable for the specified limit,
no output change occurs
TRANSPORT DELAY
It represents pure propagation delay i.e.,
wires and interconnect delays
Signal value is assigned with a specified
delay independent of the width of the input
waveform
DELAYS
10 ns
X
3 ns
6 ns
10 ns
2 ns
Z1
Z2
Z3
TYPES OF SIMULATION
BEHAVIORAL SIMULATION
STATIC TIMING SIMULATION
GATE-LEVEL SIMULATION
SWITCH-LEVEL SIMULATION
TRANSISTOR-LEVEL OR CIRCUITLEVEL SIMULATION
TYPES OF SIMULATION
It ignores timing aspects
Verifies only the functionality of the design
BEHAVIORAL SIMULATION
A given functionality is modeled using HDL
Timing aspects are considered
TYPES OF SIMULATION
STATIC TIMING SIMULATION
A built in tool that computes delay for each
timing path
Does not require input stimuli
GATE-LEVEL SIMULATION
Is used to check the timing performance of design
Delay parameters of logic cells are used to
verify things
TYPES OF SIMULATION
SWITCH-LEVEL SIMULATION
Is one level below the gate level simulation
It models transistors as switches
It provides more accurate timing predictions
than gate-level simulation
TYPES OF SIMULATION
TRANSISTOR-LEVEL SIMULATION
Requires transistor models. Circuit is described in
terms of resistances, capacitances and voltage and
current sources
A set of mathematical equations relating current and
voltages is setup and solved numerically
Gives analog results and is most accurate
Requires large amount of computing resources
And finally!!
Simulation time depends on :
Simulation levels of logic
Physical Memory of PC
Speed of PC
THANK YOU !!!
State Machine Design with

VHDL
R.B.Ghongade
Lecture 23,24,25,26
State Machines
Finite state machines (FSM) constitute a
special modeling technique for sequential
logic circuits.
Such a model can be very helpful in the
design of certain types of systems,
particularly those whose tasks form a welldefined sequence
Examples are : counters, digital
controllers, sequence generators/
detectors etc
Basic categories of state machines

State
Machine
Clocked
Synchronous
Circuits
Multiple Inputs can
change at arbitrary
times and so the
output but state
changes only on clock
Feedback
Sequential
Circuits
Inputs can
change one at a
time
Combinational
+
Sequential ( Memory)
Asynchronous
Circuits
Clock-less
machines
Absence of F/F
Combinational ckts
with feedback
Types of state machines
Outputs depend
on STATE and
INPUTS
INPUTS
NEXT STATE
LOGIC
EXCITATION
STATE
MEMORY
CURRENT STATE
OUTPUT
LOGIC
OUTPUTS
CLOCK INPUT
Outputs depend
on STATE only
CLOCK SIGNAL
MEALY MACHINE
INPUTS
NEXT STATE
LOGIC
EXCITATION
STATE
MEMORY
CURRENT STATE
OUTPUT
LOGIC
OUTPUTS
CLOCK INPUT
Typically edgetriggered D F/Fs

CLOCK SIGNAL
MOORE MACHINE
Moore & Mealy Machines

These are basic topologies for state machines
In theory, both machines are equivalent, so one can
convert a synchronized digital hardware design from
a Mealy to a Moore state machines or vice versa
The Moore state machine generates output based
only on its current state hence the Moore machine
output is usually synchronized with the system clock
or the clock edge of the output D flip flop (the delay
element)
In the Mealy machine, because output depends on
both the input and current state, output will change
whenever the input changes. In other words, in the
Mealy system, when output is released at a clock
edge, the input is usually latched and considered
prior to the release of latched output
Moore & Mealy Machines cont..

Because the Mealy machine outputs based on
the input and the current state, the correct
initiating output process in a Mealy machine is
first to change the input value. Due to the
dependency of input and the current state,
Mealy machine output changes next. However,
the change at the input will also trigger the
change at the machine state At last, the output
will change again due the new state
Moore machine output coincide with the state
change
Mealy machine example

0/0
1/0
Low
High
0/0
1/1
Rising Edge Detector
There are two states in the state machine: HIGH and

LOW Notation x/y next to an arc between states stands
for input/output values during the state transition
The machine advances to the next state when it sees an
input x
In mean time, the machine also outputs y
State Table
Present
State
Next State
Output
Input
Input
0
1
LOW
LOW HIGH
HIGH
LOW HIGH
Timing diagram
1/0
HIGH
clk
input
0/0
1/1
present state
LOW
output
0/0
1/1, LOW
Input :
1001
Output :
00
101
Present State :
H
H
LL
0/0, LOW
1/1, HIGH
0/0, LOW
0/0, HIGH
1/0, HIGH
Excitation Table
Present
State(S)
Input
(I)
Next State
(S*)
Output
(O)
Design
K-map for Next Sate (S*)
I
S
S* = I
K-map for Output (O)
I
S
O = S. I
Using D F/F
Characteristic Equation for D F/F is Q* = D
I
S*
S
D
Q
D F/F
CLK
VHDL Code
library IEEE;
entity edge_det is port (
reset, clk, input: in bit;
output: inout bit;
mea_output: out bit );
end edge_det;
architecture edge_det of edge_det is

type StateType is (LOW, HIGH);
signal present_state, next_state: StateType;
begin
state_machine: process(present_state) begin
case present_state is
when LOW => if (input='0') then
next_state <= LOW;
else
next_state <= HIGH;
end if;
when HIGH => if (input='0') then
next_state <= LOW;
else
next_state <= HIGH;
end if;
end case;
end process state_machine;
state_clocking: process(clk) begin

if (clk'event and clk='1') then
present_state <= next_state;
mea_output <= output;
end if;
end process state_clocking;
mealy_output: process(input, present_state) begin
if (present_state=LOW and input='1') then
output <= '1';
else
output <= '0';
end if;
end process mealy_output;
end edge_det;
Actual output & Inference
reset
clk
input
D[0]
Q[0]
D[0]
Q[0]
mea_output
present_state[0]
mealy_output.un6_present_state
mea_output
output
Sequence Detector
A state machine is to be designed to
detect a sequence such that :
X=1 , X=0, X=1, X=0
The machine will generate high output
only when it detects the proper sequence
After testing is complete it starts all over
again
State Diagram
1/0
0/0
Output
High
1/0
0/0
A
00
1/0
B
01
0/0
C
10
1/0
D
11
0/1
State Table
P_S
A
B
C
D
00
01
10
11
N_S
X=0
X=1
00
01
10
00
00
11
11
00
OUTPUT
X=0
X=1
0
0
0
0
0
0
1
0
Excitation Table
0
1
2
3
4
5
6
7
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
A*
0
0
1
0
0
1
1
0
B*
0
1
0
0
0
1
1
0
Y
0
0
0
0
0
0
1
0
K-map minimization
K-map for Next Sate (A*)
BX
00
01
11
10
A
0
1
0
0
0
4
0
1
1
5
0
0
3
7
1
1
2
6
K-map for Next Sate (B*)
BX
00
01
11
10
A
0
1
0
04
1
1
1
5
0
0
3
7
0
6
1
00
01
11
10
B* = BX + ABX
K-map for Next Sate (Y*)
BX
A* = BX + ABX
0
04
0
0
1
5
0
0
3
7
0
16
Y = ABX
Hardware implementation
A
B
X
DA
QA
D F/F
(A)
A
B
X
DB
QB
D F/F
(B)
B
X
A
B
X
CLK
VHDL implementation
library IEEE;
entity sd is
port(
x ,clk: in STD_LOGIC;
y : out STD_LOGIC;
temp : inout STD_LOGIC
);
end sd;
architecture sd of sd is
type StateType is (A, B,C,D);
begin
state_machine: process(present_state) begin
when A =>
if (x='1') then
next_state
else
next_state
end if;
when B =>
if (x='1') then
next_state
else
next_state
end if;
when C =>
if (x='1') then
next_state
else
next_state
end if;
when D =>
if (x='1') then
next_state
else
next_state
end if;
end case;
<= B;
<= A;
<= A;
<= C;
<= D;
<= A;
<= A;
<= D;
state_clocking: process(clk)
begin
if (clk'event and clk='1') then
y <= temp;
end if;
mealy_output: process(x, present_state)
begin
if (present_state=D and x='0') then
temp <= '1';
else
temp<= '0';
end if;
end sd;
Timing diagram
Incorrect sequence
leads to state A (00)
Correct sequence
generates Y=1
[0]
[1]
Synthesis result
state_machine.next_state16
next_state_0_sqmuxa_1
clk
[0]
[1]
01
e
d
00
e
d
00
e
d
10
e
d
[0]
[1]
11
e
d
00
e
d
00
e
d
[1:0]
[1:0]
D[1:0]
Q[1:0]
[0]
[1]
[1:0]
present_state[1:0]
next_state_1_sqmuxa
D[0]
Q[0]
11
d
next_state[1:0]
temp
x
next_state_0_sqmuxa
Mealy State Machine Design Procedure #1

Construct entity with : input, output, reset, clk,
inout (required for temporary storage)
(As far as possible use bit type)
Declare states : (A,B,C,D)

Declare signal : present_state, next_state
(all declarations between : architecturebegin )
Simulate only after synthesis
library IEEE;
entity SM is
port(.. );
end SM;
architecture SM of SM is
begin
state_machine: process (present_state)
begin
when A =>
if (input condition) then
next_state <= B;
else
next_state <= A;
Use when
end if;
others as
when B =>
last case
next_state <= C;
else
next_state <= B;
end if;
when others =>
end case;
next_state <= A;
state_clocking: process (clk)

begin
if (reset='1') then
present_state<= A;
elsif (clk'event and clk='1') then
output <= inout;
end if;
mealy_output: process (input, present_state)
begin
if (present_state and input condition) then
inout <= '1';
else
inout <= '0';
end if;
end SM;
This style is called three process coding
Vending machine problem

A state machine is to be designed for
cold-drink vending machine
The machine accepts Re. 1 , Rs. 2, Rs. 5
coins , one coin at a time
Only after a total of Rs. 5 is reached the
machine will release the cold-drink bottle
and then return back to wait for next
transaction
State Diagram
a3
a2
a1
001/0
001/0
001/0
001/0
001/1
010/0
010/0
a4
010/1
001/0
001/0
ab1
Start
term
010/1
010/0
b1
b2
001/1
010/0
100/1
000/0
Rs.5
0/1
Rs.2
0/1
Re.1
0/1
OP
0/1
E.g. : 010/1 means

Rs. 2 coin is
inserted and output
becomes 1
VHDL code
library IEEE;
entity vms is
port( clk, rst : in bit;
inp : in bit_VECTOR(2 downto 0);
rel : out bit
);
end vms;
architecture vms of vms is
type StateType is
start,a1,a2,a3,a4,ab1,b1,b2,term);
signal ps, ns: StateType;
signal temp:bit;
begin
state_machine: process(ps,inp) begin
case ps is
--start
when start => if (inp="001") then
ns <= a1;
temp<='0';
elsif (inp="010") then
ns <= b1;
temp<='0';
ns <= term;
temp<='1';
else
ns <= start;
temp<='0';
end if;
--a1
when a1 => if (inp="001") then
ns <= a2;
temp<='0';
ns <= ab1;
temp<='0';
else
ns <= a1;
temp<='0';
end if;
--a2
ns <= a3;
temp<='0';
ns <= a4;
temp<='0';
else
ns <= a2;
temp<='0';
end if;
--a3
ns <= a4;
temp<='0';
ns <= term;
temp<='1';
else
ns <= start;
temp<='0';
end if;
--a4
ns <= term;
temp<='1';
else
ns <= a4;
temp<='0';
end if;
--ab1
when ab1 => if (inp="010") then
ns <= term;
temp<='1';
ns <= a3;
temp<='0';
else
ns <= ab1;
temp<='0';
end if;
--b1
when b1 => if (inp="010") then
ns <= b2;
temp<='0';
ns <= a3;
temp<='0';
else
ns <= b1;
temp<='0';
end if;
--b2
when b2 => if (inp="001") then
ns <= term;
temp<='1';
else
ns <= b2;
temp<='0';
end if;
when term =>
ns <= start;
temp<='0';
when others =>
ns<=start;
temp<='0';
end case;
state_clocking: process(clk,rst) begin

if (rst='1') then
ps<=start;
elsif (clk'event and clk='1')then
ps <= ns;
rel <= temp;
end if;
end vms;
Results
Mealy State Machine Design Procedure #2

Construct entity with : input, output,
reset,clock , (As far as possible use bit type)
Declare states : (A,B,C,D)
Declare signal : present_state, next_state
Declare signal : temp (same size as output)
(all declarations between : architecturebegin )
library IEEE;
entity SM is
port(.. );
end SM;
architecture SM of SM is
signal present_state, next_state: StateType; signal temp: bit;
begin
state_machine: process (present_state,input)
begin
when A =>
next_state <= B;
temp <= 1;
else
next_state <= A;
temp <= 0;
end if;
when B =>
next_state <= C;
temp <= 0;
else
next_state <= B;
temp <= 1;
end if;
when others =>
next_state <= A;
end case;
Additional
assignment
statement
state_clocking: process (clk)

begin
if (reset='1') then
present_state<= A;
output <= temp;
end if;
end SM;
This style is called two process coding
Two types of outputs

Output is not
stored hence do
not use temp
signal for output
assignment
Direct output
assignment
Output is stored hence

use temp signal for
output assignment
Moore machine design

The Moore state machine generates output
based only on its current state hence the
Moore machine output is usually
synchronized with the system clock or the
clock edge of the output D flip flop (the
delay element)
In VHDL the design procedure is nearly the
same as Mealy machine, hence Design
Template #2 will be used
BCD counter
State Diagram
reset
ONE
TWO
THREE
FOUR
0001
0010
0011
0100
ZERO
FIVE
0000
0101
NINE
EIGHT
SEVEN
SIX
1001
1000
0111
0110
VHDL code
library IEEE;
entity bcd is
port(
clk : in bit;
reset : in bit;
d : out bit_vector(3 downto 0)
);
end bcd;
architecture bcd of bcd is

type state_type is (zero,one,two,three,four, five,
six,seven, eight,nine);
signal ps,ns: state_type;
begin
state_machine: process(ps)
begin
case ps is
when zero =>
d<="0000"; ns<= one;
when one =>
d<="0001";ns<= two;
when two =>
d<="0010";ns<= three;
when three =>
d<="0011";ns<=four;
when four =>
d<="0100";ns<= five;
when five =>
d<="0101";ns<=six;
when six =>
d<="0110";ns<= seven;
when seven =>
d<="0111";ns<=eight;
when eight =>
d<="1000";ns<= nine;
when nine =>
d<="1001";ns<=zero;
end case;
clocking:process(clk,reset)
begin
if (reset='1') then
ps<= zero;
ps<=ns;
end if ;
end process clocking;
end bcd;
Simulation Output
State machine design using statediagram entry

Active-HDL supports the design entry via
three methods
HDL code
Block diagram
State diagram
After state-diagram is compiled VHDL

code is generated automatically
We shall explore this method to design the
BCD counter
Usual port declaration using wizard
State
Reset
condition
State condition
Transition
(for Mealy , use
condition here)
Generated VHDL code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd is
port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
d: out STD_LOGIC_VECTOR (3 downto 0));
end bcd;
architecture bcd_arch of bcd is

-- USER DEFINED ENCODED state machine: ctr
attribute enum_encoding: string;
type ctr_type is (
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10
);
attribute enum_encoding of ctr_type: type is
"0000 " &
-- S1
"0001 " &
-- S2
"0010 " &
-- S3
"0011 " &
-- S4
"0100 " &
-- S5
"0101 " &
-- S6
"0110 " &
-- S7
"0111 " &
-- S8
"1000 " &
-- S9
"1001" ;
-- S10
signal ctr: ctr_type;
begin
----------------------------------------------------------- Machine: ctr

---------------------------------------------------------ctr_machine: process (clk)
begin
if clk'event and clk = '1' then
if reset='1' then
ctr <= S1;
-- Set default values for registered outputs/signals and
-- for variables...
else
-- Set default values for registered outputs/signals and
-- for variables
case ctr is
when S1 =>
ctr
when S2 =>
ctr
when S3 =>
ctr
when S4 =>
ctr
<= S2;
<= S3;
<= S4;
<= S5;
when S5 =>
ctr <= S6;
when S6 =>
ctr <= S7;
when S7 =>
ctr <= S8;
when S8 =>
ctr <= S9;
when S9 =>
ctr <= S10;
when S10 =>
ctr <= S1;
when others =>
null;
end case;
end if;
end if;
end process;
-- signal assignment statements for combinatorial outputs

-- d_assignment:
d <= "0000" when
"0001" when
"0010" when
"0011" when
"0100" when
"0101" when
"0110" when
"0111" when
"1000" when
"1001" when
"0000";
end bcd_arch;
(ctr
(ctr
(ctr
(ctr
(ctr
(ctr
(ctr
(ctr
(ctr
(ctr
=
=
=
=
=
=
=
=
=
=
S1) else
S2) else
S3) else
S4) else
S5) else
S6) else
S7) else
S8) else
S9) else
S10) else
Functional simulation output
After synthesis
statemachine
reset
clk
I[0]
C
R
Q[9:0]
ctr[0:9]
[0:9]
[9]
0000
e
d
[8]
0001
e
d
[7]
0010
e
d
[6]
0011
e
d
[5]
0100
e
d
[4]
0101
e
d
[3]
0110
e
d
[2]
0111
e
d
[1]
1000
e
d
[0]
1001
e
d
[0:3]
[0:3]
un10[0:3]
d[3:0]
Post-synthesis simulation output
Note that state coding is

one-hot
Next class
Synthesis Issues
Synthesis Issues
R.B.Ghongade
Lecture 27,28
Agenda
What is synthesis ?
Synthesis Tools : Expectations
Synthesis Tools : Features
Hardware modeling examples
Good coding Practices
Synthesis guidelines
What is synthesis ?
Synthesis is an automatic process that
converts users hardware description into
structural logic description
When we use VHDL as textual file, the
process is called VHDL Synthesis
Synthesis is a means of converting HDL
into real world hardware
Synthesis tools generate a gate-level
netlist for the target technology
What is synthesis ?
SYNTHESIS = TRANSLATION + OPTIMIZATION
x <= ( a and b ) or ( c and d );
a
a
x
x
c
d
c
d
LUT
c
d
Synthesis is target device technology specific

Synthesizer will try to use the best architectural
resource available with the target
Several steps work out behind the

scene!
Translation
Optimization
Hardware
Description - written
with hardware in
mind
Mix of Boolean ,
other operations
and memory
elements
Mapping
Gate Level
Technology
Specific
Translation ( language synthesis ) : Design at higher level

of description is compiled into known language elements
Optimization : Algorithms are applied to make the design
compact and fast
Design is mapped using architecture specific techniques
Synthesis process design flow

HDL behavioral description
Netlist
RTL Synthesis
RTL Optimization
Logic extraction
High-level
description with
Boolean equations
Structured
Boolean equations
Logic Optimization
Structured
Boolean equations
Technology mapping
Gate-level
optimization
Optimized Netlist
Synthesis process
Translation : Inputs are transformed into a description based

Boolean equations
If the input data consists of gate level netlist than it is
necessary to extract Boolean equations to determine
functionality of all used gates
Technology independent logic optimization: This process aims
to improve structure of Boolean equations by applying rules of
Boolean algebra . This removes the redundant logic and
reduces the space requirement
Technology Mapping: This is the process of transforming
technology independent netlist into technology dependent one.
During mapping , timing and area information of all usable
gates of the target technology must be available. It is split into
two phases
Flattening
Structuring
Flattening
The aim is to generate Boolean equations for each
output of module in such a way that the output value is a
direct function of inputs. These equations reflect two
level logic in SOP form.
Resulting equations do not imply any structure
Good optimization results are obtained
Caution: In case of structured logic this process would
destroy the characteristic structure and its associated
properties . e.g. carry look ahead adder
Flattening cannot be applied to every logic circuit
because the number of product terms may become very
large
Structuring
New intermediate variables are inserted
during the structuring process
E.g. If (A.B.C) occurs 10 times then the
tool may assign X= (A.B.C) and use X
everywhere
Finally , the sub-functions are substituted
into original equations
Compared to the logic before structuring,
the resulting area is reduced
Synthesis process- review

CONSTRAINT(area , speed)
LIBRARIES
DESIGN
SYNTHESIS
NETLIST
Translation process
converts RTL to a Boolean
form
Optimization is done on the
converted Boolean
equations
Optimized logic is mapped
to technology library
REPORT
Flattening is a process where all the design hierarchy is

removed, the entire design is transformed into a flat , generic ,
SOP form
Structuring is the opposite of flattening, its adds structure to the
generic design by extracting common logic factors and
representing them as intermediate nodes to produce compact
logic
Synthesis tool : expectations

A good synthesis tool should
perform technology specific optimizations i.e. vendor
specific FPGAs and CPLds
have best optimization techniques
allow designer control
have broad language coverage
provide user friendly debugging environment
have fast compile times
provide clean and seamless link with backend tools
Synthesis Tools - features

Tool cost depends on features provided by it
Desirable features are:
Replicating the logic
Duplicate flip-flops, remove unused logic
optimization across design hierarchy
resource sharing of adders , incrementors,
multipliers
automatic RAM inference (RAM logic is
automatically mapped to technology specific
RAM cells)
Replicate logic
Replicate logic to
meet fan-out
demands
E.g. WR may be
connected to 100
points hence add
buffers to split
internally
BUF
BUF
BUF
BUF
BUF
BUF
Duplicating logic
We can duplicate the logic which generates the
signal , for minimizing fan-out
Trade-off : Loading effect of signals is reduced
hence lowering propagation delay but at the
cost of logic and interconnect complexity
D
Resource sharing
Some synthesis tools automatically perform a
limited amount of resource sharing ( for
arithmetic expressions that are mutually
exclusive)
Consider the code:
ADDSEL: process( sel, a ,b,c,d)
begin
if (sel=1 ) then
y<= a + b ;
else
y<= c + d ;
end if ;
end process ADDSEL ;
Resource sharing
a
a
c
+
+
b
y
d
sel
sel
Before resource
sharing
After resource
sharing
An adder requires more floor space than a multiplexer
Simulation vs. Synthesis

Some simulation constructs are not
supported by synthesis tools
e.g. wait statements
Synthesis tools ignore initial values

Care should be taken so that simulationsynthesis mismatch does not occur
Using Signals or Variables

Variables are used only for convenience of
describing behaviour
Variables are used and declared in a process
however it cannot be used to communicate
between processes
Variable assignments are done immediately and
are executed sequentially
Variables may or may not represent physical
wires
Signal assignments are done at the end of
process
Signals represent physical wires in the circuit
Using Signals or Variables

Use variables in combinational processes
because there is less simulation overhead
Order dependency
Signal assignments are order independent
Variable assignments are order dependent
Signal assignments under a clocked process are
translated into registers
Variable assignments under a clocked process may
or may not be translated into registers
Signals or Variables
process (clk, a, b, c, d)
variable y, x, w : std_logic ;
begin
if (clk=1 and clkevent) then
z1<= y ;
variables are read
y : = x ;
before being written
x : = a and b ;
to , this infers a
w : = c and d ;
memory element
z2<= w ;
end if;
end process ;
Hardware inferred
Same process with order of statements

changed
process (clk, a, b, c, d)
variable y, x, w : std_logic ;
begin
if (clk='1' and clk'event) then
x := a and b ;
y := x ;
variables are read
z1<= y ;
before being written
z2<= w ;
to , this infers a
w := c and d ;
memory element
end if;
end process ;
Hardware inferred
Hardware modeling examples

For loop
process(word)
variable result : std_logic;
begin
result:='0';
for i in 0 to 7 loop
result := result xor word(i);
end loop;
op<=result;
end process;
Multiplexer optimization
The hardware inferred depends on the
condition given in the when others clause
case sel is
when 000 => y<= data(0);
when 001 => y<= data(1);
when 010 => y<= data(2);
when 011 => y<= data(3);
1) when others => y<= 0;
2) when others => y<= Z;
3) when others => y<= X;
4) when others => NULL;
end case;
Case 1
when others => y<= 0;
Case 2
when others => y<= Z;
Case 3
when others => y<= X;
Case 4
when others => NULL;
Good coding practices

Good coding style means that the synthesis tool can
identify constructs within your code that it can easily
map to technology features
All programmable devices may have their unique
architectural resources e.g. Xilinx Virtex series has
built-in RAM
Coding for performance :
common mistake is to ignore hardware and start
coding as if programming. To achieve best
performance the designer must think about
hardware

Improve performance by
avoiding unnecessary priority structures
in logic
optimizing logic for late arriving signals
structuring arithmetic for performance
avoiding area inefficient code
buffering high fan-out signals

Use constants to enhance readability and code
maintenance
Comparison with a constant is preferred since it
is much cheaper to implement
To avoid accidental latches
specify all clauses of if and case statements
specify all outputs
Use case rather than if-then-else whenever

possible
Use parentheses for better operation
Never use mode buffer
Design constraints
Constraining designs:
constraints are means of communicating our
requirements to the synthesis and back-end tools
Categories of constraints are :

Timing constraints
maximum frequency
duty cycle
input delays
output delays
Layout constraints
Design constraints
Avoid over-constraining the design
Consequences of over-constraining are:
Design performance suffers:
critical timing paths get the best placement and
fastest routing options
as the number of critical paths increase , the ability
to obtain the design performance objectives
decrease
Run times increase
Simulate your design before synthesis
Avoid combinational loops in processes
If a port is declared to be an integer data
type, the range should be specified, else
the synthesis tool will infer a 32-bit port
Avoid mixed clock edges
if a large number of both positive and
negative edge flip-flops are required they
should be placed in different modules
For best results:
use technology primitives (macros) from the target
technology libraries wherever possible
try small designs on target technology to fing its
limitations and strengths
Partition the design correctly
eliminate glue logic at the top level
partition block size based on the logic function, CPU
resources and memory
separate random logic from structured logic
separate timing-sensitive modules from area -sensitive ones
Next class
CPLDs and FPGAs
CPLD, FPGA
Programmable Logic
R.B.Ghongade
Lecture 29,30,31
Programmable Logic
Programmable digital integrated circuit
Standard off-the-shelf parts
Desired functionality is implemented by configuring on-chip
logic blocks and interconnections
Advantages (compared to an ASIC):
Low development costs
Short development cycle
Device can (usually) be reprogrammed
Types of programmable logic:

Complex PLDs (CPLD)
Field programmable Gate Arrays (FPGA)
PLD - Sum of Products

Programmable AND array followed by fixed fan-in OR gates
A
C
Programmable switch or fuse
f1 = A B C + A B C
f2 = A B + A B C
AND plane
3
PLD - Macrocell
Can implement combinational or sequential logic
Select
A
Enable
Flip-flop
f1
MUX
D
Clock
AND plane
CPLD Structure
Integration of several PLD blocks with a programmable
interconnect on a single chip
PLD
PLD
Block
Block
PLD
PLD
Block
Block
I/O Block
Block
I/O
I/O Block
Block
I/O
Interconnection
Interconnection Matrix
Matrix
PLD
PLD
Block
Block
PLD
PLD
Block
Block
I/O Block
Block
I/O
I/O Block
Block
I/O
CPLDs Architecture
CPLD
architecture
Small number of largish

PLDs (e.g., 36V18) on a single chip
Programmable interconnect between PLDs
6
How to expand PLD architecture?

Increase # of inputs and outputs in a
conventional PLD?
E.g., 16V8 --> 20V8 --> 22V10.
Why not --> 32V16 --> 128V64 ?
Problems:
n times the number of inputs and outputs requires
n2 as much chip area -- too costly
logic gets slower as number of inputs to AND array
increases
Solution: multiple PLDs with a relatively small

programmable interconnect.
Less general than a single large PLD, but can use
software fitter to partition into smaller PLD blocks.
7
CPLD families
Identical individual PLD blocks (Xilinx FBs)
replicated in different family members.
Different number of PLD blocks
Different number of I/O pins
Many CPLDs have fewer I/O pins than

macrocells
Buried Macrocells -- provide needed logic terms
internally but these outputs are not connected
externally.
IC package size dictates # of I/O pins but not the
total # of macrocells.
Typical CPLD families have devices with differing
resources in the same IC package.
8
Xilinx CPLDs
Notice overlap in resource availability in a

particular package.
9
Xilinx 9500-family CPLD architecture
72 ==>
XC9572
10
9500-family function blocks (FBs)
18 macrocells per FB
36 inputs per FB (partitioning challenge, but
also reason for relatively compact size of FBs)
Macrocell outputs can go to I/O cells or back
into switch matrix to be routed to this or other
FBs.
11
9500-series macrocell (18 per FB)

Set control
Programmable
inversion or XOR
product term
Up to 5
product terms
Global clock or
product-term clock
Reset control
OE control
12
9500-series product-term allocator

programmable
steering
elements
Share terms from

above and below
13
9500-series
I/O block
14
Switch matrix
for XC95108
Could be anything from a limited set of

multiplexers to a full crossbar.
Multiplexer -- small, fast, but difficult fitting
Crossbar -- easy fitting but large and slow
15
FPGAs
Historically, FPGA architectures and
companies began around the same time as
CPLDs
FPGAs are closer to programmable ASICs -large emphasis on interconnection routing
Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLDs switch matrix.
But more scalable to large sizes.
FPGA programmable logic blocks have only a

few inputs and 1 or 2 flip-flops, but there are a
lot more of them compared to the number of
macrocells in a CPLD.
16
FPGA
architecture
Much larger number of

smaller programmable logic blocks.
Embedded in a sea of lots and lots
of programmable interconnect.
17
General FPGA chip architecture
a.k.a. CLB -configurable logic

block
18
FPGA - Generic Structure

FPGA building blocks:
Interconnection switches
I/O
I/O
I/O
Programmable logic blocks

Implement combinatorial and
sequential logic
Programmable interconnect
Wires to connect inputs and outputs
to logic blocks
Programmable I/O blocks
Special logic blocks at the periphery
of device for external connections
Logic block
I/O
19
Other FPGA Building Blocks

Clock distribution
Embedded memory blocks
Special purpose blocks:
DSP blocks:
Hardware multipliers, adders and registers
Embedded microprocessors/microcontrollers
High-speed serial transceivers
20
FPGA Basic Logic Element

LUT to implement combinatorial logic
Register for sequential circuits
Additional logic (not shown):
Carry logic for arithmetic functions
Expansion logic for functions requiring more than 4 inputs
Select
Out
A
B
C
D
LUT
LUT
Clock
21
Look-Up Tables (LUT)

Look-up table with N-inputs can be used to implement any combinatorial
function of N inputs
LUT is programmed with the truth-table
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
Truth-table
A
B
C
D
LUT
LUT
LUT implementation
A
B
Z
C
D
Gate implementation
22
LUT Implementation
Example: 3-input LUT
Based on multiplexers (pass
transistors)
LUT entries stored in
configuration memory cells
X1
X2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Configuration memory
cells
0/1
0/1
X3
23
Programmable Interconnect
Interconnect hierarchy (not shown)
Fast local interconnect
Horizontal and vertical lines of various lengths
LE
LE
LE
LE
Switch
Matrix
LE
LE
LE
LE
Switch
Matrix
LE
LE
LE
LE
24
Switch Matrix Operation

Before Programming
After Programming
6 pass transistors per switch matrix

interconnect point
Pass transistors act as programmable
switches
Pass transistor gates are driven by
configuration memory cells
25
Special Features
Clock management
PLL,DLL
Eliminate clock skew between external clock input and onchip clock
Low-skew global clock distribution network
Support for various interface standards

High-speed serial I/Os
Embedded processor cores
DSP blocks
26
Configuration Storage Elements

Static Random Access Memory (SRAM)
each switch is a pass transistor controlled by the state of an SRAM bit
FPGA needs to be configured at power-on
Flash Erasable Programmable ROM (Flash)

each switch is a floating-gate transistor that can be turned off by injecting charge
onto its gate. FPGA itself holds the program
reprogrammable, even in-circuit
Fusible Links (Antifuse)

Forms a forms a low resistance path when electrically programmed
one-time programmable in special programming machine
radiation tolerant
27
Xilinx 4000-series FPGAs
28
FPGA specsmanship
Two flip-flops per CLB, plus two per I/O cell.
25 gates per CLB if used for logic.
32 bits of RAM per CLB if not used for logic.
All of this is valid only if your design has a
perfect fit.
29
Configurable Logic Block (CLB)
30
CLB function generators (F, G, H)

Use RAM to store a truth table
F, G: 4 inputs, 16 bits of RAM each
H: 3 inputs, 8 bits of RAM
RAM is loaded from an external PROM at system
initialization.
Broad capability using F, G, and H:

Any 2 funcs of 4 vars, plus a func of 3 vars
Any func of 5 vars
Any func of 4 vars, plus some funcs of 6 vars
Some funcs of 9 vars, including parity and 4-bit
cascadable equality checking
31
CLB input and output connections -buried in the sea of interconnect
32
Detail
connections
controlled by
RAM bits
33
Programmable Switch Matrix

programmable switch element
turning the corner, etc.
34
The fitters job

Partition logic functions into CLBs
Arrange the CLBs
Interconnect the CLBs
Minimize the number of CLBs used
Minimize the size and delay of interconnect
used
Work with constraints
Locked I/O pins
Critical-path delays
Setup and hold times of storage elements
35
I/O blocks
36
Problems common to CPLDs and FPGAs

Pin locking
Small changes, and certainly large ones, can cause
the fitter to pick a different allocation of I/O blocks
and pinout.
Locking too early may make the resulting circuit
slower or not fit at all.
Running out of resources

Design may blow up if it doesnt all fit on a single
device.
On-chip interconnect resources are much richer
than off-chip; e.g., barrel-shifter example.
Larger devices are exponentially more expensive.
37
CPLD Vs. FPGA
CPLD
Interconnect style
Architecture and timing
Software compile times
In-system performance
Power consumption
Applications addressed
Continuous
Predictable
Short
Fast
High
Combinational and
registered logic
FPGA
Segmented
Unpredictable
Long
Moderate
Moderate
Registered
logic only
Source: Altera
38
FPGA Selection Criteria

Density
Speed
Price
Flexibility
39
FPGA Vendors & Device Families

Xilinx
Virtex-II/Virtex-4: Feature-packed
high-performance SRAM-based
FPGA
Spartan 3: low-cost feature reduced
version
CoolRunner: CPLDs
Altera
Stratix/Stratix-II
High-performance SRAM-based
FPGAs
Actel
Anti-fuse based FPGAs
Radiation tolerant
Flash-based FPGAs
Lattice
Flash-based FPGAs
CPLDs (EEPROM)
QuickLogic
ViaLink-based FPGAs
Cyclone/Cyclone-II
Low-cost feature reduced version for
cost-critical applications
MAX3000/7000 CPLDs
MAX-II: Flash-based FPGA
40
State of the Art in FPGAs

90 nm process on 300 mm wafers
Lower cost per function (LUT + register)
Smaller and faster transistors: Higher speed
System speed up to 500 MHz

Mainly through smart interconnects, clock management, dedicated circuits,
flexible I/O.
Integrated transceivers running at 10 Gigabits/sec
More Logic and Better Features:

>100,000 LUTs & flip-flops
>200 embedded RAMs, and same number 18 x 18 multipliers
1156 pins (balls) with >800 GP I/O

50 I/O standards, incl. LVDS with internal termination
16 low-skew global clock lines

Multiple clock management circuits
On-chip microprocessor(s) and multi-Gbps transceivers
41
Latest Devices: Capacity & Features

Xilinx Virtex-4
Altera Stratix-II
90nm process
Up to 960 I/Os
>200000 logic cells
Up to 552 18kb block RAMs (~10Mb
RAM)
192 DSP slices (18x18 multiplieraccumulator)
20 digital clock managers (DCM)
24 high-speed serial transceivers
(622Mb/s to 11.1Gb/s)
Up to four PowerPC 405 cores
90nm process
Up to 1170 I/Os
179000 logic elements
9.6Mb embedded RAM
96 DSP blocks: 380 18x18
multipliers
12 PLLs
Serial I/O up to 1Gb/s

No hard processor cores
42
JTAG and Boundary Scan

Technique for Testing
R.B.Ghongade
Lecture 32,33
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VLSI Design Issues

R.B.Ghongade
Lecture 34 ,35
Perspective view of n-channel

MOSFET
Inversion
The bulk has to have the
lowest potential to ensure
reverse biased pn-junctions
(no current must flow
between drain/source
and bulk!)
VSB = 0 in the following
we relate all voltages to the
source voltage
VGS > VT n-channel is
induced (blue area between
drain and source)
White area depletion
region
A current can flow between
drain
and source, if VDS > 0
Because the MOSFET is a

symmetrical device, source and
drain have to be defined: source
has always a lower potential than
the drain for an n-channel FET!
Ohmic region
Increasing VDS to a value VDS > 0
leads to a current ID.
Near the drain the voltage
responsible for the inversion is
(VGS - VT) - VDS and thus smaller
than near the source.
The channel acts like a linear
resistor - thats why this region of
operation is called ohmic.
Pinch-off
If VDS rises to the point
where it is VGS - VT,
there is no voltage near
the drain to induce an
inversion layer - the
channel is pinched off
at the drain
Saturation
Further increasing VDS
causes the pinch-off
point to move in the
direction of the source
The voltage at the pinch
off point is always VGS
VT
When the electrons
coming from the source
reach the pinch off point,
they are injected into the
depleted region and the
electric field in this
region sweeps the
electrons from the pinch
off point to the drain.
Channel length modulation is significant for

short channel devices and corresponds to the
ID increase at high VDS
Transfer Characteristics and

Depletion Mode MOSFET
Transfer characteristics: plot of
drain current versus gate-source
voltage for a fixed drain-source
voltage
If threshold voltage of NMOS
transistor negative depletion
mode MOSFET (there exists an
implanted n-type channel region)
p-channel MOSFET
MOS Equations Summary
Cg =
K=
Cg =
K=
Cg
WL
Cg
WL
ins 0WL
D
Cg =
ins 0WL
D
ins 0WL
D
MOS capacitances (linear region)

The channel shields the bulk electrode from the gate since the
inversion layer acts as conductor between drain and source.
MOS capacitances (saturation region)

The channel shields the bulk electrode from the gate since the
inversion layer acts as conductor between drain and source.
The channel is pinched off and does not contact the drain n+
region.
MOS capacitances (cut-off)

The gate-bulk capacitance consists of the gate capacitance in
series with the depletion capacitance of the depletion region.
Small signal model for FET (I)

Considering the MOSFET as a three-terminal device
Small-signal model of the MOSFET is based on the yparameter two-port network
Small-Signal Models for Field-Effect

Transistors
Body Effect in the

Four-Terminal MOSFET
A second voltage-controlled current source has been added to
model the back-gate transconductance gmb
High-Frequency MOSFET
Small Signal Model
High-Frequency MOSFET
Small Signal Model
Short channel effects on MOS

transistors
As the technology scaling
reaches channel lengths less
than a micron (L<1), second
order effects, that were ignored in
devices with long channel length
(L>1), become very important
MOSFETs owning those
dimensions are called short
channel devices
The main second order effects
are:
Velocity Saturation
Threshold Voltage Variations
Hot Carrier Effects
Velocity saturation
The behavior of the short

channel devices deviates
considerably from this model
Equation assumes the mobility
n as a constant independent
of the value of the electric field
At high electric field carriers

fail to follow this linear model
This is due to the velocity
saturation effect
Threshold voltage variations
For a long channel N-MOS transistor the threshold Voltage is

only a function of the technology and applied body bias VSB
For short channel devices this model becomes inaccurate
and threshold voltage becomes function of L, W and VDS
Hot carrier effects

During the last decades transistors dimensions
were scaled down, but not the power supply
The resulting increase in the electric field strength
causes an increasing energy of the electrons
Some electrons are able to leave the silicon and
tunnel into the gate oxide
Such electrons are called Hot carriers
Electrons trapped in the oxide change the VT of the
transistors
This leads to a long term reliability problem
For an electron to become hot an electric field of
104 V/cm is necessary
This condition is easily met with channel lengths
below 1m.
Process variations
Variations in the process parameters, such as
impurity concentration densities, oxide thicknesses,
and diffusion depths. These are caused by non-uniform
conditions during the deposition and/or the diffusion
of the impurities. This introduces variations in the sheet
resistances and transistor parameters such as the
threshold voltage
Variations in the dimensions of the devices, mainly
resulting from the limited resolution of the
photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the
emitter areas of bipolar devices
CMOS Technology
R.B.Ghongade
Lecture 35
Wafer terminology
1. Chip = Die = Microchip = Bar
2. Scribe Lines
3. Engineering Test Die
4. Edge Die
5. Crystal Planes
6. Wafer Flats
Basic Wafer Fabrication Operations

The number of steps in IC fabrication flow depends
upon the technology process and the complexity of the
circuit
Ex.:
CMOS n-Well process - 30 major steps, and each
major step may involve up to 15 substeps
Only three basic operations are performed on the
wafer:
Layering
Patterning
Doping
Layering
Patterning
Doping
Change conductivity type and resistivity on selected regions of
wafer
Doping takes place to the wafer through the holes patterned in
the surface layer
Two techniques are used:
Thermal diffusion
Ion implantation
Thermal diffusion:
- heat the wafer to the vicinity of 1000C
- expose the wafer to vapors containing the desired dopant
- the dopant atoms diffuse into the wafer surface creating a p/n
region
Ion implantation:
- room temperature
- dopant atoms are accelerated to a high speed and shot into
the wafer surface
- an annealing (heating) step is necessary to reorder the crystal
structure damaged by implant
NMOS Fabrication flow
Device isolation
MOS transistors must be electrically isolated from each other in order to:
prevent unwanted conduction paths between devices
avoid creation of inversion layers outside the channel regions
reduce the leakage currents
Each device is created in dedicated regions - active areas
Each active area is surrounded by a field oxide barrier using few techniques:
A) Etched field-oxide isolation
1) grow a field oxide over the entire surface of the chip
2) pattern the oxide and define active areas
Drawbacks: -large oxide steps at the boundaries between active areas and field
regions!
-cracking of polysilicon/metal subsequent deposited layers!
Not used!
B) Local Oxidation of Silicon (LOCOS)
n-Well CMOS Technology simplified process sequence
References
VLSI Design by Weste & Eshraghian
CMOS VLSI Design by Rabaey
VLSI Technology by Sanders
CMOS Inverter
R.B.Ghongade
Lecture 36,37
Inverter as simplest logic gate
Logic Voltage Levels

VOL: Nominal voltage
corresponding to a low logic
state at the output of a logic
gate for VI = VOH
Generally V- VOL
VOH: Nominal voltage
corresponding to a high logic
state at the output of a logic
gate for VI = VOL.
Generally VOH V+
VIL: Maximum input voltage that
will be recognized as a low
input logic level.
VIH: Minimum input voltage that will
be recognized as a high input
logic level.
Noise Margins
NML: Noise margin associated with
a low input level
NML = VIL VOL
NMH: Noise margin associated with
a high input level
NMH = VOH - VIH
Dynamic Response of Logic Gates

Rise time tr: time required for
the transition from V10% to V90%
Fall time tf: time required for the
transition from V90% to V10%
Propagation delay P: difference

in time between the input and
output signals reaching V50%
MOS Inverter with Resistive Load

NMOS switching device MS
designed to force vO to VOL
Resistor load R to pull the output
up toward the power supply VDD
VOH = VDD
(driver in cut off iD = 0)
VOL determined by W/L ratio of
MS
Example
On - Resistance
Transistor Alternatives to the Load

Resistor
CMOS inverter technology
Complementary MOS (CMOS)

Logic Design
Inverter with resistive
load =>power dissipation
when the input is high
If an NMOS and
PMOS transistor is
used => CMOS
One transistor is
always off while the
other is on => no
static power consumption
CMOS voltage transfer

Characteristic
Regions of Operation of Transistors in a

Symmetrical Inverter
Input Voltage vI
Output
Voltage
vO
vI VTN
VOH = VDD Cutoff
Linear
VTN < vI vO + VTP
High
Saturation
Linear
vI = VDD/2
VDD/2
Saturation
Saturation
vO + VTN < vI (VDD + VTP) Low
Linear
Saturation
vI (VDD + VTP)
Linear
Cutoff
Region
VOL = 0
NMOS
Transistor
PMOS
Transistor
Calculation of VIL
Calculation of VIH
Calculation of Vth
Design of CMOS inverter (I)
Design of CMOS inverter (II)
Dynamic Behavior of the CMOS Inverter

High to Low Output Transition
Low to high output transition
Dynamic Behavior of the CMOS Inverter
Power Dissipation
Two kinds of power
dissipation in digital
electronics:
static power dissipation
(logic gate output is
stable)
dynamic power
dissipation (during
switching of logic gate)
With CMOS nearly no
static power dissipation!
Dynamic Power Dissipation (I)
Dynamic Power Dissipation (II)
Dynamic Power Dissipation (III)

Thus, every time a logic gate goes through a complete switching cycle,
the transistors within the gate dissipate an energy equal to ETD.
Logic gates normally switch states at some relatively high frequency
(switching events/second), and the dynamic power PD dissipated by
the logic gate is then
In effect, an average current equal to ( C.VDD.f ) is supplied

from the source VDD.
Dynamic Power Dissipation (IV)

Power dissipation due to the short circuit current (when both
transistors are on during transition)
The short circuit current reaches a peak for Vin = Vout = VDD/2
Complementary MOS (CMOS)

Logic Design
R.B.Ghongade
Lecture 37
Basic CMOS Logic Gate Structure

PMOS and NMOS
switching networks
are complementary
Either the PMOS or
the NMOS network is
on while the other is
off
No static power
dissipation
CMOS NOR Gate
Transistor Sizing for CMOS Gates

Goal: To maintain the delay times equal the reference inverter
design under the worst-case input conditions
Example: 2 input CMOS NOR gate
- Each transistor of the NMOS network is capable of
discharging individually the load capacitance C =>
Same size as NMOS transistor of reference inverter
- PMOS network conducts only when AB = 00
(Transistors in series) => Each PMOS must be twice
larger ( On-resistance proportional to (W/L)-1 )
CMOS NAND Gate
Multi-Input NAND Gate
Summary
AND - serially connected FET
OR - parallel connected FET
NMOS network implements
zeros
PMOS network implements
ones
W/L ratio has to be
determined as a design
parameter
Power-Delay Product (PDP)
Power-Delay Product (contd)
CMOS Transmission Gate (I)
Bidirectional resistive connection between the input and

output terminals
Useful in both analog (e.g. for relay contacts) and in digital
design (e.g. for multiplexers)
Implementation, Fitting, Place

& Route
R.B.Ghongade
Lecture 38
Device Implementation
We now have a design netlist that completely describes our design
using the gates for a specific vendor/ device family and it has been
fully verified. It is now time to put this in a chip, referred to as Device
Implementation.
Translate consists of a number of various programs that are used to
import the design netlist and prepare it for layout. The programs will
vary among vendors. Some of the more common programs during
translate include: optimisation, translation to the physical device
elements, device-specific design rule checking (e.g. does the design
exceed the number of clock buffers available in this device). It is
during the stage of the design flow that you will be asked to select the
target device, package, speed grade and any other device-specific
options.
The translate step usually ends with a comprehensive report of the
results of all the programs executed. In addition to warnings anderrors, there is
usually a listing of device and I/O utilisation, which
helps the designer to determine if he has selected the best device.
Fitting
For CPLDs, the design step is called Fitting to Fit the design to the
target device. A section of the design is fit to the CPLD. CPLDs are a fixed
architecture so the software needs to pickthe gates and interconnect paths that
match the circuit. This is usuallya fast process.
The biggest potential problem here is if the designer has previously
assigned the exact locations of the I/O pins, commonly referred to as
Pin Locking. (Most often this is from a previous design iteration and
has now been committed to the printed circuit board layout).
Architectures (like the Xilinx XC9500 & CoolRunner CPLDs) that
support I/O pin locking have a very big advantage. They permit the
designer to keep the original I/O pin placements regardless of the
number of design changes, utilisation or required performance.
Pin locking is very important when using In-System Programming ISP. This means that if you layout your PCB to accept a specific pin
out then if you need to change the design you can re-programme
confident that you pin out will stay the same.
Place & Route

For FPGAs, the Place and Route programs are run after Compile.
Place is the process of selecting specific modules or logic blocks in
the FPGAs where design gates will reside. Route as the name
implies, is the physical routing of the interconnect between the logic
blocks.
Most vendors provide automatic place and route tools so the user does
not have to worry about the intricate details of the device architecture.
Some vendors have tools that allow expert users to manually place
and/or route the most critical parts of their designs and achieve better
performance than with the automatic tools. Floorplanner is a form of
such manual tools.
These two programs require the longest time to complete successfully
since it is a very complex task to determine the location of large
designs, ensure they all get connected correctly, and meet the desired
performance. These programs however, can only work well if the
target architecture has sufficient routing for the design. No amount of
fancy coding can compensate for an ill-conceived architecture,
especially if there is not enough routing tracks. If the designer faces
this problem, the most common solution to is to use a larger device.
And he will likely remember the experience the next time he is
selecting a vendor.
A related program is called Timing-Driven Place & Route (TDPR).

This allows users to specify timing criteria that will be used during
device layout
A Static Timing Analyser is usually part of the vendors implementation
software. It provides timing information about paths in the design.
This information is very accurate and can be viewed in many different
ways (e.g. display all paths in the design and rank them from longest
to shortest delay).
In addition, the user at this point can use the detailed layout
information after reformatting, and go back to his simulator of choice
with detailed timing information. This process is called BackAnnotation and has the advantage of providing the accurate timing as
well as the zeros and ones operation of his design.
In both cases, the timing reflects delays of the logic blocks as well as
the interconnect.
Downloading Design
Download generally refers to volatile devices such as SRAM FPGAs.
As the name implies, you download the device configuration
information into the device memory. The Bitstream that is transferred
contains all the information to define the logic and interconnect of the
design and is different for every design. Since SRAM devices lose their
configuration when the power is turned off, the bitstream must be
stored somewhere for a production solution. A common such place is
a serial PROM. There is an associated piece of hardware that
connects from the computer to a board containing the target device.
Program is used to program all non-volatile programmable logic
devices including serial PROMs. Programming performs the same
function as download except that the configuration information is
retained after the power is removed from the device. For antifuse
devices, programming can only be done one per device. (Hence the
term One-Time Programmable, OTP).
Programming of Xilinx CPLDs can be done In-System via JTAG (Joint

Test Advisory Group) or using a conventional device programmer e.g.
Data I/O. JTAG boundary scan formally known as IEEE/ANSI
standard 1149.1_1190 is a set of design rules, which facilitate
testing, device programming and debugging at the chip, board and
system levels. In-System programming has the added advantage that
devices can be soldered directly to the PCB, e.g. TQFP surface mount
type devices, and if the design changes do not need to be removed
form the board but simply re-programmed in-system. JTAG stands for
Joint Test Advisory Group and is an industry.
System Debug
At this point in the design flow, the device is now working but were not
done yet. We need to do a System Debug - verify that our device
works in the actual board. This is truly the moment of truth because
any major problems here means the engineer has made a assumption
on the device specification that is incorrect or has not considered
some aspect of the signal required to/from the programmable logic
device. If so, he will then collect data on the problem and go back to
the drawing (or behavioural) board!
Additional Topics
R.B.Ghongade
Lecture 39
Setup and Hold times

tsu
th
CLK
tplh
tphl
For ideal DFF , if input changed at exactly the same

time as active edge of clock, the DFF would operate
correctly
But for real DFF , the D input must be stable for a
certain amount of time before the active edge of the
clock (called as setup time, tsu)
In addition to this, the D input must be stable for
certain time after the active edge of clock ( called
hold time, th)
Therefore if the D input is not stable during tsu
before the active edge of the clock or during th after
the active clock edge. it cannot be determined
whether the FF will change state
The propagation delays tphl and tplh are also
important
These four timing parameters are specified in
manufacturers datasheet
Maximum clock frequency for sequential

network
Outputs(Z)
Inputs(X)
Combinational
Network
Next State
Clock
State
Reg
State
Assume :
max propagation delay for combinational network = tcmax
max propagation delay from the time the clock changes to the FF
output changes= tpmax where tpmax=max(tphl,tplh)
Then the max time from active clock edge to the time the change in Q
propagates back to DFF inputs= tpmax+tcmax
If clock period is tck, the D inputs must be stable tsu before the end of
clock peiod, hence
tpmax + tcmax tck-tsu

or
tck tpmax+tcmax+tsu
E.g. If max gate delay is 15 ns , tpmax=15 ns, tsu=5 ns then
tck ( 2 x 15 ) +15 + 5 = 50 ns
therefore max clock frequency= 1/tck = 20 MHz
A hold time violation could occur if the change in Q fed back through the
combinational network and caused D to change too soon after the clock
edge.
The hold time is satisfied if
tpmin +tcmin th

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Introduction to VHDL

EDA stands for ELECTRONIC DESIGN AUTOMATION

VHDL has got powerful language

Design hierarchies to create modular

Sequential statements are required to design sequential circuits

Timing can be specified in a process only

Any HDL should thus be equipped with

MODULE UNDER TEST

Equivalent to mechanical test jigs used for testing functionality of mass

Design hierarchy simplifies the design procedure and manageability in case

HOW TO RESOLVE THIS CONDITION ?

For this problem a 9-valued logic system

Layout information and analog effects are

Register Transfer Level

Digital design using VHDL

Place & route

Vendors providing programmable

Basic building blocks

This package defines a standard for designers

This package defines a standard for designers

This package defines numeric types and

This package defines numeric types and

This package defines a standard for designers

This package defines a set of arithmetic,

This package defines a set of arithmetic,

This package defines supplemental types,

This package defines a set of signed

This package overloads the standard

IEEE.STD_LOGIC_UNSIGNED.all This package defines a set of unsigned

Ports should be well documented with

port ( C : inout std_logic ) ;

Drivers reside both

port ( D : buffer std_logic ) ;

Signal can be read inside the entity

Architecture can contain only concurrent

VHDL is a strongly typed language

VHDL is not case sensitive ( but avoid

This results in an object called COUNT that holds

The name given to the object is called as

Each object has a data type and class

Pre-defined data types

BIT (and BIT_VECTOR): 2 level logic (0, 1)

SIGNAL Y : BIT_VECTOR (3 downto 0);

SIGNAL W : BIT_VECTOR (0 to 7);

To assign a value to the signal use the

X is a single bit SIGNAL whose value is 1

Y is a 4- bit SIGNAL whose value

STD_LOGIC (and STD_LOGIC_VECTOR):

SIGNAL Y : STD_LOGIC_VECTOR (3 downto 0);

Most of std_logic levels are intended for simulation

The STD_ULOGIC has 9 valued logic levels : additional

32-bit integers (from - 2,147,483,647 to +

Non-negative numbers (from 0 to

Real numbers (from -1.0E-38 to +1.0E38)

Used to inform physical quantities like , time,

Single ASCII character or a string of such

User defined data types

User defined integer type

User defined enumerated type