Introduction to Verilog

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 Course Objectives

n Learn the basic constructs of Verilog

n Learn the modeling structure of Verilog
n Learn the concept of delays and their effects in
simulation

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 Course Outline

n Verilog Overview
n Basic Structure of a Verilog Model
n Components of a Verilog Module
– Ports
– Data Types
– Assigning Values and Numbers
– Operators
– Behavioral Modeling
• Continuous Assignments
• Procedural Blocks
– Structural Modeling
n Summary: Verilog Environment

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 Verilog
Overview

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 What is Verilog?

n IEEE industry standard Hardware Description

Language (HDL) - used to describe a digital system
n For both Simulation & Synthesis

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 Verilog History

n Introduced in 1984 by Gateway Design Automation

n 1989 Cadence purchased Gateway (Verilog-XL
simulator)
n 1990 Cadence released Verilog to the public
n Open Verilog International (OVI) was formed to
control the language specifications.
n 1993 OVI released version 2.0
n 1993 IEEE accepted OVI Verilog as a standard,
Verilog 1364

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 Verilog Structure

n Verilog HDL : Consists of Keywords, syntax and

semantics used to describe hardware functionality
and timing.
n PLI : Programming Language Interface provides C
language routines used to interact between Verilog
and EDA tools. (Simulators,Waveform displays)
n SDF : Standard Delay Format - a file used to back-
annotate accurate timing information to simulators
and other tools.

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 Terminology

n HDL - Hardware Description Language is a software

programming language that is used to model a piece
of hardware
n Behavior Modeling - A component is described by its
input/output response
n Structural Modeling - A component is described by
interconnecting lower-level components/primitives

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 Behavior Modeling

n Only the functionality of the circuit, no structure

n No specific hardware intent
n For the purpose of synthesis, as well as simulation

output1, .., outputn

input1, .., inputn
if (input1)
for (j=0, j<8, j=j+2)
#5 output1 = 1’b0;
else
for (j=1, j<8, j=j+2)
#5 output1 = 1’b1;

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 Structural Modeling
n Functionality and structure of the circuit
n Call out the specific hardware
n For the purpose of synthesis

Higher-level Component
input1 output1

Lower-level
Component1

Lower-level
Component1

inputn outputn

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 More Terminology

n Register Transfer Level (RTL) - A type of behavioral

modeling, for the purpose of synthesis.
– Hardware is implied or inferred
– Synthesizable
n Synthesis - Translating HDL to a circuit and then
optimizing the represented circuit
n RTL Synthesis - The process of translating a RTL
model of hardware into an optimized technology
specific gate level implementation

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 RTL Synthesis
always @(a or b or c or d or sel)
inferred
a
begin b mux_out
case (sel) c
2’b00: mux_out = a; d
2b’01: mux_out = b; sel
2b’10: mux_out = c; 2
2’b11: mux_out = d;
endcase

Translation
d

d
Optimization

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 Verilog vs. Other HDL Standards

n Verilog
– “Tell me how your circuit should behave and I will give you
the hardware that does the job.”
n VHDL
– Similar to Verilog
n ABEL, PALASM, AHDL
– “Tell me what hardware you want and I will give it to you”

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 Verilog vs. Other HDL Standards

n Verilog
– “Give me a circuit whose output only changes when there is
a low-to-high transition on a particular input. When the
transition happens, make the output equal to the input until
the next transition.”
– Result: Verilog Synthesis provides a positive edge-triggered
flipflop
n ABEL, PALASM, AHDL
– “Give me a D-type flipflop.”
– Result: ABEL, PALASM, AHDL synthesis provides a D-type
flipflop. The sense of the clock depends on the synthesis
tool.

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Typical Synthesis Design Flow

Verilog Technology
Model Library

Synthesis
Compiler

Timing Analysis Netlist Place/Route

Text Output
Test
Simulation Vectors
Waveform

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Typical Simulation Design Flow

Verilog Verilog
Model TestBench

Optional

Simulation
Compiler

Simulation Test
Model Vectors

Waveform Verilog
Text Output
Simulation

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 Verilog
Modeling

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 Verilog - Basic Modeling Structure
n CASE-sensitve
module module_name (port_list); n All keywords are
port declarations lowercase
n Whitespace is used for
data type declarations readability.
n Semicolon is the
circuit functionality statement terminator
n Single line comment: //
timing specifications n Multi-line comment: /* */
endmodule n Timing specification is
for simulation

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 Components of a Verilog Module

module Timing Specifications

(Port List)

Port Data Type Circuit Subprograms

Declarations Declarations Functionality
Instantiation task
input Net
Continuous Procedural function
output Register Assignment Blocks
System Tasks

inout assign initial

parameter
block Compiler
Directives
always
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 Components of a Verilog Module
module Module_name (Port_list)

Port declarations (if ports are present)

Parameters (optional)

Data type declarations

Continuous Assignments (assign)

Procedural Blocks (initial and always)

- behavioral statements

Instantiation of lower-level modules

Tasks and Functions

Timing Specifications

endmodule
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 Schematic Representation - MAC

adder_out out
ina
+ D Q

mult_out clk
X
inb
CLRN
clr

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Verilog Model: Mulitiplier-Accumulator (MAC)
`timescale 1 ns/ 10 ps assign adder_out = mult_out + out;

module mult_acc (out, ina, inb, clk, clr); always @ (posedge clk or posedge clr)
begin
input [7:0] ina, inb; if (clr)
input clk, clr; out = 16'h0000;
output [15:0] out; else
out = adder_out;
wire [15:0] mult_out, adder_out; end
reg [15:0] out;
multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));
parameter set = 10;
parameter hld = 20; specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify

endmodule

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 Let’s take a look at:

module Timing Specifications

(Port List)

Port Data Type Circuit Subprograms

Declarations Declarations Functionality
Instantiation task
input Net
Continuous Procedural function
output Register Assignment Blocks
System Tasks

inout assign initial

parameter
block Compiler
Directives
always
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 Ports
n Port List:
– A listing of the port names
– Example:
module mult_acc (out, ina, inb, clk, clr);
n Port Types:
– input --> input port
– output --> output port
– inout --> bidirectional port
n Port Declarations:
– <port_type> <port_name>;
– Example:
input [7:0] ina, inb;
input clk, clr;
output [15:0] out;
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 Ports: List and Declaration
`timescale 1 ns/ 10 ps assign adder_out = mult_out + out;

module mult_acc (out, ina, inb, clk, clr); always @ (posedge clk or posedge clr)
begin
input [7:0] ina, inb; if (clr)
out = 16'h0000;
input clk, clr; else
output [15:0] out; out = adder_out;
end
wire [15:0] mult_out, adder_out;
reg [15:0] out; multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));

parameter set = 10; specify

parameter hld = 20; $setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify

endmodule

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 Data Types
n Net Data Type - represent physical interconnect between
processes (activity flows)
process process
Functional Functional
nets Block:
nets Block:
nets
MUX Adders
(nets) (nets)

n Register Data Type - represent variable to store data

temporarily
– It does not represent a physical (hardware) register
Temporary Storage

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 Net Data Type

n wire --> represents a node

n tri --> represents a tri-state node

n Bus Declarations:
– <data_type> [MSB : LSB ] <signal name> ;
– <data_type> [LSB : MSB] <signal name> ;

n Examples:
– wire <signal name> ;
– wire [15:0] mult_out, adder_out;

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 Net Data Types

Supported by
Net Data Type Functionality Synthesis

wire tri Used for interconnect

supply0 supply1 Constant logic value
wand triand Used to model ECL
wor trior Used to model ECL
tri0 tri1 Pull-down, Pull-up
trireg Stores last value when
not driven

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 Register Data Types

n reg - unsigned variable of any bit size

n integer - signed variable (usually 32 bits)

n Bus Declarations:
– <data_type> [MSB : LSB ] <signal name> ;
– <data_type> [LSB : MSB] <signal name> ;

n Examples:
– reg <signal name> ;
– reg [7 : 0] out ;

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 Register Data Types

Register Supported by
Data Type Functionality Synthesis

reg Unsigned variable of

any bit size
integer Signed variable -
usually 32 bits
time Unsigned integer -
usually 64 bits
real Double precision
floating point variable

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 Memory

n Two dimensional register array

n Can not be a net type
n Examples:

reg [31:0] mem[0:1023]; // 1Kx32

reg [31:0] instr;

instr = mem[2];

n Double-indexing is not permitted

instr = mem[2][7:0] // Illegal

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 Parameter

n Parameter - assigning a value to a symbolic name

parameter size = 8;

reg [size-1:0] a, b;

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 Data Type

n Every signal (which includes ports) must have a data

type
– Signals must be explicitly declared in the data type
declarations of your module
– Ports are, by default, wire net data types if they
are not explicitly declared

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 Data Types: Declaration
`timescale 1 ns/ 10 ps assign adder_out = mult_out + out;

module mult_acc (out, ina, inb, clk, clr); always @ (posedge clk or posedge clr)
begin
input [7:0] ina, inb; if (clr)
input clk, clr; out = 16'h0000;
output [15:0] out; else
out = adder_out;
wire [15:0] mult_out, adder_out; end
reg [15:0] out; multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));

parameter set = 10; specify

parameter hld = 20; $setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify

endmodule

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 Assigning Values - Numbers
and
Operators

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 Assigning Values - Numbers

n Are sized or unsized: <size>‘<base format><number>

– Sized example: 3’b010 = 3-bit wide binary number
• The prefix (3) indicates the size of number
– Unsized example: 123 = 32-bit wide decimal number by default
• Defaults
– No specified <base format> defaults to decimal
– No specified <size> defaults to 32-bit wide number
n Base Format:
– Decimal (‘d or ‘D) 16’d255 = 16-bit wide decimal number
– Hexadecimal (‘h or ‘H) 8’h9a = 8-bit wide hexadecimal number
– Binary (‘b or ‘B) ’b1010 = 32-bit wide binary numer
– Octal (‘o or ‘O) ‘o21 = 32-bit wide octal number

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 Numbers

n Negative numbers - specified by putting a minus sign before

the <size>
– Legal: -8’d3 = 8-bit negative number stored as 2’s complement of 3
– Illegal: 4’d-2 = ERROR!!
n Special Number Characters:
– ‘_’(underscore): used for readability
• Example: 32’h21_65_bc_fe = 32-bit hexadecimal number
– ‘x’or ‘X’(unknown value)
• Example: 12’h12x = 12-bit hexadecimal number; LSBs unknown
– ‘z’or ‘Z’(high impedance value)
• Example: 1’bz = 1-bit high impedance number

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 Numbers

n Extended
– If MSB is 0, x, or z, number is extended to fill MSBs with 0, x,or
z, respectively
• Examples: 3’b01 = 3’b001, 3’bx1 = 3’bxx1, 3’bz = 3’bzzz
– If MSB is 1, number is extended to fill MSBs with 0
• Example: 3’b1 = 3’b001

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 Short Quiz

n Short Quiz:
– Q: What is the actual value for 4’d017 in binary?

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 Answers

n Short Quiz:
– Q: What is the actual value for 4’d017 in binary?
– A: 4’b0001, MSB is truncated (10001)

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 Arithmetic Operators
Operator Operation Examples
Symbol Performed ain = 5, bin = 10, cin = 2’b01, din =2’b0Z

+ Add bin + cin = 11

- Subtract, Negate bin - cin = 9 , -bin = -10
* Multiply ain * bin = 50
/ Divide bin / ain = 2
% Modulus bin % ain = 0

n Treats vectors as a whole value

n If any operand is Z or X, then the results are unknown
– Example: ain + din = unknown
n If results and operands are same size, then carry is lost
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 Bitwise Operators
Operator Operation Examples
Symbol Performed ain = 3’b101, bin = 3’b110, cin = 3’b01X

~ Invert each bit ~ain is 3’b010

& And each bit ain & bin is 3’b100, bin & cin is 3’b010
| Or each bit ain | bin is 3’b111
^ Xor each bit ain ^ bin is 3’b011
^~ or ~^ Xnor each bit ain ^~ bin = 3’b100

n Operates on each bit of the operand

n Result is the size of the largest operand
n Left-extended if sizes are different

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 Reduction Operators
Operator Operation Examples
Symbol Performed ain = 5’b10101, bin = 4’b0011
cin = 3’bZ00, din = 3’bX011
& And all bits &ain = 1’b0, &din = 1’b0
~& Nand all bits ~&ain = 1’b1
| Or all bits |ain = 1’b1, |cin = 1’bX
~| Nor all bits ~|ain = 1’b0
^ Xor all bits ^ain = 1’b1
~^ or ^~ Xnor all bits ~^ain = 1’b0

n Reduces a vector to a single bit

n X or Z are considered unkown, but result maybe a known
value
– Example: &din results in 1’b0
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 Relational Operators
Operator Operation Examples
Symbol Performed ain 3’b010, bin = 3’b100, cin=3’b111
din = 3’b01z, ein = 3’b01x
> Greater than ain > bin results false (1’b0)
< Less than ain < bin results true (1’b1)
>= Greater than or equal ain >= din results unknown (1’bX)
<= Less than or equal ain <= ein results unknown (1’bX)

n Used to compare values

n Returns a 1 bit scalar value of boolean true (1) / false (0)
n If any operand is Z or X, then the results are unknown

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 Equality Operators
Operator Operation Examples
Symbol Performed ain 3’b010, bin = 3’b100, cin=3’b111
din = 3’b01z, ein = 3’b01x

== Equality ain == cin results false (1’b0)

!= Inequality ein != ein results unknown (1’bX)
=== Case equality ein === ein results true (1’b1)
!== Case inequality ein !== din results true (1’b1)

n Used to compare values

n Returns a 1 bit scalar value of boolean true (1) / false (0)
n If any operand is Z or X, then the results are unknown
n Case equality and inequality includes x and z

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 Logical Operators
Operator Operation Examples
Symbol Performed ain = 3’b101, bin = 3’b000

! Not true !ain is false (1’b0)

&& Both expressions ain && bin results false (1’b0)
true
|| One or both
expressions true ain || bin results true (1’b1)

n Returns a 1 bit scalar value of boolean true (1) / false (0)

n If any operand is Z or X, then the results are unknown

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 Shift Operators
Operator Operation Examples
Symbol Performed ain = 4’b1010, bin = 4’b10X0

>> Shift right bin >> 1 results 4’b010X

<< Shift left ain << 2 results 4’b1000

n Shifts a vector left or right some number of bits

n Zero fills
n Shifted bits are lost

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 Miscellaneous Operators
Operator Operation Examples
Symbol Performed

?: Conditional (condition) ? true_val : false_val;

sig_out = (sel==2’b01) ? A : B ;

{} Concatenate ain = 3’b010, bin = 4’b1100

{ain,bin} results 7’b0101100

{{}} Replicate {3{2’b10}} results 6’b101010

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 Operator Precedence
n Operators default precedence
+ , - , ! , ~ (unary) Highest Priority
+ , - (Binary)
<< , >>
< , > , <= , >=
== , !=
&
^ , ^~ or ~^
|
&&
||
?: (ternary) Lowest Priority
n ( ) can be used to override default
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 Components of a Verilog Module

module Timing Specifications

(Port List)

Port Data Type Circuit Subprograms

Declarations Declarations Functionality
Instantiation task
input Net
Continuous Procedural function
output Register Assignment Blocks
System Tasks

inout assign initial

parameter
block Compiler
Directives
always
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 Behavioral Modeling

Continuous Assignment

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 Continuous Assignments

n Model the behavior of Combinatorial Logic by using

operators

wire adder_out = mult_out + out

n Continuous assignments /*implicit continuous
can be made when the assignment */
net is declared
is equivalent to
n OR by using the assign
statement wire adder_out;
assign adder_out = mult_out + out

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Continuous Assignments: Characteristics

1) Left-hand side (LHS) must be wire adder_out = mult_out + out

a net data type /*implicit continuous
2) Always active: When one of the assignment */
right-hand side (RHS) operands
changes, expression is evaluated, is equivalent to
and LHS net is updated
immediately wire adder_out;
assign adder_out = mult_out + out
3) RHS can be net, register, or
function calls
4) Delay values can be assigned to
model gate delays

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 Continuous Assignments
`timescale 1 ns/ 10 ps // Continuous Assignment
module mult_acc (out, ina, inb, clk, clr); assign adder_out = mult_out + out;
input [7:0] ina, inb; always @ (posedge clk or posedge clr)
input clk, clr; begin
output [15:0] out; if (clr)
out = 16'h0000;
wire [15:0] mult_out, adder_out; else
reg [15:0] out; out = adder_out;
end
parameter set = 10;
parameter hld = 20; multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));

specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify

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 Continuous Assignment - Example

module ander (out, ina, inb);

input [7:0] ina, inb;

output [7:0] out;

wire [7:0] out;

assign out = ina & inb;

endmodule

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 Simulation Time

n Simulation Time is the same for all modules during a

simulation run
– Simulation starts at time 0
– Simulation time advances when all processes at
current time are simulated

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One Type of Continuous Assignment Delay
n Regular Assignment Delay

assign #5 a = b; Statement Executed

Input ‘b’is sampled and is assigned

to ‘a’ 5 time units after ‘b’
has changed value.
b=1
a=b
b=1 a=1
b=0
0 2 7 12
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 Behavioral Modeling

Procedural Blocks

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 Two Structured Procedures (Blocks)
n initial Block - Used to initialize behavioral statements
for simulation
n always Block - Used to describe the circuit functionality
using behavioral statements

ð Each always and initial block represents a separate

process
ð Processes run in parallel and start at simulation time 0
ð However, statements inside a process execute
sequentially
ð always and initial blocks cannot be nested

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 Two Procedural Blocks

always and initial blocks

Behavioral Statements

Assignments:
Blocking
Nonblocking

Timing Specifications

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 Initial Block

n Consists of behavioral statements

n If there are more than one behavioral statement
inside an initial block, the statements need to be
grouped using the keywords begin and end.
n If there are multiple initial blocks, each block
executes concurrently at time 0.

ð Not supported by synthesis

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 Initial Block

n Used for initialization, monitoring, waveforms and

other processes that must be executed only once
during simulation
ð An intial block starts at time 0, executes only once during
simulation, and then does not execute again.
ð Behavioral statements inside an initial block execute
sequentially.
ð Therefore, order of statements does matter

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 Initial Block Example
module system;
Time Statement Executed
reg a, b, c, d;

// single statement 0 a = 1’b0; b = 1’b1;

initial
a = 1’b0; 5 c = 1’b0;
/* multiple statements:
needs to be grouped */ 15 d = 1’b0;
initial
begin 20 $finish
b = 1’b1;
#5 c = 1’b0;
#10 d = 1’b0;
end

initial
#20 $finish;

endmodule
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 Always Block
n Consists of behavioral statements
n If there are more than one behavioral statement
inside an always block, the statements can be
grouped using the keywords begin and end.
n If there are multiple always blocks, each block
executes concurrently.

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 Always Block

n Used to model a process that is repeated

continuously in a digital circuit
ð An always block starts at time 0 and executes the behavioral
statements continuously in a looping fashion.
ð Behavioral statements inside an initial block execute
sequentially.
ð Therefore, order of statements does matter.

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 Characteristics
1) Left-hand side (LHS) must be
a register data type: Can be a reg,
integer, real, or time variable or a
memory element
2) LHS can be a bit-select or part-select
3) A concatenation of any of the above
4) Right-hand side (RHS): All operators
can be used in behavioral reg [15:0] out;
expressions
always @ (posedge clk or posedge clr)
begin
if (clr)
out = 16'h0000;
else
out = adder_out;
end

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 Always Block - Example
module clock_gen (clk); Time Statement Executed
output clk;
reg clk; 0 clk = 1’b0

parameter period=50, duty_cycle=50; 25 clk = 1’b1

initial 50 clk = 1’b0

clk = 1’b0;
75 clk = 1’b1
always
#(duty_cycle*period/100) clk = ~clk; 100 $finish

initial
#100 $finish;

endmodule

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 Always/Initial Blocks

always/initial
blocks

Procedural Processes Behavioral Block

Assignments (Sensitivity List) Statements Execution

Blocking (=) Combinatorial if-else Sequential

(begin-end)
Nonblocking (<=) Clocked case
Concurrent
for loop (fork-join)

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 Procedural Assignments

n Let’s first look at the two different procedural

assignments:
– Blocking Assignment
– Nonblocking Assignment

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 Procedural Assignments

n Procedural Assignments - assignments that are

made inside the two structured procedures (initial
and always blocks)
n Update values of reg, integer, real, or time variables
n Value placed on a variable will remain unchanged
until another procedural assignment updates the
variable with a different value.

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 Two types of Procedural Assignments

n Blocking Assignment (=) : executed in the order they

are specified in a sequential block

n Nonblocking Assignment (<=) : allow scheduling of

assignments without blocking execution of the
statements that follow in a sequential block
– Recommended: Use Nonblocking assignments for clocked
processes when writing synthesizable code.

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 Blocking vs. Nonblocking Assignments

Blocking (=) Nonblocking (<=)

initial initial
begin begin
#5 a = b; #5 a <= b;
#10 c = d; #10 c <= d;
end end

a=b c=d a=b c=d

5 10 15 5 10 15

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 Simulation Time

n Simulation Time is the same for all modules during a

simulation run
– Simulation starts at time 0
– Simulation time advances when all processes at
current time are simulated

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3 Delay Controls for Procedural Assignment

n Regular Delay Control

n Intra-assignment Delay Control
n Zero Delay Control

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 Regular Delay Control
n Regular Assignment Delay

assign #5 a = b; Statement Executed

Input ‘b’is sampled and is assigned

to ‘a’ 5 time units after ‘b’
has changed value.
b=1
a=b
b=1 a=1
b=0
0 2 7 12
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 Intra-assignment Delay Control
n Intra-assignment Delay Control
initial initial
is equivalent to
a = #5 b; temp = b;
<=> #5 a = temp;

Statement Executed

b=0 Input ‘b’is sampled at the time ‘b’

a=b changes value and is assigned
to ‘a’ 5 time units after ‘b’
b=1 a=1 has changed value.
b=0
0 2 7 12
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 Zero Delay Control
n Zero Delay Control
initial Statement Executed
begin
All four statements will be executed at
a = 0; simulation time 0. However, since
b = 0; a = 1 and b = 1 have #0, they will be
end executed last.

initial n Not recommended to assign 2 different

begin values to a variable
#0 a = 1; – May cause a race condition
#0 b = 1; n Zero Delay Control - provides a useful
end way of controlling the order of
execution
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 Always/Initial Blocks

always/initial
blocks

Procedural Processes Behavioral Block

Assignments (Sensitivity List) Statements Execution

Blocking (=) Combinatorial if-else Sequential

(begin-end)
Nonblocking (<=) Clocked case
Concurrent
for loop (fork-join)

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 Processes and Behavioral Statements

n Now, let’s look at the two different processes:

– Combinatorial Process
– Clocked Process
n Let’s also look at some behavioral statements

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 Sensitivity List

n Sensitivity List:

always @(sensitivity_list)
begin
-- Statement #1
-- … … … … ..
-- Statement #N
end

n This procedural block (process) executes after a

change in any signal in the Sensitivity List

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 Two Types of Processes
• Combinatorial Process
– Sensitive to all inputs used in
the combinatorial logic a
c
• Example b
always @(a or b or sel)
sel
sensitivity list includes all inputs used
in the combinatorial logic

• Clocked Process d D Q q
– Sensitive to a clock or/and
control signals clk
ENA
• Example CLRN

always @(posedge clk or negedge clr) clr

sensitivity list does not include the d input,

www.pld.com.cn only the clock or/and control signals
 Combinatorial Process

n Let’s first look at:

– Combinatorial Process Examples

• Combinatorial Process
– Sensitive to all inputs used in
the combinatorial logic a
c
• Example b
always @(a or b or sel)
sel
sensitivity list includes all inputs used
in the combinatorial logic

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 Behavioral Statements

n Behavioral Statements
– IF-ELSE statement
– CASE statement
– Loop statements

n These Behavioral Statements can also be used in a

Clocked Process

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 If-Else Statements
n Format: n Example:
if (<condition1>) always @(sela or selb or a or b or c)
sequence of statement(s) begin
else if (sela)
if (<condition2>) q = a;
sequence of statement(s) else
if (selb)
. q = b;
. else
else q = c;
sequence of statement(s) end

c
b q
a
selb
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 If-Else Statements

n Conditions are evaluated in order from top to bottom

– Prioritization
n The first conditon, that is true, causes the
corresponding sequence of statements to be
executed.
n If all conditions are false, then the sequence of
statements associated with the “else” clause is
evaluated.

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 Case Statement
n Format: n Example:
case (expression) always @(sel or a or b or c or d)
<condition1> : begin
sequence of statement(s) case (sel)
<condition2> : 2’b00 :
sequence of statement(s) q = a;
2’b01 :
. q = b;
2’b10 :
. q = c;
default :
default :
sequence of statement(s) q = d;
endcase endcase
end
a
b q
c
d
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2
 Case Statement

n Conditions are evaluated at once

– No Prioritization
n All possible conditions must be considered
n default clause evaluates all other possible conditions
that are not specifically stated.

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 Two Other Forms of Case Statements
n casez casez (encoder)
4’b1??? : high_lvl = 3;
– Treats all ‘z’values
4’b01?? : high_lvl = 2;
in the case 4’b001? : high_lvl = 1;
conditions as don’t 4’b0001 : high_lvl = 0;
cares, instead of default : high_lvl = 0;
logic values endcase
– All ‘z’ values can • if encoder = 4’b1zzz, then high_lvl = 3
also be represented
by ‘?’ casex (encoder)
4’b1xxx : high_lvl = 3;
n casex
4’b01xx : high_lvl = 2;
– Treats all ‘x’ and ‘z’ 4’b001x : high_lvl = 1;
values in the case 4’b0001 : high_lvl = 0;
conditions as don’t default : high_lvl = 0;
cares, instead of endcase
logic values • if encoder = 4’b1xzx, then high_lvl = 3

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 Loop Statements

n forever loop - executes continually

n repeat loop - executes a fixed number of times
n while loop - executes if expression is true
n for loop - executes once at the start of the loop and
then executes if expression is true

ð Loop statements - used for repetitive operations

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 Forever and Repeat Loops

n forever loop - executes continually

initial
begin Clock with period
clk = 0; of 50 time units
forever #25 clk = ~clk;
end

n repeat loop - executes a fixed number of times

if (rotate == 1)
repeat (8) Repeats a rotate
begin operation 8 times
tmp = data[15];
data = {data << 1, temp};
end
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 While Loop

n while loop - executes if expression is true

initial
begin
count = 0; Counts from 0 to 100
while (count < 101) Exits loop at count 101
begin
$display (“Count = %d”, count);
count = count + 1;
end
end

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 For Loop
n for loop -
integer i; // declare the index for the FOR LOOP
executes once
at the start of always @(inp or cnt)
the loop and begin
result[7:4] = 0;
then executes result[3:0] = inp;
if expression is if (cnt == 1)
true begin
for (i = 4; i <= 7; i = i + 1)
begin
4-bit Left Shifter
result[i] = result[i-4];
end
result[3:0] = 0;
7 6 5 4 3 2 1 0 end

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 Clocked Process
n Let’s now look at:
– Clocked Process Examples
– Functional for synthesis
n Nonblocking assignments (<=) are used for clocked
processes when writing synthesizable code

• Clocked Process d D Q q
– Sensitive to a clock or/and
control signals clk
ENA
• Example CLRN

always @(posedge clk or negedge clr) clr

sensitivity list does not include the d input,

only the clock or/and control signals
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 Functional Latch vs. Functional Flipflop
Level-sensitive Latch Edge-triggered Flipflop
module latch (d, gate,q); module dff ( d, clk, q);

input d, gate ; input d, clk ;

output q ; output q;

wire d, gate ; wire d, clk;

reg q ; reg q ;

always @(d or gate) always @(posedge clk)

if (gate) q <= d ;
q <= d ; endmodule
endmodule
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 Synchronous vs. Asynchronous
Synchronous Preset & Clear Asynchronous Clear
module sync (d,clk, clr, pre, q); module async (d,clk, clr, q);

input d, clk, clr, pre ; input d, clk, clr ;

output q ; output q ;
reg q ;
reg q ;
always @(posedge clk)
begin always @(posedge clk or posedge clr)
if (clr) begin
q <= 1’b0 ; if (clr)
else if (pre) q <= 1’b0 ;
q <= 1’b1 ; else
else q <= d ;
q <= d ;
end
end
endmodule endmodule

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 Clock Enable
Clock Enable
module clk_enb (d, ena, clk, q) ;

input d, ena, clk ;

output q ;

reg q ;

/* If clock enable port does not exist in target technology,

a mux is generated */

always @( posedge clk )

if (ena)
q <= d ;
endmodule

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 Functional Counter
module cntr(q, aclr, clk, func, d);
input aclr, clk;
input [7:0] d;
input [1:0] func; // Controls the functionality
output [7:0] q;
reg [7:0]q;
always @(posedge clk or posedge aclr) begin
if (aclr)
q <= 8'h00;
else
case (func)
2'b00: q <= d; // Loads the counter
2'b01: q <= q + 1; // Counts up
2'b10: q <= q - 1; // Counts down
2'b11: q <= q;
endcase
end
endmodule

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 Always/Initial Blocks

always/initial
blocks

Procedural Processes Behavioral Block

Assignments (Sensitivity List) Statements Execution

Blocking (=) Combinatorial if-else Sequential

(begin-end)
Nonblocking (<=) Clocked case
Concurrent
for loop (fork-join)

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 Block Execution

n Finally, let’s look at the two different block execution

inside an always block:
– Sequential Blocks
– Parallel Blocks

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 Two Types of Block Executions

n Sequential Blocks - statements between begin and

end execute sequentially
– If there are multiple behavioral statements inside an initial
and always block and you want the statements to execute
sequentially, the statements must be grouped using the
keywords begin and end.

n Parallel Blocks - statements between fork and join

execute in parallel
– If there are multiple behavioral statements inside an initial
and always block and you want the statements to execute in
parallel, the statements must be grouped using the keywords
fork and join.

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 Sequential vs. Parallel Blocks

n Sequential and Parallel Blocks can be nested

Time Statement Executed

initial
fork
10 a=1
#10 a = 1;
#15 b = 1;
15 b=1
begin
#20 c = 1;
20 c=1
#10 d = 1;
end
25 e=1
#25 e = 1;
join
30 d=1

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 Behavioral Modeling

Tasks and Functions

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 Components of a Verilog Module

module Timing Specifications

(Port List)

Port Data Type Circuit Subprograms

Declarations Declarations Functionality
Instantiation task
input Net
Continuous Procedural function
output Register Assignment Blocks
System Tasks

inout assign initial

parameter
block Compiler
Directives
always
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 Verilog Functions and Tasks

n Function and Tasks are subprograms.

n Useful for code that is repetitive in module
n Add to module readability
n Function
– Return a value based on its inputs
– Produces combinatorial logic
– Used in expressions: assign mult_out = mult (ina, inb);
n Tasks
– Like procedures in other languages
– Can be combinatorial or registered.
– Task are invoked as statement: stm_out (nxt, first, sel, filter);

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 Create a Function for the multiplier

adder_out out
ina
+ D Q

mult_out clk
X
inb
CLRN
clr

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 Function Definition - Multiplier
Function Definition:
function [15:0] mult;
input [7:0] a, b ;
reg [15:0] r;
integer i ;
begin
if (a[0] == 1)
r = b;
else
r=0;
for (i =1; i <=7; i = i + 1)
begin
if (a[i] == 1)
r = r +b <<i ;
end
mult = r;
end
endfunction

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 Function Invocation - MAC
`timescale 1 ns/ 10 ps assign adder_out = mult_out + out;

module mult_acc (out, ina, inb, clk, clr); always @ (posedge clk or posedge clr)
begin
input [7:0] ina, inb; if (clr)
input clk, clr; out = 16'h0000;
output [15:0] out; else
out = adder_out;
wire [15:0] mult_out, adder_out; end
reg [15:0] out;
// Function Invocation
parameter set = 10;
parameter hld = 20; assign mult_out = mult (ina, inb);
specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify

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Create a Task for the Statemachine Output
RESET
Inputs: Outputs:
reset select
nw Idle first
nxt = 0 nw = 1
first = 0
nxt
nw = 0
Tap1
nw = 1 select = 0
Tap4 first = 1
select = 3
nxt = 1

Tap2
Tap3 select = 1
select = 2 first = 0

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 Task Definition - Statemachine Output
task stm_out (nxt, first, sel, filter);
input [2:0] filter;
output nxt, first;
output [1:0] sel;
reg nxt, first;
reg [1:0] sel;
parameter idle=0, tap1=1, tap2=2, tap3=3, tap4=4;
begin
nxt = 0; first = 0;
case (filter)
tap1: begin sel = 0; first = 1; end
tap2: sel = 1;
tap3: sel = 2;
tap4: begin sel = 3; nxt = 1; end
default: begin nxt = 0; first = 0; sel = 0; end
endcase
end
endtask

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 Task Invocation - Statemachine
module stm_fir (nxt, first, sel, clk, reset, nw);
input clk, reset, nw;
output nxt, first;
output [1:0] sel;
reg nxt, first;
reg [1:0] sel;
reg [2:0] filter;
parameter idle=0, tap1=1, tap2=2, tap3=3, tap4=4;
always @(posedge clk or posedge reset)
begin if (reset) filter = idle;
else case (filter)
idle: if (nw==1) filter = tap1;
tap1: filter = tap2;
tap2: filter = tap3;
tap3: filter = tap4;
tap4: if (nw==1) filter = tap1;
else filter = idle; endcase end
always @(filter)
// Task Invocation
stm_out (nxt, first, sel, filter);
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 Differences
Functions Tasks
n Can enable another function but n Can enable other tasks and
not another task functions
n Always executes in zero n May execute in non-zero
simulation time simulation time
n Can not contain any delay, event, n May contain delay, event, or
or timing control statements timing control statements
n Must have at least one input n May have zero or more input,
argument output, or inout arguments
n Always return a single value n Returns zero or more values
n Can not have output or inout
arguments

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 Review - Behavioral Modeling
Continuous Assignment Procedural Block
module full_adder4(fco, fsum, cin, a, b); module fll_add4(fco, fsum, cin, a, b);

output [3:0] fsum; output [3:0] fsum;

output fco; output fco;
input [3:0] a, b; input [3:0] a, b;
input cin; input cin;

wire [3:0] fco, fsum; reg [3:0] fco, fsum;

wire cin;
always @(cin or a or b)
assign {fco, fsum} = cin + a + b; {fco, fsum} = cin + a + b;

endmodule endmodule

n Will produce the same logical model and functionality

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 Structural
Modeling

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 Levels of Abstraction
Behavioral Modeling
Behavioral Models input1, .., inputn
if (input1)
output1, .., outputn

(function only) for (j=0, j<8, j=j+2)

#5 output1 = 1’b0;
else
for (j=1, j<8, j=j+2)
#5 output1 = 1’b1;

RTL Models Abstract

(function and
inferred structure)
Detailed Structural Modeling

Gate Level Models

Higher-level Component (function and
input1 output1
structure)
Lower-level
Component1
Switch Level Models
Lower-level
Component1
(function and
inputn outputn structure)

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 Stuctural Modeling

n Defines function and structure of a digital circuit

n Adds to Hierarchy

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 Verilog Structural Modeling

n Component Level Modeling - instantiating user-

created lower-level designs (components)
n Gate Level Modeling - instantiating Verilog built-in
gate primitives
– and, nand, or, nor, xor, xnor
– buf, bufif0, bufif1, not, notif0, notif1
n Switch Level Modeling - instantiating Verilog built-in
switch primitives
– nmos, rnmos, pmos, rpmos, cmos, rcmos
– tran, rtran, tranif0, rtranif0, tranif1, rtrainif1, pullup, pulldown
ð Switch level modeling will not be discussed

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 Verilog Structural Modeling

n Verilog has predefined gate primitives

Primitive Name Function Primitive Name Function

and n-input AND gate buf n-output buffer

nand n-input NAND gate not n-output buffer

or n-input OR gate bufif0 tristate buffer lo enable

nor n-input NOR gate bufif1 tristate buffer hi enable

xor n-input XOR gate notif0 tristate inverter lo enable

xnor n-input XNOR gate notif1 tristate inverter hi enable

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 Instantiation of Gate Primitives

n Instantiation Format:
<gate_name> #<delay> <instance_name> (port_list);

– <gate_name> - The name of gate

– #delay - The gate delay
• Not required, used for simulation
– <instance_name> - Any name that you want
• Not required for Verilog gate primitives
– (port_list) - The port connection

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 Connecting ports by ordered list
n For Verilog gate primitives, the module half_adder (co, sum, a, b);
first port on the port list is the output,
followed by the inputs. output co, sum;
– <gate_name> input a, b;
• and
• xor parameter and_delay = 2;
– #delay - OPTIONAL
parameter xor_delay = 4;
• 2 time unit for the and gate
and #and_delay u1(co, a, b);
• 4 time unit for the xor gate
xor #xor_delay u2(sum, a, b);
– <instance_name> - OPTIONAL
• u1 for the and gate endmodule
• u2 for the xor gate
– (port_list) a co
• (co, a, b) - (output, input, input)
• (sum, a, b) - (output, input, input)
b sum
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 User-Defined Primitives (UDP)

n Allows users to define their own primitives

n Defined as truth tables
n Both combinatorial and clocked logic may be
represented in the truth table
n Once defined, a UDP is used exactly the same as a
built-in primitive
n Characteristics:
– Only 1 outuput
– Must have at least 1 input but no more than 10

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 UDP - Latch
primitive latch (q, clock,data); // Level sensitive, active low
output q;
reg q;
input clock, data;
initial q = 1'b0; // Output is initialized to 1'b0.
// Change 1'b0 to 1'b1 for power up Preset
table
// clock data current state next state
0 1 :?: 1;
0 0 :?: 0;
1 ? :?: -; // ‘-’= no change
endtable
endprimitive

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 UDP - Register
primitive d_edge_ff (q, clock,data); //edge triggered, active high
output q;
reg q;
input clock, data;
initial q = 1'b0; //Output is initialized to 1'b0.
//Change 1'b0 to 1'b1 for power up Preset
table
// clk data state next
(01) 0 :?: 0;
(01) 1 :?: 1;
(0x) 1 :1: 1;
(0x) 0 :0: 0;
(?0) ? :?: -; // ignore negative edge of the clock
? (??) :?: -; // ignore data changes on clock levels
endtable
endprimitive

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 Instantiation of lower-level Components

n Instantiation Format:

<component_name> #<delay> <instance_name> (port_list);

– <component_name> - The name of your lower-level

component
– #delay - The component delay
• Not required, used for simulation
– <instance_name> - Any name that you want
• Required, unlike Verilog gate primitives
– (port_list) - The port connection

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 Connecting ports by ordered list or by name
n For user-created lower-level module full_adder(fco, fsum, cin, a, b);
components, the port connection is
defined by the module declaration’s output fco, fsum;
port list order. input cin, a, b;
wire c1, s1, c2;
module half_adder (co, sum, a, b);
– Therefore for the first half_adder : half_adder u1(c1, s1, a, b);
– The ports are connected by ordered list half_adder u2(.a(s1), .b(cin),
– The order of the port connection does .sum(fsum), .co(c2));
matter or u3(fco, c1, c2);
• co -> c1, sum -> s1, a -> a, b -> b
endmodule
n For the second half_adder:
– The ports are connected by name c1
a u3
u1 s1 c2 fco
– The order of the port connection does b u2
not matter cin fsum
• a -> s1, b -> cin, sum -> fsum, co ->c2

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 Port Connection Rules
Port connections when modules
are instantiated within other
modules
driving
output
into a
Ports consist of 2 units: reg or net net
input
1) internal to the module
driving from a net
2) external to the module inout
reg or net

net driving
from/into a
net

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 Defparam
n Used to change the value of a lower-level component
parameter(s)
module full_adder(fco, fsum, cin, a, b);

output fco, fsum;

input cin, a, b;
wire c1, s1, c2;

defparam u1.and_delay = 4, u1.xor_delay = 6;

defparam u2.and_delay = 3, u2.xor_delay = 5;
half_adder u1(c1, s1, a, b);
half_adder u2(.a(s1), .b(cin),
.sum(fsum), .co(fco));
or u3(fco, c1, c2);

endmodule
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 Simulation Time

n Simulation Time is the same for all modules during a

simulation run
– Simulation starts at time 0
– Simulation time advances when all processes at
current time are simulated

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 Gate Delays

n Rise Delay - transition from 0, x, or z to a 1

n Fall Delay - transition from 1, x, or z to a 0
n Turn-off Delay - tranzition from 0, 1 or x to a z
<component_name> #(Rise, Fall, Turnoff) <instance_name> (port_list);

and #(2) u1 (co, a, b); // Delay of 2 for all transitions

and #(1, 3) u2 (co, a, b); // Rise = 1, Fall = 3
bufif0 #(1, 2, 3) u3 (out, in, enable) ;
// Rise = 1, Fall = 2, Turn-off = 3

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 Min/Typ/Max Values

n Min Value - the minimum delay that you expect the

gate to have
n Typ Value - the typical delay that you expect the gate
to have
n Max Value - the maximum delay that you expect the
gate to have
#(Min:Typ:Max, Min:Typ:Max, Min:Typ:Max)

and #(1:2:3) u1 (co, a, b);

and #(1:2:3, 1:2:3) u2 (co, a, b);
bufif0 #(2:3:4, 2:3:4, 3:4:5) u3 (out, in, enable) ;

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 Verilog Summary

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 Verilog Environment

n Contains a Design Block and a Stimulus Block

System Stimulus Block

– Connects the Design Block with the TestBench

Stimulus Block: Design Block:

TestBench (Function and
(Test Vectors) Timing)

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 Verilog - Design Block
module counter(q, clk, clr, f, in); else
input clk, clr; case (f)
input [1:0] f; 2'b00: q = d; // Loads the counter
input [7:0] d; 2'b01: q = q + 1; // Counts up
output [7:0] q; 2'b10: q = q - 1; // Counts down
reg [7:0] q; 2'b11: q = q;
parameter set = 4, hold = 1; endcase
end
clock_gen #(100, 50) clock(clk);
specify
always @(posedge clk or posedge clr) $setup (d, posedge clk, set);
$hold (posedge clk, d, hold);
begin
endspecify
if (clr)
q = 8'h00;
endmodule

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 Verilog - Stimulus Block
module counter_test(clrd, fd, ind, clkd);
input clkd;
output clrd;
output [1:0] fd;
output [7:0] ind;
reg clrd;
reg [1:0] fd;
reg [7:0] ind;
clock_gen #(100, 50) clockd(clkd);
always @(posedge clkd) begin
clrd=1; fd=0; ind=0;
#100 clrd=1; fd=0; ind=0;
#100 clrd=0; fd=0; ind=8’b01010101;
#100 clrd=0; fd=3; ind=8’b11111111;
#100 clrd=0; fd=1; ind=8’b10101010;
#100 clrd=0; fd=2; ind=8’b11001100; end
endmodule
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 Verilog - System Stimulus Block
module counter_system;
wire clear, sys_clock;
wire [1:0] func;
wire [7:0] datain, result;

clock_gen #(100,50) system_clock(sys_clock);

counter #(4, 1) op(.clr(clear), .clk(sys_clock), .f(func), .d(datain), .q(result));
counter_test op_test(.clrd(clear), .clkd(sys_clock), .fd(func), .ind(datain));

initial begin
$display(“\t\t Time clear sys_clock func datain result”);
$monitor($time,,clear,,,,,,,,,,sys_clock,,,,,,,,,,func,,,,,,,datain,,,,,,result);

#1300 $finish; end

endmodule

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 Verilog Environment
counter_system
clock_gen

clk sys_clock
counter

counter_test clk
q result
clear
clkd clrd clr
func
fd f
datain
ind in

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 Verilog

n Used for both simulation and synthesis

– Two sets of constructs:
• Simulation Constructs
• Synthesis Constructs
– Supported by synthesis tools

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Typical Simulation Design Flow

Verilog Verilog
Model TestBench

Optional

Simulation
Compiler

Simulation Test
Model Vectors

Waveform Verilog
Text Output
Simulation

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Typical Synthesis Design Flow

Verilog Technology
Model Library

Synthesis
Compiler

Timing Analysis Netlist Place/Route

Text Output
Test
Simulation Vectors
Waveform

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 Verilog
Synthesis Simulation
n Functionality n Functionality and Timing
module dff ( d, clk, q); module dff ( d, clk, q);

input d, clk ;
input d, clk ;
output q;
output q;
wire d, clk;
wire d, clk; reg q ;
reg q ;
always @(posedge clk)
always @(posedge clk) q=d;
specify
q=d;
$setup (d, posedge clk, set);
endmodule $hold (posedge clk, d, hold);
endspecify

endmodule

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 Appendix

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 System Tasks and Functions

n Defined by (dollar sign) $<keyword>

n Located before the module declaration

n $stop; - stop simulation

n $finish; - quit simulation
n $display(… ); - display value
n $monitor(… ); - monitor value
n $time; - current simulation time

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 Compiler Directives

n Defined by (back tick) `<keyword>

n Located before the module declaration
n `timescale <reference_time_unit> / <time_precision>
– <reference_time_unit> specifies the unit of measurement for
times and delays
– <time_precision> specifies the precision to which the delays are
rounded off during simulation
– Only 1, 10, and 100 are valid integers for specifying time unit and
time precision
– Example: `timescale 1 ns / 10 ps

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 Compiler Directives

n `define - assigns a constant value

– Example: `define SIZE 32
– Difference between parameter:
• parameter has global visibility
• `define is visible locally to that macrofunction
n `include - includes entire contents of a Verilog source
file
– Example: `include test.v
• test.v is a separate design file

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 Conditional Compilation
// Conditional Compilation

`ifdef TEST // Compile module counter only if text macro TEST is defined
module counter;
…
..
endmodule
`else // Compile the module counter_test as default
module counter_test;
…
…
endmodule
`endif
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 Timing Specifications

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 Specify Blocks

n Path Delay - the delay between a source (input or inout)

pin and a destination (output or inout) pin
n Path Delays are assigned in Specify Blocks with the
keywords specify and endspecify

n Statements in a Specify Block can do the following:

– Assign pin-to-pin timing delays
– Set up timing checks in the circuits
– Define specparam constants

n Alternative to the #<delay> construct

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 Parallel Connection

n Parallel Connection - specified by the symbol (=>)

n Format:
<source> => <destination> = <delay>

// Single bit a and b // 2-bit Vector a and b

a => b = 5; a => b = 5;

Source Destination is equivalent to

a[0] => b[0] = 5;

a[1] => b[1] = 5;

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 Full Connection

n Full Connection - specified by the symbol (*>)

– Each bit in the source is connected to each bit in the
destination
n Format: <source> *> <destination> = <delay>

Source Destination // 2-bit Vector a and b

a *> b = 5;

is equivalent to

a[0] *> b[0] = 5;

a[1] *> b[1] = 5;
a[0] *> b[0] = 5;
a[1] *> b[1] = 5;
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 Specparam

n Specparam - assigning a value to a sympbolic name

for a timing specification
– Similar to parameter but used in specify blocks

specify

specparam a_to_b = 5;

a => b = a_to_b;

end specify

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 Rise, Fall, Turn-off and Min/Typ/Max Values

specify

specparam rise = 4:5:6;

specparam fall = 6:7:8;
specparam turnoff = 5:6:7;

a => b = (rise, fall, turnoff);

end specify

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 Timing Checks
n $setup task - system task that n $hold task - system task that
checks for the setup time checks for the hold time
$setup(data_event, reference_event, limit); $hold(reference_event, data_event, limit);
– data_event - monitored for – reference_event - establishes
violations a reference for monitoring the
– reference_event - establishes dat_event signal
a reference for monitoring the – data_event - monitored for
dat_event signal violations
– limit - minimum time for setup – limit - minimum time for hold

clock specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
data
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
setup hold endspecify
time time
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 OVI Synthesis Guidelines

n Fully supported constructs for all synthesis tool

Verilog Construct
Module
Module Instantiations
Port Declarations
Net Date Types
wire, tri, supply1,supply0
Register Data Types
reg, integer
Parameter Constants
Integer values
Function and Tasks
begin and end statements
disable of name statement groups
if, if-else, case,casex,casez
Blocking
procedural and continuous

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 OVI Synthesis Guidelines

n Partially support constructs

n Constructs used with certain restrictions
n Could vary among synthesis tools
Partially Supported
always (always @ .....)
Edge-sensitive
posedge and negedge
for Loop
Bit and part select of vectors
Procedural
non blocking ( <= )
Operators (logical,equalit,relational,reduction
arithmatic,shift,concatenate, replicate
conditional )
Operator by the power of 2 only
( multiply, divide, modulo)

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 OVI Synthesis Guidelines

n Optional Ignore constructs are not supported by all synthesis

tools.
n Synthesis should ignore construct
Optional-Ignored
Timing and delays (#)
Specify Block
System tasks or functions ($)

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 OVI Synthesis Guidelines

n Optional-Aborts are not supported by all synthesis tools.

n Synthesis must abort when encountered
Optional-Abort
Any partially support construct used in a
non-supported way.
Net Types
wand,triand,wor,trior,tri0,tri1,trireg
Loops
forever, repeat , while
Identify operators ( === !== )
wait
initial
fork-join
Procedural deassign
force, release
User Defined Primitives
Some Built-in Primitives

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