INDEX

1. Full Adder And Suubtractor

2. Ripple Carry Adder

3. Carry-Look Ahead Adder

4. Synthesis of Flip-Flop

5. Register And Counter

6. Booth’s Algorithm

7. Arithmatic And Logic Unit

8. CPU Design
 Experiment :01

Aim: A] To design a Full Adder

B] To design a Full Subtrator

Apparatus: Virtual lab

Theory:
A] Full adder : Full adder is a digital circuit used to calculate the
sum of three binary bits. Full adders are complex and difficult to
implement when compared to half adders. Two of the three bits are
same as before which are A, the augend bit and B, the addend bit.
The additional third bit is carry bit from the previous stage and is
called 'Carry' – in generally represented by CIN. It calculates the
sum of three bits along with the carry. The output carry is called
Carry – out and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S,
Carry OUT as outputs is shown below.

Full Adder Block Diagram and Truth Table

S = A'B'Cin + A'BCin' + ABCin
COUT = AB + ACIN + BCIN
B] Full Subtractor : A full subtractor is a combinational circuit that
performs subtraction involving three bits, namely A (minuend), B
(subtrahend), and Bin (borrow-in) . It accepts three inputs: A
(minuend), B (subtrahend) and a Bin (borrow bit) and it produces
two outputs: D (difference) and Bout (borrow out). The logic
symbol and truth table are shown below.

Full Subtractor Block Diagram and Truth Table

D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin

Result:- Thus, successfully we have designed Full Adder and Full

Subtractor
 Experiment :02
Aim: To design the Ripple Carry Adders

Apparatus: Virtual lab

Theory: Arithmetic operations like addition, subtraction, multiplication,

division are basic operations to be implemented in digital computers using
basic gates like AND, OR, NOR, NAND etc. Among all the arithmetic
operations if we can implement addition then it is easy to perform
multiplication (by repeated addition), subtraction (by negating one
operand) or division (repeated subtraction).

Half Adders can be used to add two one bit binary numbers. It is also
possible to create a logical circuit using multiple full adders to add N-bit
binary numbers. Each full adder inputs a Cin, which is the Cout of the
previous adder. This kind of adder is a Ripple Carry Adder, since each
carry bit "ripples" to the next full adder. The first (and only the first) full
adder may be replaced by a half adder. The block diagram of 4-bit
RippleCarry Adder is shown here below -

sum = A+B

carry = A . B

Procedure:
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design the circuit we need 3 full adder, 1 half adder, 8 Bit switch(to
give input), 3 Digital display(2 for seeing input and 1 for seeing output
sum), 1 Bit display(to see the carry output), wires.
 3. The pin configuration of a component is shown whenever the mouse is
hovered on any canned component of the palette or press the 'show
pin config' button. Pin numbering starts from 1 and from the bottom
left corner(indicating with the circle) and increases anticlockwise.
4. For half adder input is in pin-5,8 output sum is in pin-4 and carry is
pin-1, For full adder input is in pin-5,6,8 output sum is in pin-4 and
carry is pin-1
5. Click on the half adder component(in the Adder drawer in the pallet)
and then click on the position of the editor window where you want to
add the component(no drag and drop, simple click will serve the
purpose), likewise add 3 full adders(from the Adder drawer in the
pallet), 8 Bit switches, 3 digital display and 1 bit Displays(from Display
and Input drawer of the pallet,if it is not seen scroll down in the
drawer)
6. To connect any two components select the Connection menu of
Palette, and then click on the Source terminal and click on the target
terminal. According to the circuit diagram, connect all the
components, connect 4 bit switches to the 4 terminals of a digital
display and another set of 4 bit switches to the 4 terminals of another
digital display. connect the pin-1 of the full adder which will give the
final carry output. connect the sum(pin-4) of all the adders to the
terminals of the third digital display(according to the circuit diagram
shown in screenshot). After the connection is over click the selection
tool in the pallete.
7. To see the circuit working, click on the Selection tool in the pallet then
give input by double clicking on the bit switch, (let it be 0011(3) and
0111(7)) you will see the output on the output(10) digital display as
sum and 0 as carry in bit display.
Observation:

Result: Hence we design the Ripple Carry Adders

 Experiment : 03
Aim : To Design Carry Lookahead Adders.
Apparatus: Virtual lab
Theory: To reduce the computation time, there are faster ways to add two binary
numbers by using carry lookahead adders. They work by creating two signals P and G
known to be Carry Propagator and Carry Generator. The carry propagator is
propagated to the next level whereas the carry generator is used to generate the
output carry ,regardless of input carry. The block diagram of a 4-bit Carry Lookahead
Adder is shown here below -

Procedure:
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design the circuit we need 7 half adders, 3 OR gates, 1 V+(to give 1
as input), 3 Digital displays(2 for seeing input and 1 for seeing output
sum), 1 Bit display(to see the carry output), and wires.
3. The pin configuration of a component is shown whenever the mouse is
hovered on any canned component of the palette or press the 'show
pin config' button. Pin numbering starts from 1 and from the bottom
left corner(indicating with the circle) and increases anticlockwise.
4. For half adder input is in pin-5,8 output sum is in pin-4 and carry is
pin-1
5. Click on the half adder component(in the Adder drawer in the pallet)
and then click on the position of the editor window where you want to
add the component(no drag and drop, simple click will serve the
purpose), likewise add 6 more full adders(from the Adder drawer in
the pallet), 3 OR gates(from Logic Gates drawer in the pallete), 1 V+, 3
 digital display and 1 bit Displays(from Display and Input drawer of the
pallet,if it is not seen scroll down in the drawer)
6. To connect any two components select the Connection menu of
Palette, and then click on the Source terminal and click on the target
terminal. According to the circuit diagram connect all the components,
connect V+ to the upper input terminals of 2 digital displays according
to your input. connect the OR gates according to the diagram shown
in the screenshot connect the pin-1 of the half adder which will give
the final carry output. connect the sum(pin-4) of those adders to the
terminals of the third digital display which will give output sum. After
the connection is over click the selection tool in the pallete.
7. See the output, in the screenshot diagram we have given the value
0011(3) and 0111(7) so get 10 as sum and 0 as carry.you can also use
many bit switches instead of V+ to give input and by double clicking
those bit switches can give different values and check the result.
Observation:

Result: Hence we Design Carry Lookahead Adders

 Experiment 04
Aim: To Synthesis of Flip Flop.

Apparatus: Virtual Lab

Theory:
Synthesis of Flip Flops

Till now the experiments are based only on the combinational

circuits where output at any instance depends only on the current
input. Most of components of digital logic consists combinational
circuits but they likely to have memory elements too. Those type of
circuits are known to be sequential circuits. In a sequential circuit
the present output is not only determined by the present input but
also depends on the past output. flip-flops are the simplest kind of
sequential circuits. A flip-flop can maintain a binary state identity
which means it can act as 1-bit memory cell. There are different
kind of flip-flops depending on the number of inputs or the way the
inputs affect the states. Basic flip-flop: A basic flip-flop circuit can
be constructed using two cross-coupled NAND/NOR gates shown
below. Each flip-flop has two outputs, Q and Q; and two inputs, set
and reset. When the set input goes to 1 the Q output goes to 1 and
the Q'goes to I when reset goes to 1. But when both set, reset are 1,
both Q. Q'outputs go to 0 for basic flip-flop circuit with NOR gates.
In basic flip-flop circuit with NAND gates, when both input go to 0,
both outputs go to 0 violating the fact that the outputs of the flip-
flop have to be complement of each other.

There are various different kind of flip-flops. Some of the common

flip-flops are: R-S flip-flop, D flip-flop, J-K flip- flop, T flip-flop etc.
1. Clocked RS flip-flop : The basic flip-flop is modified by adding
some gates to the inputs so that the flip-flop changes state only
when the clock pulse is 1. The truth table for this type of flip-flop
 is shown below. If R is high then reset state occurs and when S=1
then set state. However, if both the inputs are 1 then it violates
normal operation of flip-flop.

2. JK flip-flop JK flip-flop is a refinement of RS flip-flop where the

indeterminate state of RS type is defined. Input J and K are
respectively the set and reset inputs of the flip-flop. When both
the inputs are high then the output of the flip-flop switches to its
complemented state.A clocked JK flip-flop is shown below.

In level triggred JK flip-flops, at J=1 and K=1, a timimg problem, known as

race around condition arises which can be explained by the following diagram.
Let the width of a clock pulse is tp and the current output Q is 1. when the
clock is applied, after the propagation delay, say dt, the output will toggle and
now the output Q will be 0. If dt is less than tp, then after dt the output Q will
again toggle and become 1. Thus the output will oscillate between 0 and 1
within the tp interval, so at the end of the clock pulse tp, the output will be
ambiguous.

3.
Master slave JK flip-flop overcome this race around condition. The following
figure depicts the circuit diagram.
However, the master slave circuit, though handles race around condition, it
may work improperly initially, if it has inconsistent initialization. Ideally,
initially the master and the slave should have the same value, but if it does
not, then it leads to inconsistent initialization, for which the circuit behaves
improperly. Bellow is a case showing the improper output for an inconsistent
initialization. Here, at clock=1, the master is supposed to change its state
acordingly, but.......
The problem occured due to the inconsistent initialization in the master slave
JK flip-flop can be avoided by asynchronously presetting or clearing the flip-
flop. The circuit diagram is shown bellow.
D flip-flop The D flip-flop is used to transfer data to the flip-flop. It is
basically the JK flip-flop where the the K input is inverted. The circuit diagram
of the D flip-flop is shown below,

4. Tflip-flop The T or "toggle" flip-flop changes its output on each clock

edge. The truth table as follows:

Result: Hence we have perform Synthesis of Flip Flop.

 Experiment : 05

Aim: To Design of Registers and Counters

Apparatus: Virtual Lab
Theory:
In a sequential circuit the present output is determined by both the present
input and the past output. In order to receive the past output some kind of
memory element can be used. The memory element commonly used in the
sequential circuits are time-delay devices. The block diagram of the sequential
circuit-

A circuit with flip-flops is considered a sequential circuit even in the absence of

combinational logic. Circuits that include flip-flops are usually classified by the
function they perform. Two such circuits are registers and counters:

1. Register is a group of flip-flops. Its basic function is to hold information

within a digital system so as to make it available to the logic units during
the computing process.

2. Counter is essentially a register that goes through a predetermined

sequence of states.

There are various different kind of Flip-Flops. Some of the common flip-flops
are: R-S Flip-Flop, D Flip-Flop, J-K Flip-Flop, T Flip-Flop. The block diagram of
different flip-flops are shown here -
Procedure :
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design a 4 bit shift register (right shift), we need 4 MSD flipflop, 1
free running clock, 1 Bit switch (which will act as input to the left most
flipflop), 4 Bit display(to see the output of individual flipflops so that
the shifting can be seen with the clock input), wires.
3. The MSD flip flop component is in the sequential circuit drawer in the
pallet. The pin configuration is shown whenever the mouse is hovered
on any canned component of the palette or press the 'show pinconfig'
button. Pin numbering starts from 1 and from the bottom left
corner(indicating with the circle) and increases anticlockwise.
4. For MSD flip flop input is in pin-5, output(Q) is in pin-4, clock is in
pin-8
5. click on the MSD flip flop component in the pallet and then click on
the position of the editor window where you want to add the
component(no drag and drop, simple click will serve the purpose),
likewise add 4 MSD flipflops, 1 free running clock, 1 Bit switche and 4
bit Displays(from Display and Input drawer of the pallet,if it is not
seen scroll down in the drawer)
6. To connect any two components select the Connection menu of
Palette, and then click on the Source terminal and click on the target
terminal. connect all the components, connect the clock to the pin-8
of all the MSD flip flops, connect a bit switch to the pin-5(Q) of the left
most MSD flip flop, connect 4 bit displays to the pin-4 of 4 MSD flip
flops, connect the Q output of the previous flip flop to the D(pin-5)
input of the next flip flop.
7. To see the circuit working, click on the Selection tool in the pallet then
give input by double clicking on the bit switch, to the left most D flip
flop at pi-5(let it be 1), start the clock now check the output and see
how the 1 is shifting from left to right.

Observation:

Result: Hence we Design of Registers and Counters

 Experiment : 06
Aim: To Design Booth's Multipliers.
Apparatus: Virtual Lab.
Theory:
Booth's multiplication algorithm is an algorithm which multiplies 2 signed
integers in 2's complement. The algorithm is depicted in the following figure
with a brief description. This approach uses fewer additions and subtractions
than more straightforward algorithms.

The multiplicand and multiplier are placed in the m and Q registers respectively.
A 1 bit register is placed logically to the right of the LSB (least significant bit) Q0
of Q register. This is denoted by Q-1. A and Q-1 are initially set to 0. Control logic
checks the two bits Q0 and Q-1. If the two bits are the same (00 or 11) then all
of the bits of A, Q, Q-1 are shifted 1 bit to the right. If they are not the same and
if the combination is 10 then the multiplicand is subtracted from A and if the
combination is 01 then the multiplicand is added with A. In both the cases
results are stored in A, and after the addition or subtraction operation, A, Q, Q-1
are right shifted. The shifting is the arithmetic right shift operation where the
left most bit, namely, An-1 is not only shifted into An-2 but also remains in An-1.
This is to preserve the sign of the number in A and Q. The result of the
multiplication will appear in the A and Q.
Procedure:
1. Start the simulator as directed.This simulator supports 5-valued logic.

2. To perform the experiment on the given modules, we need the datapath

specified for booth's multiplication, a controller with a specified state chart, a
clock input, bit switch (to give input, which will toggle its value with a double
click), bit displays (for seeing output), wires.

3. Instantiating the controller: A control unit can be seen as a finite state machine,
so its behavior can be represented in a state table. The controller of the
simulator accepts the Moore type state chart and must contain an end state.
State names will automatically be generated in the form of S<sub<n< sub="">. In
the left pane of the simulator, click on the ASM chart button in the controller
subsection. Give the required informations in the appeared form as follows:

o Number of states: 7

o Number of inputs: 3

o Number of outputs: 5

The controller will generate 5 output control signals. After entering this information,
the second form will appear where you can set the names of the inputs and outputs.
Here inputs are the Q0, Q-1, count. Outputs control signals are load, add, sub, shift, dc.
The order of given input/outputs are maintained while creating terminals of the
controller. For example, the first output signal will appear in the leftmost output
terminal (lower terminals), second output will appear in the second left most bit and so
on. In case of input terminals, the leftmost bit is for clock input, so the first input
appears in the second terminal, and then the order is maintained. Then the third form
will appear where you actually specify the state chart i.e. state, outputs of that state and
transition conditions . The fields of the chart will be generated dynamically according
to previously given information on states, inputs and outputs.After entering the
following state chart, click on the controller component in the palette of the simulator
then click on the position of the design editor where you want to put the component
(no drag and drop, simple click will serve the purpose).
4. Instantiate the Booth's multiplier datapath from the sequential ckt drawer in the
palette (by clicking as mentioned previously).

5. The pin configuration of the component is shown whenever the mouse is

hovered on any canned component of the palette or pressing the show pin
configuration button on the toolbar will show it constantly in the left pane. Pin
numbering starts from 1 and from the bottom left corner(indicating with the
circle) and increases anticlockwise.

6. Pin configuration of the datapath module:

o M : Multiplicand (4 bit), Q : Multiplier (4 bit)

o Initialization : Inl:1, preset:1, set M, Q, start clock

o Starting multiplication: Inl:0, preset:0, start clock

o Result: FQ0 to FA3, at end state (here it is S6). These are the content of
A(4bit) and Q(4bit) register, total 8 bit (FQ0 is LSB, FA3 is MSB)

o I/P:

▪ Clk:32, Inl:31, preset:30

▪ Control pins: load:29, add:28, sub:27, shift:26, dc:25

▪ Multiplicand: M3 : 24, M2 : 23, M1 : 22, M0 : 21

▪ Multiplier: Q3 : 20, Q2 : 19, Q1 : 18, Q0 : 17

o O/P: FQ-1 is output of Q-1 bit register, similarly FQ0 to FQ3 are for Q
register and FA0 to FA3 are for A register.

▪ Datapath to controller input: Count, clkToController, FQ-1, FQ0

▪ Count : 16, clkToController : 15, FQ-1 : 14, FQ0 : 13

▪ FQ1 : 12, FQ2 : 11, FQ3 : 10

▪ FA0 : 9, FA1 : 8, FA2 : 7, FA3 : 6

7. To connect any two components select the Connection menu of Palette, and then
click on the Source terminal and click on the target terminal. According to the
following diagram connect all the components. Connect the controller outputs
to the specified control input terminals of the datapath, specified datapath
outputs to the inputs of the controller, the clock input, Bit switches with the
inputs and Bit displays component with the outputs (from Display and Input
 drawer of the pallet,if it is not seen scroll down in the drawer). After the
connection is over click the selection tool in the pallete.

8. At first initialize the multiplier by giving the specified inputs specified earlier, this
will load the multiplier and multiplicand, then start the multiplication operation
by giving the specified inputs specified earlier. At the end state (S6), the
multiplication result will be seen through ports FQ0 to FA3 (FQ0 is LSB, FA3 is
MSB). The current state of the controller is shown in the left pane as it transits
from one state to another. The controller can be reset by clicking the reset
controller button in the top toolbar, to start with a new input.

Observation:

Result: Hence we Design Booth's Multipliers.

 Experiment: 07
Aim: To Design of ALU.
Apparatus: Virtual Lab
Theory:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like
addition, subtraction,division, multiplication and logical oparations like and, or, xor,
nand, nor etc. A simple block diagram of a 4 bit ALU for operations and,or,xor and
Add is shown here :

The 4-bit ALU block is combined using 4 1-bit ALU block

Procedure:
1. Start the simulator as directed. This simulator supports 5-valued logic.
2. To design the circuit we need 4 1-bit ALU, 11 Bit switch (to give
input,which will toggle its value with a double click), 5 Bit displays (for
seeing output), wires.
3. The pin configuration of a component is shown whenever the mouse is
hovered on any canned component of the palette. Pin numbering
starts from 1 and from the bottom left corner (indicating with the
circle) and increases anticlockwise.
4. For 1-bit ALU input A0 is in pin-9,B0 is in pin-10, C0 is in pin-11 (this
is input carry), for selection of operation, S0 is in pin-12, S1 is in
pin-13, output F is in pin-8 and output carry is pin-7
5. Click on the 1-bit ALU component (in the Other Component drawer in
the pallet) and then click on the position of the editor window where
you want to add the component (no drag and drop, simple click will
serve the purpose), likewise add 3 more 1-bit ALU (from the Other
Component drawer in the pallet), 11 Bit switches and 5 Bit Displays
(from Display and Input drawer of the pallet,if it is not seen scroll
down in the drawer), 3 digital display and 1 bit Displays (from Display
and Input drawer of the pallet, if it is not seen scroll down in the
drawer)
6. To connect any two components select the Connection menu of
Palette, and then click on the Source terminal and click on the target
 terminal. According to the circuit diagram, connect all the
components. Connect the Bit switches with the inputs and Bit displays
components with the outputs. After the connection is over click the
selection tool in the pallete.
7. See the output, in the screenshot diagram we have given the value of
S1 S0=11 which will perform add operation and two number input as
A0 A1 A2 A3=0010 and B0 B1 B2 B3=0100 so get output F0 F1 F2
F3=0110 as sum and 0 as carry which is indeed an add operation.you
can also use many other combination of different values and check the
result. The operations are implemented using the truth table for 4 bit
ALU given in the theory.

Observation:

Result : Hence we Design of Memory

 Experiment: O8
Aim: To Study CPU Design
Apparatus: Virtual Lab
Theory:
At the top level a computer consists of a CPU (central processing unit), memory, I/O
components, with one or more modules of each type. These modules are
interconnected in a specific manner to achieve the basic functionality of a computer
i.e. executing programs. At the top level a computer system can be described as
follows:

● describing the external behavior of each component i.e the data and the
control signals that or exchanges with other components

● describing the interconnection structure and the controls required

We are considering the Von Neumann architecture. Some of the basic features of
this architecture are as follows:

● data and instructions are stored in a single read-write memory

● the contents of the memory are addressable by location

● execution occurs in a sequential manner (unless explicitly specified) from

one instruction to the next

Top level components and interactions among them:

● CPU exchanges data with memory. For this CPU uses two internal resistors.
Following is a block diagram of a basic computer system:

o Memory address register (MAR) which specifies the address for the
next read or write
 o Memory buffer register (MBR) which contains the data to be written
into memory or receives the data read from memory

o I/O buffer (I/O BR) register is used for the exchange of data between
an I/O module and the CPU

● A memory module consists of a set of locations defined by sequentially

numbered addresses. Each location contains a binary number that can be
interpreted as either an instruction or data.

● An I/O module transfers data from external devices to CPU and memory and
vise versa

● The basic function of a computer is to execute a program which consists of a

set of instructions stored in the memory. Processing required for a single
instruction is called an instruction cycle which consists of instruction fetch
and instruction execution. A register called program counter (PC) holds the
address of the next instruction. Unless told otherwise the processor always
increments PC after each instruction fetch so that the next instruction is
fetched in sequence. The fetched instruction is fetched into a register called
instruction register (IR).

The basic instruction cycle is shown in the following figure:

● After fetching an instruction, processor execute the instruction by doing

some processing on the data which may involve arithmetic and logic unit
(ALU), specified by the instruction, then the processor writes back the result
(if any) to the memory.

This experiment provides a single instruction CPU with a built-in controller. A

working memory has been provided to check the working principle of the CPU. The
single instruction which this CPU supports is SBN (subtract and branch if negative).
The format of this instruction is:

● SBN a,b,c Mem[a] = Mem[a] - Mem[b] if(Mem[a] < 0) goto c

● a, b, c are 4 bit addresses

● Mem[a] denotes the contents of memory address a

 In this experiment, no I/O module has been included for the purpose of simplicity.
The working memory should contain the program and data in binary format. The
CPU executes the program. For halting, it uses a self loop, no other halt instruction
is provided.

Procedure:
1.
2. Start the simulator as directed.This simulator supports 5-valued logic.
3. To perform the experiment on the given modules, we need the CPU,
the working memory with a program and data loaded, a clock input,
Bit switch(to give input,which will toggle its value with a double click),
Bit displays(for seeing output), wires.
4. Load memory: click on the load memory button in the left pane. you
can either load the memory by filling the form or you can directly load
the program form a text file. The memory provides 4-bit address
space and 12 bit data word, thus providing 16 memory addresses
starting from 0000 to 1111. For loading from file, the file should
contain only binary values, it must contain 16 lines, each line
containing the content to be stored in the corresponding memory
address. For example, the content of the first line will be loaded to the
0000 address of the memory, similarly, the second line will
correspond to the 0001 address and so on, finally the content of the
last line will be fed to the 1111 address. The program should use self
loop for halting, for example, the instruction stored at address 1010
will cause self loop execution, if it content of a has -1 in binary format
(in 2's complement), the content of b has 0 and c is 1010, then once
the execution reaches to this 1010 address, it will finally point to
itself.
5. Instantiating the memory: after loading the memory, click on the
memory component from the computer design drawer in the palette of
the simulator then click on the position of the design editor where you
want to put the component(no drag and drop, simple click will serve
the purpose).
6. The pin configuration of the component is shown whenever the mouse
is hovered on any canned component of the palette or pressing
the show pin configuration button on the toolbar will show it
constantly in the left pane. Pin numbering starts from 1 and from the
bottom left corner(indicating with the circle) and increases
anticlockwise.
7. Pin configuration of the memory module:
o Input pins (upper terminals): memory enable : 30, R/W' : 29,
address : 25-28, data : 13-24 (13 is LSB)
o Output pins(lower terminals): data output : 1-12 (1 is MSB)
8. Instantiate the CPU from the computer design drawer in the palette of
the simulator then click on the position of the design editor where you
want to put the component.
9. Pin configuration of the CPU:
 o Input pins (upper terminals): data input : 20-31 (20 is MSB)
,clock input : 19
o Output pins(lower terminals): memory enable : 1, R/W' : 2,
address : 3-6( 3 is MSB), data output : 7-18 (7 is MSB)
10. To connect any two components select the Connection menu of
Palette, and then click on the Source terminal and click on the target
terminal. According to the following diagram connect all the
components. Connect the memory outputs to the input terminals of
the CPU, specified datapath outputs to the inputs of the controller, the
clock input, Bit switches with the inputs and Bit displays component
with the outputs (from Display and Input drawer of the pallet,if it is
not seen scroll down in the drawer). After the connection is over click
the selection tool in the pallete.
11. Start clock and observe the behavior of the CPU.See the content of
memory by clicking show memory button in the left pane. Observe
how the program is executing sequentially and modify the data
content as per the program.

Observation:

Result: Hence we Study CPU Design