ACTS, Pune

Suggested Teaching Guidelines for

Verification using UVM PG-DVLSI September 2022
Duration: 30 class room hours + 58 Lab hours
Objective: To introduce Verification Concepts and implementing them using UVM.
Prerequisites: Knowledge of System Verilog concepts, C programming, OOP concepts.
List of Books / Other training material

Evaluation method: Theory exam– 40% weightage

Lab exam – 40% weightage
Internal exam – 20% weightage

Courseware:

No specific courseware for modules, faculty may share some course materials.

Reference:
1. Universal Verification Methodology (UVM) 1.2 User’s Guide
2. Universal Verification Methodology (UVM) 1.2 Class Reference

Session 1
Lecture: Introduction to Verification Methodologies
• Need of Verification Methodologies
• Comparative study of Verification Methodologies
o Verification Methodology Manual (VMM)
o Open Verification Methodology (OVM)
o Universal Verification Methodology (UVM)

Session 2
Lecture: Overview of UVM
• Introduction to Universal Verification Methodology (UVM)
• Coverage-Driven Verification (CDV)
• UVM testbenches and environments
• Verification components:
o Data Item (Transaction)
o Driver (BFM)
o Sequencer
o Monitor
o Agent
o Environment
• UVM Class library
o UVM object class
• UVM factory

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 ACTS, Pune
Suggested Teaching Guidelines for
Verification using UVM PG-DVLSI September 2022
Session 3 & 4
Lecture: Transaction Level Modeling (TLM)
• Basics of TLM
• TLM Overview, TLM, TLM-1, TLM 2.0
• UVM reporting & transaction
• Basic TLM communication
• Communicating between processes
• Blocking versus Nonblocking
• Connecting Transaction-Level Components
• Peer-to-Peer connections
• Port/Export Compatibility

Session 5
Lecture: TLM-1
• Encapsulation and Hierarchy
o Hierarchical Connections
o Connection Types
• Analysis Communication
o Analysis Ports
o Analysis Exports

Session 6
Lecture: Introduction to TLM 2.0 Theory Concepts
• Generic Payload
o Attributes
o Accessors
o Extensions
• Core Interfaces and Ports
• Blocking Transport
• Nonblocking Transport
• Sockets
• Time
• Use Models

Session 7 & 8
Lecture: Developing Reusable Verification Components – I
o Modeling Data Items for Generation
• Transaction-Level Components
• Creating the Driver
• Creating the Sequencer
• Connecting the Driver and Sequencer
• Creating the Monitor
• Instantiating Components
• Creating the Agent
• Creating the Environment
• UVM Configuration Mechanism

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 ACTS, Pune
Suggested Teaching Guidelines for
Verification using UVM PG-DVLSI September 2022

Session 9 & 10
Lecture: Developing Reusable Verification Components – II
• Enabling Scenario Creation
o Declaring User-Defined Sequences
o Generating Stimulus with Sequences and Sequence Items
o Configuring the Sequencer’s Default Sequence
o Overriding Sequence Items and Sequences
• Managing End of Test
• Implementing Checks and Coverage
• Implementing Checks and Coverage in Classes
• Implementing Checks and Coverage in Interfaces
• Controlling Checks and Coverage

Session 11 & 12
Lecture: Using Verification Components
• Using a Verification Component
• Testbench Class
• Instantiating Verification Components
• Test Class
• Verification Component Configuration
• Creating and Selecting a User-Defined Test
• Creating Meaningful Tests
• Virtual Sequences
• Checking for DUT Correctness
• Scoreboards
• Implementing a Coverage Model

Session 13
Lecture: Introduction to Register Layer Classes Theory Concepts
• Overview
• Usage Model
• Access API
• Coverage Models
• Constructing a Register Model
• Back-door Access
• Special Registers
• Integrating a Register Model (RM)
• Randomizing Field Values
• Pre-defined Sequences
Session 14
Lecture: Advanced UVM Concepts
• The uvm_component Base Class
• The Built-In Factory and Overrides

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 ACTS, Pune
Suggested Teaching Guidelines for
Verification using UVM PG-DVLSI September 2022
• Callbacks
• The Sequence Library
• Advanced Sequence Control
• Command Line Interface (CLI)

Session 15
Lecture: Case studies of UVM Environment
• Device Under Test (DUT) and its connection with environment, Scoreboards,
coverage, predictors, monitors
• Verification of Traffic Light Controller / ATM Design / AHB Peripheral using UVM

Assignments:
• More lab practice as well as assignments should be taken of the following topics:
o config_db
o sequential circuits in UVM
o scoreboard for FSM logic
o verification for memory designs
o multiple agent
o environmental hierarchy
o hands on examples of environment creation for combinational as well as
sequential circuits
• Write code to create a proper UVM environment class which contains the following
phases.
o virtual function void build();
o virtual function void connect();
o virtual function void end_of_elaboration();
o virtual function void start_of_simulation();
o virtual task run();
o virtual function void extract();
o virtual function void check();
o virtual function void report();
• Create an environment with primary reporting methods in UVM.Note that,In the top
module, 3 objects of reporting must be created and different verbosity levels should
be set.
• Write programs for the following requirements using field automation macros.
o Define the enumerated types for packet types
o Method to calculate the fcs
o Test to check the packet implementation
• Create a UVM with classes that represent complete UVM sequence generation.
• Write a program to create a link between generated UVM sequence and driver.
• uvm_test is derived from uvm_component class and there is no extra functionality is
added. select the testcase by passing the testcase name as string to
uvm_root::run_test(<testcase_string>) method. Implement the environment with
following topology

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 ACTS, Pune
Suggested Teaching Guidelines for
Verification using UVM PG-DVLSI September 2022

o Extend uvm_env class and define user environment.

o Utility macro should be declared.
o Declare the objects for agents.
o Define the constructor.
o Define build method.
o Define the phases
o Test case should be implemented.

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