Von Neumann and Harvard Architecture
Von Neumann and Harvard Architecture
Von Neumann and Harvard Architecture
Architecture
Buses (Signal One common signal path (bus) It uses separate buses for the
Paths) helps in the transfer of both transfer of both data and
instruction and data. instructions.
Number of It requires two clock cycles for It executes any instruction using
Cycles executing a single instruction. only one single cycle.
Access to CPU The CPU is not able to The CPU can easily read/write
read/write data and access data as well as access the
instructions at the same time. instructions at any given time.
Uses This method comes to play in This architecture is best for signal
the case of small computers and processing as well as
personal computers. microcontrollers.
Usage of Space This architecture does not waste This type of architecture can result
any space. It is because the in space wastage. It is because the
instruction memory can utilize instruction memory cannot utilize
the left space of the data the leftover space in the data
memory. It can also happen memory. It also cannot happen
vice-versa. vice-versa.
The idea was introduced in the late 1940s by John von Neumann who
proposed that a program be electronically stored in the binary-number
format in a memory device so that instructions could be modified by
the computer as determined by intermediate computational results.
Von-Neumann Model
The major components of CPU are Arithmetic and Logic Unit (ALU),
Control Unit (CU) and a variety of registers.
Arithmetic and Logic Unit (ALU)
The Arithmetic and Logic Unit (ALU) performs the required micro-
operations for executing the instructions. In simple words, ALU
allows arithmetic (add, subtract, etc.) and logic (AND, OR, NOT,
etc.) operations to be carried out.
Control Unit
Registers
Registers Description
MAR (Memory Address This register holds the memory location of the data
Register) that needs to be accessed.
MDR (Memory Data This register holds the data that is being transferred
Register) to or from memory.
CIR (Current Instruction This register contains the current instruction during
Register) processing.
Buses
Buses are the means by which information is shared between the
registers in a multiple-register configuration system.
A bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at a
time. Control signals determine which register is selected by the bus
during each particular register transfer.
Bus Description
Address Address Bus carries the address of data (but not the data) between
Bus the processor and the memory.
Data Bus carries data between the processor, the memory unit and
Data Bus
the input/output devices.
Control
Control Bus carries signals/commands from the CPU.
Bus
Memory Unit
A memory unit is a collection of storage cells together with associated
circuits needed to transfer information in and out of the storage. The
memory stores binary information in groups of bits called words. The
internal structure of a memory unit is specified by the number of
words it contains and the number of bits in each word.
Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.
Advantages
Disadvantages
In this mode, the instruction specifies the register whose contents give us the address of
operand which is in memory. Thus, the register contains the address of operand rather than
the operand itself.
Auto Increment/Decrement Mode
In this the register is incremented or decremented after or before its value is used.
In this, the address field of instruction gives the address where the effective address is stored
in memory. This slows down the execution, as this includes multiple memory lookups to find
the operand.
In this the contents of the indexed register is added to the Address part of the instruction, to
obtain the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and
R(that holds the displacement), or vice versa.
Relative Addressing Mode
In this the contents of PC(Program Counter) is added to address part of instruction to obtain
the effective address.
The operand is A cells away from the current cell(the one pointed to by PC)
In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP
top two items from the stack, add them, and will then PUSH the result to the top of the stack.
Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the basic operational
process of a computer. This process is repeated continuously by CPU from boot up to shut
down of computer.
The instruction is fetched from memory address that is stored in PC(Program Counter) and
stored in the instruction register IR. At the end of the fetch operation, PC is incremented by 1
and it then points to the next instruction to be executed.
If the instruction has an indirect address, the effective address is read from the memory.
Otherwise operands are directly read in case of immediate operand instruction.
The Control Unit passes the information in the form of control signals to the functional unit
of CPU. The result generated is stored in main memory or sent to an output device.
The cycle is then repeated by fetching the next instruction. Thus in this way the instruction
cycle is repeated continuously.
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