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    Department of Electrical Engineering Indian Institute of Technology, Kanpur EE 210 Home Assignment #9 Assigned: 25/2/20

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    Adarsh Banth
    The document contains 8 questions regarding circuit analysis of BJT and MOSFET amplifier stages. Question 1 asks to derive expressions for voltage gain and output resistance of a CS amplifier stage. Question 2 involves determining input resistance, voltage gain, and output resistance of a CB amplifier stage. Question 3 relates to the output resistance of a CB stage excited by an ideal current source.

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    Department of Electrical Engineering Indian Institute of Technology, Kanpur EE 210 Home Assignment #9 Assigned: 25/2/20

    Uploaded by

    Adarsh Banth
    17 views2 pages
    The document contains 8 questions regarding circuit analysis of BJT and MOSFET amplifier stages. Question 1 asks to derive expressions for voltage gain and output resistance of a CS amplifier stage. Question 2 involves determining input resistance, voltage gain, and output resistance of a CB amplifier stage. Question 3 relates to the output resistance of a CB stage excited by an ideal current source.

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    The document contains 8 questions regarding circuit analysis of BJT and MOSFET amplifier stages. Question 1 asks to derive expressions for voltage gain and output resistance of a CS amplifier stage. Question 2 involves determining input resistance, voltage gain, and output resistance of a CB amplifier stage. Question 3 relates to the output resistance of a CB stage excited by an ideal current source.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    17 views2 pages

    Department of Electrical Engineering Indian Institute of Technology, Kanpur EE 210 Home Assignment #9 Assigned: 25/2/20

    Uploaded by

    Adarsh Banth
    The document contains 8 questions regarding circuit analysis of BJT and MOSFET amplifier stages. Question 1 asks to derive expressions for voltage gain and output resistance of a CS amplifier stage. Question 2 involves determining input resistance, voltage gain, and output resistance of a CB amplifier stage. Question 3 relates to the output resistance of a CB stage excited by an ideal current source.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    Department of Electrical Engineering

    Indian Institute of Technology, Kanpur

    EE 210 Home Assignment #9 Assigned: 25/2/20

    1. Show that for a CS(D) stage, the expressions for the voltage gain Av and the output resistance
    R0 are given by Av = gmRD/[1 + (gm + gmb)RS + (RS + RD)/r0], and R0 = RS + r0[1 + (gm +
    gmb)RS] respectively. Note that the expression for the output resistance is identical to that of a
    CG stage biased by a non-ideal current source, having a source resistance RS. Also, if RS →
     (i.e., the current source tends to become ideal), then R0 →  , as expected.

    2. In a CB circuit, assume IC = 260 A,  = 100, and RC = 10 k. Determine the input
    resistance, voltage gain, and output resistance. Neglect r0. Now, assume that the transistor has
    a base resistance rb of 101 . How will it affect the input resistance and voltage gain?

    3. Show that if a CB circuit is excited by an ideal current source, then the output resistance R 0 ,
    looking into the collector of the transistor, is given by R 0 = r0.

    4. Show that for a CG stage, if the output resistance r0 cannot be neglected, but the body effect
    can be neglected, then the input resistance (Ri) is given by (r0 + RD)/(1 + gmr0), where RD is
    the drain (i.e., load) resistance, and gm is the transconductance of the MOSFET. Hence, show
    that the expression for the ac small-signal midband voltage gain (Av) can be given by (1 +
    gmr0)RD/(r0 + RD). Note that in the limit of very large r0, Ri and Av simplify to 1/gm and gmRD
    respectively, as expected.

    5. The transistor (Q) used in the circuit shown in Fig.1 has  = 200. Assume the capacitors C1-
    C3 to have very large values, so that they can be treated as short circuits in midband. Neglect
    r0 of the transistor.
    a) Choose RB to give IC = 1 mA, and choose RC to give maximum undistorted peak-to-peak
    output voltage swing.
    b) Compute the ac small-signal midband transresistance (v0/is) of the circuit.

    6. The BJT (Q) in the circuit shown in Fig.2 has  = 100. Assume the capacitors C1 and C2 to
    have very large values, so that they can be treated as short circuits in midband. Neglect r0 of
    the transistor.
    a) Determine the dc collector current and the collector-to-emitter voltage.
    b) Calculate the input resistance Ri, the output resistance R0, and the voltage gain v0/vi.

    7. In the circuit shown in Fig.3, called a boot-strapped follower, assume the capacitors C1 and
    C2 to have very large values, so that they can be treated as short circuits in midband. Neglect
    r0 of the transistor.
    a) Calculate the dc collector current, assuming  = 100.
    b) Calculate the input resistance Ri and the voltage gain v0/vs.
    c) Repeat b) for the case when capacitor C2 is open-circuited. Compare the results with
    those obtained in b) to find the advantages of bootstrapping.

    8. The amplifier shown in Fig.4 consists of two identical CE amplifiers connected in cascade.
    Assume the capacitors C1-C5 to have very large values, so that they can be treated as short
    circuits in midband. Neglect r0 of the transistors.
    a) For VCC = 15 V, R1 = R3 = 100 k, R2 = R4 = 47 k, RE1 = RE2 = 3.9 k, RC1 = RC2 =
    6.8 k, and  = 100, determine the dc collector current and the collector-to-emitter
    voltage of each transistor. Neglect base currents for dc analysis.
    b) Now, perform an ac small-signal midband analysis of the stage, and determine the
    following:
    i) Ri1 and vb1/vs for RS = 5 k.
    ii) Ri2 and vb2/vb1.
    iii) v0/vb2 for RL = 2 k.
    iv) the overall voltage gain v0/vs.

    12 V VCC

    1 mA
    C2
    RC v0
    RB v0
    C1
    100 k 10 k
    C3
    Q 10 k
    vi Q
    R0
    C1
    is 10 k
    1 k C2 175 
    Ri

    Fig.2
    Fig.1

    9V
    Source Stage I Stage II Load
    C1
    vs 10 k VCC
    Q
    9V RC1 RC2
    C5
    R1 vb2 R3 v0
    10 k
    20 k
    C1 C3
    v0 vs RS
    Q1 Q2 RL
    Ri vb1
    C2
    20 k 2 k
    R2 R4
    RE1 C2 RE2 C4

    Fig.3
    Ri1
    Ri2
    Fig.4

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