IP Core

eUSB 3.1 Gen 2 Device - Software Enumeration, FIFO Interface

Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel® FPGA built-in 10 Gbps transceiver. It is
a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS)
and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It
provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.
It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the control
transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
Architecture Implementation Results
Supported Family Resource Utilization Memory Bits Memory Blocks
USB Tx D+
EP1
EP1 USB2.0 ULPI USB
USB2.0 ULPI USB 2.0
2.0 ULPI
ULPI
Data Protocol
Protocol Layer
Layer Manager
Manager PHY
PHY D- Cyclone 10 (up to Gen ~17902 ALM ~441136 ~74 M20K
EP2
EP2
2 10Gbps interface)
FIFO
FIFO
Interface
Interface USB3.1
USB3.1 Gen
Gen 22 SS_RX+ Arria 10 (up to Gen 2 ~16948 ALM ~441136 ~74 M20K
Protocol
Protocol Layer
USB Rx
Layer Intel
Intel SS_RX- 10Gbps interface)
EP30 Transceiver
Transceiver
Data EP30 PHY
PHYIP IPCore
Core SS_TX+
Link
Link Cyclone V (up to Gen 1 ~6210 ALM ~412720 ~71 M10K
Layer
EP0
Layer SS_TX- 5Gbps interface)
EP0
Arria V (up to Gen 1 ~6190 ALM ~413248 ~74 M10K
5Gbps interface)
Avalon
Avalon To
To
FIFO
FIFO
Bridge
Bridge
Note:
1. Results are based on 1-Bulk IN and 1-Bulk OUT endpoint with 16K buffer each.
SLS

Avalon
Bus
DMA
DMA
Intel
Deliverable
External
Contents Eval Full
Avalon
OpenCore Plus Evaluation:
Bus
One (1) month evaluation license at free of cost v
Performance Results Full Version:
Project based perpetual License with one (1) year post- v
sales support. Other licensing schemes are also available.
Time-limited (4 hours) SOF generation support v
Full programming files generation support v
Encrypted IP Core design files with Control, 1-Bulk IN and
1-Bulk OUT endpoints v v
Qsys based Reference design for Intel® Arria® 10
Development Board and SLS FMC eUSB 3.1 Snap On v v
Board
Demonstrations:
1) Enumeration Demo
2) Mass Storage Demo v v
Check out Video at https://youtu.be/q9ZYtW3KEWQ 3) UVC Demo
4) Loopback Test Demo
Features
Nios II Sample Applications (with C code)
 USB 3.1 Specific Features 1) Enumeration v v
 Supports SuperSpeedPlus (SSP - USB 3.1 Gen 2) and Documentation:
SuperSpeed (SS - USB3.1 Gen 1) mode 1) IP Core User Guide v v
 Uses Intel Transceiver as a PHY layer and thus eliminates need 2) Windows API User Guide
for external PHY for USB 3.1 Windows Reference Driver (Object Code) v v
 USB 2.0 Specific Features
Software Library
 Supports High Speed (HS) and Full Speed (FS) modes 1) VC++ v v
 Provides ULPI interface to interact with external USB 2.0 PHY
 Ease of Use Application
 Ready to use component for Intel’s Qsys  Imaging Device  Machine Vision
 Simple FIFO interface to transfer data over non-control  Storage Device  Data Centers
endpoint
Licensing
 Flexibility
 Capable to support up to 31 endpoints (1 default control  OpenCore Plus Evaluation: 1 month evaluation license at no cost
endpoint, 15 IN endpoints and 15 OUT endpoints)  Full: Project based Perpetual License
 Allows to select number of buffers per endpoint based on the  Maintenance: 20% of License fee from next year to continue
technical support and getting updates for IP Core
requirement
Support
 IP integration support is available with the purchase of full version
 IP Core modification and customization support available at
additional cost

Contact [email protected] for more information and [email protected] for placing an order.
System Level Solutions
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Tel : 91-2692-232 501 / 502 / 001-408-852-0067 / 001-408-705-2339
• E-mail: [email protected] • Website: www.slscorp.com

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