Power consumption in CMOS

 There are basically

two types of power
consumption in
CMOS

1) Dynamic Power
2) Static Power
(Leakage power)

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 Dynamic Power

 Dynamic power is power consumed by the cell

whenever output changes its value (0 to 1 or 1 to
0)
 Consists of two main parts
• Switching power(Pswiching)
• Internal power(PInternal )

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 Switching power

 Switching power results from the

charging and discharging of the
external capacitive load on the output
of the cell

VDD

D
CL
G

GND

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 Internal power

 Power consumed during short period when

input signal is transitioning, during which
both the PMOS and NMOS transistors can
be conducting
 Large current called “crowbar” or “short
circuit” current flows from VDD to VSS

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 Static Power (Leakage power)

 The leakage power is consumed by the circuit when the output is at stable
state
 Main components:
• Gate leakage current
The current that flows directly from the gate through the oxide to the
substrate due to gate oxide tunneling and hot carrier injection
• Sub threshold leakage current
The current that flows from drain to source of a transistor operating in the
weak inversion region
• Reverse bias PN junction leakage current
The current that results due to minority carrier drift and generation of
electron/hole pair in the depletion regions

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 Leakage current components

 Leakage current comprises of the following

components

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 Why Low power ?

 Increasing cell count ---> Increasing power

 Higher frequencies ---> Increasing power
 Smaller geometries ---> Increasing leakage
power

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 Power reduction techniques

 The power has two main components

• Dynamic power
• Static power (Leakage power)

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 Dynamic power reduction techniques

 Dynamic power is mainly a function of the

supply voltage, output load (Cload) , Frequency
and switching activity of a cell
 Reducing any of the above component will
result in the reduction of the dynamic power
 There are several techniques employed in
ASIC as following

1) Clock gating
2) Multiple voltage design
3) Dynamic voltage and frequency scaling
(DVFS)
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 Clock Gating

 Clock gating is used to reduce the

switching activity of the clocks at
selected FF's input and thereby • Design after clock gating
reducing the dynamic power
 Clock gating inserts Q
combinational logic on clock path Input D
to conditionally stop the clock at
FF’s inputs Enable
CK
 This technique reduces the clock
dynamic power consumption

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 Multiple Voltage Design


Reducing the supply voltage reduces the power consumption
exponentially

Selectively providing different voltages to different blocks depending on
their performance requirement reduces the power

Reducing voltage also increases delay

Apply higher voltages to the timing critical blocks

Apply lower voltages to the non timing critical blocks

Create voltage islands in the chip area

Needs level shifters at the interfaces of the voltage islands

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 Multiple Voltage Design

 Level shifters are needed at the

block interface to convert the
voltage levels for the receiving
blocks
 Needed to make sure the valid
voltage levels for receiving blocks
 For signals going from low voltage LOW TO HIGH
block to high voltage block a low to LEVEL SHIFTER

high level shifter is needed and it

should be placed in high voltage LOW HIGH
block VOLTAGE VOLTAGE
 For signals going from high voltage BLOCK BLOCK
block to low voltage block a high to HIGH TO LOW

level shifter is needed and it should LEVEL SHIFTER

be in low voltage block

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 Multi-Voltage design Example

 CPU And RAM operating on

Higher frequency
 Hence operated at Higher VDD1 = 1.8V VDD2= 1.2V
voltages
CPU
 Peripherals operating on
Higher
lower frequency voltage
 Hence operated at lower Voltage Peripherals
 Level shifters are inserted in RAM Lower voltage
respective domains at block Higher
voltage
interfaces

GND=0V

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 Dynamic voltage and frequency scaling.


Dynamically changing the voltage and the
frequency of the chip depending on the work
load

Reduces dynamic power significantly

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 Static (Leakage) power reduction techniques

 Multi Vt
 Power gating

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 Multi-Vt


Requires libraries having multiple Vt cells

High Vt cells: More delay, Less leakage

Low Vt cells : Less Delay, More leakage

Use Low Vt cells in the timing critical paths
to achieve timing

Use High-Vt cells in the timing non-critical
paths to reduce leakage power

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 Multi-Vt


Two approaches

Timing critical design
• Insert all the low Vt cells to achieve timing
• Selectively replace low Vt cells by High-Vt cells in non critical paths to
reduce the leakage

Power critical design
• Insert all the high Vt cells to reduce the leakage power
• Selectively replace high Vt cells by low-Vt cells in timing critical paths to
reduce the leakage

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 Power Gating


Portion of the chip (Certain blocks ) are shut down during the period of
inactivity of those blocks

Reduces leakage power of the inactive blocks during powered off state

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 Power gating -Requirements

 Power controller circuits to

decide power on/off sequence of
the power gated block
 Power switching network that VDD VDD
provides power to the gated
blocks
 SLEEPN
Power switches are the POWER
transistors that connect the SVDD GATED
always on power structure to the BLOCK
power pins of the cells in the POWER
power gated blocks GATED SVSS
 Power switches, when switched BLOCK
on provides power to the gated SLEEP
block and when switched off it
disconnects power supply from VSS
the gated block VSS
 High Vt cells are used as power GATED GATED VSS
switches VDD

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 Power gating -Requirements

 Isolation cells : Needed for signal isolation

between power gated blocks and always
on blocks
 Needed for the output signals of the power
gated blocks
 Provides a known constant voltage
(0/1/last logic value before power down
the block) to the always on block input,
when the power gated domain is switched
off
 The isolation cell prevents any unknown Power Always
logic values to reach to the input of the Gated On
always on block Block Block
Isolation
 The output of the gated block does not Cell
decay immediately and it floats near the Power_U
threshold level, the isolation cell helps p
reducing the crowbar current at the input
of the always on block by providing
constant voltage level

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 Power gating -Requirements

 Retention registers
• Often desirable to save the logic values of the
power gated blocks when it is powered off
• Retention register stores the logic values when
the gated block is powered off D Q
• Contains one shadow registers in addition to the Main
normal flip flop, powered by always on power Register
supply, which stores the logic values when the
gated block is switched off save restore
• Restores the stored logic when the gated block is
again powered on Shadow
• When SAVE is asserted before power down, the Register
content of the main register is stored in the
shadow register CLK
• When RESTORE is asserted after power up, the
content of the shadow register is restored back in SAVE RESTORE
the main register

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 Power Management Kit

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 Special cells for low power techniques

The following special cells are used for various low

power techniques
• Level Shifters
• Power gating cells (Headers/Footers)
• Isolation cells
• Retention registers

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 Level Shifters

Level Shifter : Cell (typically buffers) that translates inputs with one voltage
swing to an output with a different voltage swing

• In a multi voltage design, there are multiple voltage islands. In such case when
signal crosses the boundary from one domain to other domain and logic level
switching voltages are not the same, level shifter cells must be inserted to convert
the signal voltage to the correct voltage at the receiving domain

• Types of level shifters

1) High to Low level shifter - Down shifting
2) Low to High level shifter - Up shifting

OUTL

vss
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High to low level shifter Low to High level shifter
 High to Low Level Shifters

1) High to Low level shifter - Down

shifting
When the signal is entering to low voltage domain from the high
OUTL
voltage domain, we need to down shift the signal, high voltage level to
low voltage level. So at that time we need high to low level shifters
• If we do not use high to low level shifters then there are no latchup or vss
break down problem but it may cause rise time and fall time faster
• However for safe timing closure we need some specially identified
“downshift” cells – High to low level shifters
• In the case of down shifting, the level shifter cell can be just a simple
inverter or buffer. As shown in figure, high to low level shifter can be
quite simple, essentially two inverters in series
• As shown in the drawing, a high-to-low level shifter only introduces a
buffer delay, so its impact on timing is small
• High to low level shifters are very simple compared to low to high level
shifters. It requires single supply voltage

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 Low to High Level Shifters

2) Low to High level shifter - Up

shifting
When the signal is entering to high voltage domain
from the low voltage domain, we need to up shift
the signal. So at that time we need low to high level shifters

• In the case of shifting up, it is necessary to design a special level

shifter circuit, because a low voltage swing input signal would not
necessarily be strong enough to turn the input transistor fully on.
This could lead to an unacceptably long rise time or fall time. It
causes higher switching current and reduce the noise margin

• A slow transition time means that the signal spends more time
near VT, causing the short circuit (crowbar) current to last longer
than necessary

• Specially designed level shifter cells solve this problem. They

provide fast signals to the higher voltage domain
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 Low to High Level Shifters

• There are number of design techniques. But a

simple one is shown in the figure

• This design takes buffered and inverted form of

the lower voltage signal and use this to drive a
cross-coupled transistor structure running at the
higher voltage

• Such level shifters requires two supply and

typically share a comman ground

• Low to high level shifters introduce a significant

delay compared to a simple buffer dealy of high
to low level shifters because of its complex
design structure

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 Placement of the level shifters

• Level shifters should be placed in the destination domain for up shifting as well as
down shifting
• As we need low voltage supply for high to low level shifter we should place such
level shifters in the low voltage domain. However we can place them in the high
voltage domain also, but then power routing for such cells become a critical task.
• For low to high level shifters, output driver has higher supply current requirement.
Thus we need to apply high voltage for output driver. So, we should place low to
high level shifters in to high voltage domain.
• Following figures explains the placement of level shifters.

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 Level Shifter Recommendations and Pitfalls
Recommendations:
• Place the level shifters in the receiving domain – in the lower domain for High-
to-Low level shifters, in the higher domain for High-to-Low level shifters

Pitfalls:
• Interfaces between domains that may both be higher or lower voltage with
respect to each other will require specialized level shifter components and make
the setup and hold timing verification across such interfaces very complex

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 Problems without Level Shifters

Problem without High to low level shifters:

• If we do not use high to low level shifters then it may cause rise time and fall
time faster for the receiving domain and that can cause hold violations
• So, for safe timing closure we need to insert high to low level shifters when
signal interacts between high voltage domain to low voltage domain

Problem without low to high level shifter:

• If the difference between low voltage and high voltage is more then 25% then a
signal from low voltage domain to high voltage domain can turn on both
transistors PMOS as well as NMOS in the receiving cell and cause the crowbar
current that increases the power consumption
• If a signal from low voltage domain is driving a cell in high voltage domain, it
may result in significant rise or fall time degradation. This may cause the setup
violations in the receiving domain
• So, to prevent power consumption due to crowbar current and setup time
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violations, we need to insert proper level shifters
 Power Gating Cells

Power gating:
• Power gating is the technique to reduce leakage
power consumption. In this technique we are using
sleep transistor
• A sleep transistor is either PMOS or NMOS high VT
transistor and is used as a switch to shut off the power
supplies to parts of a design in standby mode
• The PMOS sleep transistor is used to switch VDD
supply and hence is called as a “Header Switch”
• The NMOS sleep transistor controls VSS supply and
hence is called as a “Footer switch”
• Figure shows schematic of header and footer switch.
In footers VSS is switched ground and VSSG is always
on ground. While in headers VDD is switched power
and VDDG is always on power

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 Isolation Cells

Isolation: Isolation is a technique for controlling the behaviour of a signal

that is driven by a powered down domain. Isolation technique driving a
signal to a known state - 1, 0, or latching it to a previous value when the
power domain is powered down

• Isolation cells are basically used to isolate the output signals of the power
gated block from the always on block Isolation ensures that there are no
floating inputs to the active power domain, which could result in crowbar
current

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 Why Isolation cells required?

Why isolation is required in the power gating?

• With a header style switch fabric, the internal nodes and outputs of the power gated block
collapse down towards to ground rail when the switch is turned off
• With a footer style switch fabric, the internal nodes and outputs of the power gated block
charges towards to supply rail when the switch is turned off
• But there is no guarantee that the power gated nodes will ever fully discharge to ground or
fully charged to the supply
• So, the challenge for power gating designs is that the outputs of the power gated block may
ramp off very slowly. The result could be that these outputs spend a significant amount of
time at threshold voltage, causing large crowbar currents in the always powered on block
• To prevent these crowbar currents, isolation cells are placed between the outputs of the
power gated block and the inputs of the always on block
To Solve this problem we have three types of isolation
techniques:
1) clamp the signal to “0”
2) clamp the signal to “1”
3) clamp the signal to the last value
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 Signal Isolation Techniques

Clamp the signal to “0” :

• For an output that requires clamping the signal to “0”, we can use a NAND gate and
an inverter, as shown in Figure, for signal isolation. This design uses an active-low
isolation control signal which forces the output low even if the other input floats.
The circuit diagram shows why the circuit is immune to a floating signal on IN. As
long as ISOLN is low, the bottom transistor is off, no current can flow through the
gate, and the input to the inverter is pulled up.

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 Signal Isolation Techniques

Clamp the signal to “1” :

• For an input that requires holding a logic “1” when the source power domain is
powered down, we can use a NOR gate, as shown in the figure, for the signal
isolation. This is shown with an active-high isolation control signal which forces the
output high even if the other input floats. The circuit diagram shows why the circuit
is immune to a floating signal on IN.

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 Signal Isolation Techniques

Clamp the signal to the last value:

• The retention latch is controlled by a pulse signal RET which is asserted just before
the logic cell goes into sleep to save the current output state into the retention latch.
Then the isolation control ISOLATION is asserted to switch the output mux to the
retention latch and the logic cell goes into sleep where the virtual power VVDD is
shut off.

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 Recommendations and Pitfalls for Isolation

Recommendations:
• Isolate the outputs of power gated blocks.

Pitfalls:
• Make sure the isolation cells really are always powered on.
• Isolation clamps on clocks can considerably complicate the clock tree synthesis
and timing closure. Clock tree balancing in particular can become difficult. If
possible, avoid clocks that are generated in a power gated block and used
externally to the block

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 Retention Registers

Retention: Retention is a technique for retaining the state value of registers in a

powered down domain

Retention Register: A register than extends the functionality of a normal

register(flip-flop) with the ability to retain its state during power down, assuming an
appropriate second (always on) supply as well as save and restore signal is on

Shadow Register: The section of a retention register retains the register state
during power down. Also known as a balloon registers (due to the topology of
some implementations).
D Q
Main
Register
save restore
Shadow
Register

CLK
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SAVE RESTORE
 Retention Registers

• Retention registers are used in power gating technique. For some power-gated
blocks, it is highly desirable to retain the internal state of the block during
power down, and to restore this state during power up
• Such a retention strategy can save significant amounts of time and power
during power up. One way of implementing such a retention strategy is to use
retention registers in place of ordinary flip-flops
• Retention registers typically have an auxiliary or shadow register that is slower
than the main register but which has much less leakage current. The shadow
register is always powered up, and stores the contents of the main register
during power gating

Full retention Vs. Partial retention

• Full State Retention: Retaining the full state of the block – that is, replacing all
registers with retention registers – provides the most robust, easily
verified, and most transparent form of power gating
• Partial State Retention: Retaining the partial state means retaining only some
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 Thank You

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