An 8-Channel Power-Efficient Time-Constant-Enhanced

Analog Front-End Amplifier for Neural Signal Acquisition

Jung-Chen Chung1, Wei-Ming Chen2, and Chung-Yu Wu1,2
1
Department of Electronics Engineering and Institute of Electronics
2
Biomedical Electronics Translational Research Center
National Chiao Tung University, Hsinchu, Taiwan

Abstract— In this paper, an 8-channel low-power analog In this paper, an 8-channel low-power AFEA with TCEAs is
front-end amplifier (AFEA) with time-constant-enhanced proposed for neural signal acquisition. In the proposed AFEA,
topology is proposed for neural signal acquisition. The AFEA is an ultra-low high-pass cut-off frequency of 0.16 Hz is realized
composed of eight time-constant-enhanced amplifiers (TCEAs) by the TCEA. The TCEA not only enhance the equilibrium
and high-pass filters (HPFs), a multiplexed transconductor time constant, but also provides a high voltage gain of 50.7 dB
(MGM) and a transimpedance amplifier (TIA). The AFEA is with only 4 pF input capacitance which reduce the required
designed and simulated in 65nm CMOS technology. The chip area. In addition, the noise and power consumption
bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 performances are also enhanced in the proposed TCEA to
dB with power consumption of 1.77 µW per channel. The TCEA
obtain a NEF of 2.13.
is designed to reduce the high-pass cut-off frequency to 0.16 Hz
and achieve a high gain of 50.7 dB with only 4 pF input This paper is organized as follows: Section II presents the
capacitance. The power consumption of TCEA is 1.08 µW under proposed system architecture of neural signal acquisition
1-V power supply. The noise efficiency factor (NEF) of the TCEA system. In section III, the circuit design is described in detail.
is 2.13 with 4.46 µVrms input-referred noise. Section IV presents the simulation results of this system.
Finally, a concluding remark of this work is made in section V.
Keywords—analog front-end, low noise, low power, time constant
enhance. II. SYSTEM ARCHITECTURE
I. INTRODUCTION The architecture of the proposed system is shown in Fig. 1
which consists of eight TCEAs and HPFs, a MGM and a TIA.
Neural signal acquisition system is one of the most important The neural signal is sensed and amplified by the TCEA with
components in the application of researching and treating adjustable gain of 30/40/50 dB. The EDO is filtered out by the
neurological disorders such as spinal cord injuries, Parkinson’s TCEA, and a passive HPF is designed between TCEA and
disease, epilepsy and so on [1]. To acquire such weak electrical MGM to prevent the offset voltage which is from the TCEA.
signals (typically from tens of microvolts to a few millivolts) To reduce the total power consumption and hardware cost, the
generated by neurons, the neural signal acquisition circuit output signals of the TCEAs share one MGM and one TIA for
requires a low-noise and high-gain amplifier. In addition, the channel multiplexing. The MGM and TIA stage also provide a
neural signal is mainly composed of local field potential and second gain of 10 dB. The amplified neural signal is further
spike potential which are mainly distributing in 1-300 Hz [2] sent to the following processing unit such as analog-to-digital
and 300-5k Hz [3], the bandwidth of the amplifier should be converter (ADC) for further operation.
designed precisely for different neural signal. For the purpose
of implantation, it should be designed with low power
consumption to increase the battery life and eliminate the need
for battery replace surgery.
Aside from amplifying the neural signal with small
amplitude, to eliminate the electrode dc offset (EDO) is the
most important problem needed to solve. The capacitive-
feedback topology with pseudo-resistor to provide a low high-
pass cut-off frequency to eliminate the EDO is proposed in [4],
[5]. The capacitive-feedback topology provides precise voltage
gain of the capacitance ratio, but requires large capacitor area.
Connecting a passive RC filter previous to the amplifier is
proposed to realize an implantable neural signal acquisition
circuit [6]. However, the gain of the open-loop topology would
drift with process variation. To enhance the noise performance,
a chopper-stabilized instrumentation amplifier is presented in
Fig. 1. System architecture of the proposed AFEA.
[7], but the EDO rejection ability might be limited.

This paper is particularly supported by "Aim for the Top University Plan"
of National Chiao Tung University and Ministry of Education, Taiwan, and
under Research Projects of MOST 103-2220-E-009 -006.

978-1-4799-8391-9/15/$31.00 ©2015 IEEE 1234

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 Fig. 4. Frequency responses comparison of the proposed TCEA and the
conventional capacitive feedback pre-amplifier.
Fig. 2. Structure of conventional capacitive feedback pre-amplifier [4].

Fig. 3. Structure of TCEA with time constant enhanced topology. Fig. 5. Schematic of input capacitors, C1.

The conventional structure of pre-amplifier is shown as a 40-dB-gain OP3. To reduce the values of required impedance
Fig. 2 [4] which employs the capacitive-feedback topology and capacitance, a 4pF input capacitor is adopted in the
with an operational amplifier OP1. R1,conv is realized with proposed TCEA.
pseudo-resistor to provide a limited high impedance (>1012 Ω).
The transfer function is shown as: The input-referred noise of TCEA is shown as:
, ,
(1) , · , · (3)
,
, ,

From (1), the high-pass cut-off frequency (fhp,conv) is where Cp is the parasitic capacitance of the input node of OP2,
1/2πR1,convC2,conv and the mid-band gain (A,conv) is -C1,conv/C2,conv. Vni, Vni,OP2 and Vni,OP3 are the input-referred noise of TCEA,
To obtain a low high-pass cut-off frequency with limited high OP2 and OP3 respectively, and A2 is gain of OP2.
impedance, the value of C2,conv should be large. The value of
C1,conv is A,con C2,conv which requires A,con times of the chip area , · (4)
of C2,conv. To obtain a high system gain, C1,conv occupies
enormous chip area. From (4), the input-referred noise is the same as that of the
conventional capacitive configuration [4]. The gain and
This paper proposes a new TCEA with time-constant- bandwidth are designed programmable. C1 is designed
enhanced topology as shown in Fig. 3 which OP1 is adjustable to modulate the gain. The low-pass cut-off
decomposed to OP2 and OP3. The transfer function can be
frequency of the TCEA is designed by changing the output
shown as:
capacitors of OP2, which are made by switches serial with
. (2) capacitors.
/
III. CIRCUIT DESIGN
where A3 is the gain of OP3.
A. Time-Constant-Enhanced Amplifier
The mid-band gain of the TCEA is the same with (1), but
the high-pass cut-off frequency is 1/2πA3R1C2. Compare to In Fig. 3, the input capacitance C1 is designed adjustable
conventional structure, the TCEA only requires 1/A3 times and implemented with fully differential topology as in Fig. 5.
time constant to achieve the same high-pass cut-off frequency A capacitor array with switches is designed to adjust the gain
which results lower R1 and C2 that decreases the required chip of the TCEA. However, the leakage current of the turned-off
area dramatically. switches create short path in extremely low frequency
(< 1 Hz). To avoid this problem, the signal Gain1 and Gain2
Fig. 4 is the frequency response comparison between the control the switch sets between C12, C13, Vinp and Vinn. The
TCEA and the conventional topology which simulated with an amplifier senses differential signal, and the cross-connected
ideal amplifier model. The values of total gain of amplifier, capacitors behave as negative capacitors in differential mode.
capacitors and resistor are the same and the gain of OP3 is set The switch sets connect the capacitors C12 and C13,
to 100. It can be seen, the high-pass cut-off frequency of the crossing /parallel to Vap and Van as positive/negative capacitors.
TCEA is lower than conventional pre-amplifier of 100 times. There are no high-impedance nodes. Thus, this programmable
For the neural signal acquisition pre-amplifier designed in [5], capacitance does not affect the low-frequency response. The
a 50 dB gain requires 66 pF input capacitance. By employing equivalent C1 is shown as (5)
TCEA with pseudo-resistor of the same impedance in [5], a
gain of 50 dB only requires 0.66 pF capacitance with · · (5)

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 Fig. 8. Schematic of multiplexed transconductor.
Fig. 6. Schematic of OP2.

where Itot is the total current, BW is the bandwidth of amplifier

and π/2 is the effective noise bandwidth factor. From (9), the
limitation of NEF of this amplifier is 1.43.
The OP3 is a fully differential amplifier as a simple
differential pair, which provides 38dB gain to amplify the
capacitance of C2 shown in Fig. 5. Moreover, OP3 consumes
Id/5 current. Taking the input capacitor of OP2 and the current
Fig. 7. Schematic of high-pass filter. of OP3, into (4) and (9), the limitation of the NEF of TCEA is
1.94.
where Gain1 and Gain2 are 1 in parallel mode and -1 in
crossing mode. The capacitance of C11, C12 and C13 are 2.2 pF,
1.4 pF and 0.4 pF respectively. Thus, the equivalent · 1.94 (10)
capacitance is {4pF, 1.2pF, 0.4pF} at {{gain1, gain2}={1,1},{-
1,1},{-1,-1}}. B. High-pass Filter
The schematic of OP2 employed in TCEA is shown in Fig. 6. To prevent the output offset voltage amplified by the
The gain of OP2 is shown as (6) following stage, a HPF is designed along with the TCEA. The
, , , ,
HPF is designed with passive device as shown in Fig. 7.
(6)
, , , , C. Multiplexed Transconductor
where gm and ro are the transconductance and output The MGM is designed as shown in Fig. 8. To reduce the
impedance of the MOS device. power consumption, the transconductor is designed to combine
To decrease the noise of the TCEA which mainly with multiplexer, only one enable signal (EN0 - EN7) is
contributed from OP2, the OP2 has both PMOS and NMOS turned-on during operation. The settling time should be lower
transistors adopted as input pairs to achieve a better noise-to- than 1µs for a presumed 500kS/s and 1pF loading capacitance
power tradeoff. The bias current of input is defined as ID, so ADC.
the current of each branch is ID/2. The input pair transistors The transconductance of this MGM is shown as:
operate in deep sub-threshold region, transconductance of
transistor in input pair is: (11)
, , , ,
(7)
D. Transimpedance Amplifier
where gm is the transconductance of each transistor in input The structure of TIA is shown in Fig. 1. In order to drive
pair, IB is the bias current, UT is the thermal voltage, and κ is ADC, the operational amplifier OPTIA requires a high-
the gate coupling coefficient of approximately 0.7 in deep sub- bandwidth and rail-to-rail output stage. Thus, OPTIA is designed
threshold region. in a two-stage class-AB structure [8]. The gain of TIA is RTIA.
The current thermal noise of each sub-threshold transistor is: The parasitic capacitor Cp,TEA from the MGM output and input
of TIA generates a pole to the feedback path of TIA. Thus,
, 4 (8)
CTIA is adopted parallel connected with RTIA to compensate the
where k is Boltzmann’s constant and T is the Kelvin pole generated by Cp,TEA and RTIA. The loop gain is described
temperature. as:
The noise efficiency factor (NEF) is calculated as follow: (12)
/

where ATIA and ωTIA are the gain and the pole of OPTIA.
, · · ·
IV. SIMULATION RESAULTS
· , · ·
· The proposed neural signal acquisition system is designed
· · · ·
and simulated in TSMC 65nm CMOS technology. The post-
1.43 (9) simulation results show that the proposed 8-channel AFEA for
neural signal acquisition system can provide adjustable gain of
41.2/50.7/61.2 dB as shown in Fig. 9. With the employment of
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 of the proposed AFEA satisfies the requirement for neural
signal acquisition which provides a promising solution to
design the neural acquisition system. The proposed AFEA is
under fabrication process and will be measured and verified
with animal experiment.
ACKNOWLEDGMENT
The authors would like to thank Taiwan Semiconductor
Manufacturing Company (TSMC) and National Chip
Implementation Center (CIC) for chip fabrication and technical
support.
Fig. 9. Simulated AC response of the proposed AFEA.
TABLE I COMPARISON OF PRE-AMPLIFEIR
[5] [6] [7] This work1
0.6µm 0.13µm 65nm
Technology 65nm CMOS
CMOS CMOS CMOS
Supply (V) 2.8 1.2 1 1
Gain (dB) 39.4 40 40 41.2/50.7/61.2
Current (µA) 0.872 29.2 1.8 1.082 /14.23
Bandwidth (Hz) 1.3k 10k 100 7k
High-pass
0.36 <0.3 0.5 0.16
frequency (Hz)
Fig. 10. Dc output voltage of 100 runs of Monte Carlo simulation.
Integrated input-
referred noise 3.07 2.2 6.7 4.46
(µVrms)
NEF 3.09 4.5 3.3 2.132
Cin (pF) 20 20 12 4
1
simulation results, 2TCEA, 3AFEA.

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V. CONCLUSION
In this paper, an 8-channel low-power AFEA with time-
constant-enhanced topology is proposed for neural signal
acquisition. The AFEA is designed and simulated in 65nm
CMOS technology. The TCEA is designed to enhance the time
constant and reduce the high-pass cut-off frequency. It has
been verified from the simulation results that the performance

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