APPLICATION NOTE 74

Application Note 74
Reading and Writing iButtons
via Serial Interfaces

I. INTRODUCTION For read operations all devices are satisfied with a 5kΩ
An iButtonTM is a chip housed in a stainless steel enclo- pull–up resistor to supply energy and to terminate the
sure. The electrical interface is reduced to the absolute 1–Wire bus. iButton devices based on non–volatile
minimum, i.e., a single data line plus a ground refer- RAM (DS1991 to DS1996) can also be written using this
ence. The energy needed for operation is either “stolen” same interface. Due to their different technology,
from the data line (“parasitic power”) or is taken from an EPROM based iButtons (DS1982 to DS1986) also
embedded lithium cell. The logical functions range from require pulses of up to 12V for programming. Since they
a simple serial number to password–protected memory, cannot be erased, EPROM iButtons are referred to as
to 64K bits and beyond of nonvolatile RAM or EPROM, Add–Only Memories. Another device, the DS1920 Tem-
to a Temperature iButton, to a real time clock plus 4K bits perature iButton, gets its energy for temperature con-
of nonvolatile RAM. Common to all iButtons is a globally version through a low impedance active pull–up to 5V.
unique registration number, the serial 1–WireTM proto- Different requirements for writing or special functions
col, presence detect, and communication in discrete are the reason for several types of interfaces.
time slots. Table 1 gives an overview of the available
devices.

iButton DEVICES Table 1

Device Family Serial Memory Bits Protected Real Time Interval Cycle
Type Code Number Type NV RAM bits Clock Timer Counter
DS1990A 01H yes ––– ––– ––– ––– –––
DS1991 02H yes 512, NVRAM 3 * 384 ––– ––– –––
DS1992 08H yes 1K, NVRAM ––– ––– ––– –––
DS1993 06H yes 4K, NVRAM ––– ––– ––– –––
DS1994 04H yes 4K, NVRAM ––– yes yes yes
DS1995 0AH yes 16K, NVRAM ––– ––– ––– –––
DS1996 0CH yes 64K, NVRAM ––– ––– ––– –––
DS1982 09H yes 1K, EPROM ––– ––– ––– –––
DS1985 0BH yes 16K, EPROM ––– ––– ––– –––
DS1986 0FH yes 64K, EPROM ––– ––– ––– –––
DS1920 10H yes 16, EEPROM TEMPERATURE iButton

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 APPLICATION NOTE 74

II. 1–WIRE INTERFACE at a voltage of 2.8V or higher to recharge the internal

A. General Information capacitor.
iButtons are self–timed silicon devices. The timing logic
provides a means of measuring and generating digital Under nominal conditions, an iButton will sample the
pulses of various widths. Data transfers are bit–sequen- line 30 µs after the falling edge of the start condition. The
tial and half–duplex. Data can be interpreted as com- internal time base of iButton may deviate from its nomi-
mands (according to the prearranged format identified by nal value. The allowed tolerance band ranges from 15
the family code) that are compared to information already µs to 60 µs. This means that the actual slave sampling
stored in the iButton to make a decision, or can simply be may occur anywhere between 15 and 60 µs after the
stored in the iButton for later retrieval. iButtons are con- start condition, which is a ratio of 1 to 4. During this time
sidered slaves, while the host reader/writer is considered frame the voltage on the data line must stay below
a master. VILMAX or above VIHMIN.

B. DC Requirements C.1. Write Time Slots

iButtons operate in an open drain environment on volt- In the 1–Wire system, the logical values of 1 and 0 are
age levels ranging from 2.8V (minimum pull–up voltage) represented by certain voltage levels in special wave-
to 6V (maximum pull–up voltage). All voltages greater forms. The waveforms needed to write commands or
than 2.2V are interpreted as logic 1 or HIGH, voltages data to iButtons are called write–1 and write–0 time
less than 0.8V are considered as logic 0 or LOW. The slots. The duration of a low pulse to write a 1 (tLOW1, Fig-
pull–up voltage must be a minimum of 2.8V to recharge ure 1 ) must be shorter than 15 µs. To write a 0, the dura-
an internal storage capacitor that is used to supply tion of the low pulse (tLOW0, Figure 2) must be at least 60
power during periods when the data line is low. The size µs to cope with worst–case conditions.
of this capacitor is about 800 pF. This capacity is seen
for a short time when an iButton is contacted by a probe. The duration of the active part of a time slot can be
After the capacitor is charged, only a very small fraction extended beyond 60 µs. The maximum extension is lim-
of this capacity is recognizable, according to the charge ited by the fact that a low pulse of a duration of at least
required to refill to full charge. The total time constant to eight active time slots (480 µs) is defined as a Reset
charge the capacitor is defined by the capacitor itself, the Pulse. Allowing the same worst–case tolerance ratio, a
internal resistances of about 1 kΩ, the resistance of the low pulse of 120 µs might be sufficient for a reset. This lim-
cable and contacts, the cable capacitance, and the resis- its the extension of the active part of a time slot to a maxi-
tor pulling up the data line. mum of 120 µs to prevent misinterpretation with reset.

At the end of the active part of each time slot, iButton

C. AC Requirements needs a recovery time tREC of a minimum of 1 µs to pre-
Timing relationships in iButtons are defined with respect
pare for the next bit. This recovery time is the inactive
to time slots. Because the falling slope is the least sensi-
part of a time slot, since it must be added to the duration
tive to capacitive loading in an open drain environment,
of the active part to obtain the time it takes to transfer
iButtons use this edge to synchronize their internal tim-
one bit. The wide tolerance of the time slots and the
ing circuitry. By definition the active part of a 1–Wire time
non–critical recovery time allow even slow micropro-
slot (tSLOT) is 60 µs. After the active part of the time slot,
cessors to meet the timing requirements for 1–Wire
the data line needs to be inactive for a minimum of 1 µs
communication easily.

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 APPLICATION NOTE 74

WRITE–ONE TIME SLOT Figure 1

tSLOT tREC
VPULLUP
VPULLUP MIN
VIH MIN
iButton
VIL MAX SAMPLING WINDOW
0V
tLOW1

15 µs
60 µs

RESISTOR
60 µs < tSLOT < 120 µs
MASTER 1 µs < tLOW1 < 15 µs
iButton 1 µs < tREC <

WRITE–ZERO TIME SLOT Figure 2

tREC
tSLOT
VPULLUP
VPULLUP MIN
VIH MIN
iButton
VIL MAX SAMPLING WINDOW
0V
15 µs

60 µs
tLOW0

60 µs < tLOW0 < tSLOT < 120 µs

RESISTOR
1 µs < tREC <

MASTER

iButton

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 APPLICATION NOTE 74

C.2. Read Time Slots probe, it will pull its data line low via an internal current
Commands and data are sent to iButtons by combining source of 5 µA. This simulates a Reset Pulse of unlim-
Write–Zero and Write–One time slots. To read data, the ited duration. As soon as the iButton detects a high level
master has to generate Read–Data time slots to define on the data line, it will generate a Presence Pulse.
the start condition of each bit. The Read–Data time slot
looks essentially the same as the Write–One time slot The nominal values are 30 µs for tPDH and 120 µs for
from the master’s point of view. Starting at the high–to– tPDL. With the same worst–case tolerance band, the
low transition, the iButton sends one bit of its addressed measured tPDH value indicates the internal time base of
contents. If the data bit is a 1, the iButton leaves the the fastest device. The sum of the measured tPDH and
pulse unchanged. If the data bit is a 0, the iButon will pull tPDL values is five times the internal time base of the
the data line low for tRDV or 15 µs (Figure 3). In this time slowest device. If there is only one device on the line,
frame data is valid for reading by the master. The dura- both values will deviate in the same direction. This cor-
tion tLOWR of the low pulse sent by the master should be relation can be used to build an adaptive system. Spe-
a minimum of 1 µs with a maximum value as short as cial care must be taken to recalibrate timing after every
possible to maximize the master sampling window. In reset since the individual timing characteristics of the
order to compensate for the cable capacitance of the devices vary with temperature and load.
1–Wire line the master should sample as close to 15 µs
after the synchronization edge as possible. Following The accuracy of the time measurements required for
tRDV there is an additional time interval, tRELEASE, after adaptive timing is limited by the characteristics of the
which the iButton releases the 1–Wire line so that its master’s input logic, the time constant of the 1–Wire line
voltage can return to VPULLUP. The duration of tRELEASE (pullup resistor x cable capacitance) and the applied
may vary from 0 to 45 µs; its nominal value is 15 µs. sampling rate. If the observed rise time or fall time
exceeds 1 µs or the highest possible sampling rate is
C.3. Reset and Presence Detect less than 1 MHz, adaptive timing should not be
The Reset Pulse provides a clear starting condition that attempted.
supersedes any time slot synchronization. It is defined
as a single low pulse of minimum duration of eight time C.4. Example Pulse Train
slots or 480 µs followed by a Reset–high time tRSTH of For illustrative purposes, a reference pulse train has
another 480 µs (Figure 4). After a Reset Pulse has been been defined (Figure 5) to explain how the waveforms
sent, the iButton will wait for the time tPDH and then gen- are generated rather than showing a complete session.
erate a Presence Pulse of duration tPDL. No other com- It starts with a reset sequence including a Presence
munication on the 1–Wire bus is allowed during tRSTH. Pulse. Further time slots show all waveforms of reading
The Presence Pulse can be used to trigger a hardware and writing 1s and 0s. Any communication session can
interrupt or to automatically power up equipment like be constructed from the waveforms of this pulse train.
Touch Pens. If an iButton is disconnected from the

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 APPLICATION NOTE 74

READ–DATA TIME SLOT Figure 3

tSLOT tREC
VPULLUP
VPULLUP MIN
VIH MIN
MASTER SAMPLING
VIL MAX WINDOW
0V
tLOWR tRELEASE
tRDV

60 µs < tSLOT < 120 µs

RESISTOR 1 µs < tLOWR < 15 µs
MASTER 0 < tRELEASE < 45 µs
1 µs < tREC <

iButton
tRDV = 15 µs

RESET AND PRESENCE PULSE Figure 4

tRSTH
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
tRSTL tPDL
tR
tPDH

RESISTOR
480 µs < tRSTL <
*
MASTER 480 µs < tRSTH <
(includes recovery time)
iButton 15 µs < tPDH < 60 µs
60 µs < tPDL < 240 µs

* In order not to mask interrupt signalling by other devices on the 1–Wire bus, tRSTL + tR should always be less than
960 µs.

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102698 6/40
APPLICATION NOTE 74

REFERENCE PULSE TRAIN Figure 5

MASTER TX MASTER RX
“RESET PULSE”
MATER WRITE “0” SLOT MASTER WRITE “1” SLOT MASTER READ “0” SLOT MASTER READ “1” SLOT
“PRESENCE
PULSE”
VCC
1–WIRE
BUS
GND
 APPLICATION NOTE 74

III. FUNDAMENTALS Since all timing depends on the clock frequency of the
A. TTL Interface microcontroller, it is required to count the number of
This category includes all logic families and micropro- clock cycles for the execution of each command within
cessors that use positive logic with a maximum 0.8V for the loop. The level of an output pin of a microprocessor
a logical 0 or LOW and a minimum of 2.2V for a logical 1 will usually not change at the end of a command, but a
or HIGH. These voltages combined with a current few clock cycles earlier. The actual reading from any
source capability of at least 1 mA and a sink capability of input pin also occurs some clock cycles before the end
more than 4 mA interface to a broad class of digital elec- of the command. If the description of the microproces-
tronics. sor does not give sufficient details on this, a test series
with different clock frequencies may be required. As
Since the 1–Wire bus is an open drain system, an open long as the microprocessor is executing time–sensitive
drain/collector driver is required to connect the output code, i.e., reading from the 1–Wire bus or writing to it,
port to the bus (Figure 6). This driver can be a general jumps or calls may occur only while the 1–Wire bus is
purpose NPN transistor with a resistor connected idle. Interrupts from other sources than the 1–Wire bus
between base and output port or an n–channel MOS- must be disabled.
FET or any open drain/collector driver available in the
logic family as long as the pullup voltage is equal to the B. RS232 Interface
driver voltage. Even a tri–state driver with its logic input This section covers all interfaces that use a special con-
tied to ground can be used, connecting the output gate troller to generate all timing and reference signals
to the tri–state control input. Depending on the charac- required for serial communication. The typical controller
teristics of the driver (inverting/non–inverting), it may be for this type of interface is the UART 8250. It relieves the
required to complement the logic value of the output microprocessor of the burden of time–critical software
gate to compensate for the driver’s signal inversion. execution. The microprocessor simply puts the charac-
ter code to be transmitted into the transmit register of the
Reading from the 1–Wire bus can usually be accom- UART and the UART will do the work. A character is
plished by directly connecting the 1–Wire bus to the received by the microprocessor just by reading the
input port of the master. If the pullup–voltage of the UART’s receive register. If the serial transmission is fin-
1–wire bus is too low or if the capacity of the cable pro- ished or if there is data for the microprocessor, this
duces slopes too slow for the logic family, it may be condition is signalled by the UART through flags that
required to employ a comparator as interface and to can be polled or by interrupts.
adjust the reference voltage to optimize noise margins
and timing characteristics. If the comparator inverts the To function properly, the UART requires configuration
signal, this inversion needs to be compensated by the with respect to baud rate, number of data bits per char-
software. acter, parity and number of start and stop bits. These
terms are common for serial communication, but fit the
Generally it is recommended to test this type of interface needs of 1–Wire networks with their time slots and sep-
carefully, starting with reset pulses generated by soft- arate synchronization if a bit rather than a character is
ware and watching the slopes with an oscilloscope. If framed by the start condition. For 1–Wire communica-
the timing specifications of Figure 4 are met, and the tion the UART is set up for a high baud rate and each
presence pulse is seen, one may proceed and test the character delivered by the UART represents a bit on the
software to generate the Write–Zero and Write–One 1–Wire bus. The microprocessor must separate the bits
time slots. After this works properly, the next step is of a byte, least significant bit first, and write them as
reading the ROM. This is done by performing a reset appropriate characters to the UART. To read data, the
cycle first, followed by 2 Write–One time slots, 2 Write– microprocessor has to assemble the bits received
Zero time slots, 2 Write–One time slots and 2 Write– through characters back into bytes. These functions are
Zero time slots (this is equivalent to sending 33H, least not time–sensitive and can easily be programmed in a
significant bit first). After this, 64 Read Data time slots high level language.
need to be generated.

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 APPLICATION NOTE 74

TTL INTERFACING Figure 6

VPULLUP

RPULLUP

TTL 1–WIRE

IN DATA

GROUND

OUT

RS232 Conventions dent wires, called RXD and TXD. Since RS232 ports are
Unlike TTL logic, RS232 has been established to trans- often used for communication via phone lines, several
port data over long lines. Therefore different current control signals are also included in the standard. Not all
drive characteristics and higher voltages are required to of these control signals need to be implemented with a
represent the logic levels 0 and 1. communication device. For 1–Wire applications only
the control signals DTR (Data Terminal Ready) and RTS
The values to be expected are: (Request to send) are needed. Other signals often
+3V to +15V for 0, found with RS232 are DSR (Data Set Ready), which is
which is identical to the polarity of the start bit and the response to DTR, and CTS (Clear To Send), which is
–3V to –15V for 1, the response to RTS. How these signals are provided
which is identical to the polarity of the stop bit and on a connector is detailed in Table 2. Full documentation
the idle state. The voltage range from –3V to +3V is on RS232 is beyond the scope of this application note.
undefined. For a complete description please refer to other litera-
ture.
All voltages are measured with respect to ground. The
receive channel and the transmit channel are indepen-

Table 2
9–PIN 25–PIN
SIGNAL CONNECTOR CONNECTOR DESCRIPTION FUNCTION
RXD 2 3 Receive Data input
TXD 3 2 Transmit Data output
DTR 4 20 Data Terminal Ready output
RTS 7 4 Request to Send output
GND 5 7 Ground (reference)
DSR 6 6 Data Set Ready input
CTS 8 5 Clear to Send input

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 APPLICATION NOTE 74

Hardware Simplified Model +1 Interrupt Enable Register

The standard hardware of a RS232 interface is shown in +2 Interrupt Identification Register
Figure 7a. The UART is hooked to the system bus like (read only)
an 8–bit memory device. The three address inputs A0 to +3 Line Control Register
A2 make the UART appear as a block of 8 read/write +4 Modem Control Register
memory locations. On the other side there are the serial +5 Line Status Register
communication signals and the control signals men- +6 Modem Status Register
tioned above. Since the UART is a 5V device, special
drivers and receivers for handling higher voltages are The meaning of the UART’s control bits and their posi-
required. Circuit diagrams of bipolar integrated drivers tion within the control registers is detailed in Figure 8.
(1488) and receivers (1489) are shown on Figures 7b For 1–Wire communication, the Interrupt Identification
and 7c. CMOS drivers and receivers are also available Register and Modem Status Register are not used.
as standard products.
To define the speed or baud rate of a serial communica-
By design, the output current of an RS232 driver is lim- tion, there is a 16 bit register, called Divisor Latch. This
ited to ±10 mA typically. Since the voltage definitions for register is accessed as two bytes using the same
1 and 0 on the RS232 channel are reversed with respect addresses as the Data Register (least significant byte)
to the conventions of positive logic, RS232 drivers and and the Interrupt Enable Register (most significant
receivers are actually inverting devices. The inversion byte). To access the Divisor Latch, the Divisor Latch
in the transmit channel is compensated through an Access Bit DLAB must be set to 1. DLAB is the most sig-
inversion in the receive channel. Thus a 1 written to the nificant bit of the Line Control Register. As long as DLAB
transmit register will appear as a 1 at the serial output, is set, the Data Register and the Interrupt Enable Regis-
as –15V at TXD, as a 1 at the serial input of the receiver ter are not accessible. For the commonly used crystal
and finally be read as a 1 in the receive register of the frequency of 1.8432 MHz, the divisor latch must
receiving UART. contain a number between 2304 (900hex, 50 bps) and
1 (115.2k bps).
For energy efficiency with battery operated equipment,
the RS232 drivers and receivers are often replaced by 1–Wire Communication through the UART
simple 5V inverting drivers. This is definitely not com- As mentioned above, to write one bit to the 1–Wire bus,
patible with the RS232 standard, but may be sufficient to the UART is programmed to transmit one character.
control a modem or to transfer data through a short Since the receive and transmit channels of the UART
cable. Interfaces like this are called 5V RS232 within are operating independently, but using the same com-
this application note. They run on the same software as munication setup, reading from and writing to the
the standard RS232, but are electrically almost the 1–Wire bus can occur at the same time. The start condi-
same as the TTL interface. tion generated at the UART’s serial output is fed to the
1–Wire bus and is simultaneously returned to the serial
Programmer’s Model input, triggering the process of reading one character.
To write software for the 8250 UART one must know the The waveform is completely defined by the baud rate,
basic address where the registers of the UART are the polarity of the start and stop bits and the bit pattern of
hardwired to. This address is generally an equipment the character. The serial output of the UART is high
specific variable, and therefore will be referenced by the (~ 5V, idle) between characters, low (~0V) for the start
name SPA (Serial Port Address) rather than by a physi- bit and equal to the value of the data bit being trans-
cal address. Of the 8 theoretically accessible addresses mitted. An idle (~5V) to low (~0V) transition at the
within the UART only 7 are really implemented, using UART’s serial input triggers the process of receiving a
the relative addresses 0 to 6. The names of these regis- character. The first bit is understood as start bit; the
ters are as follows: remaining bits are shifted into the receive register in the
same polarity as they arrive at the serial input. Bits
address: received after the receive register is full, are ignored.
SPA +0 Receive (read)/Transmit (write)
Data Register

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APPLICATION NOTE 74

HARDWARE OVERALL CONCEPT Figure 7a

16
XIN
17
XOUT
A0–A2
15
BAUDOUT
9
RCLK RS–232
12 CONNECTOR
CS0
13 33 DTR
CS1 DTR 20
32 RTS
RTS 4
34
OUT1
31
OUT2

39
RI +5V
38
8250 DCO 8
(UART) 37 DSR
DSR
6
36 CTS
CTS
5
D0–D7

11 TXD
SOUT 2
21
RD
18 10 RXD
WR SIN 3
35 30
MR INTR
22 24
RD CSOUT
19 23 GND
WR DDIS 7
25 29
ADS NC
1
14
CS2

20 40
GND +5V
VSS (VCC)

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 APPLICATION NOTE 74

TYPICAL DRIVER Figure 7b

VCC

8.2k 6.2k

INPUT

INPUT
70
300
OUTPUT

3.6k

GND

10k
7k 70

VEE

TYPICAL RECEIVER Figure 7c

VCC

RF IS EITHER 6.7 OR 1.6 kΩ 9k 5k 1.7k

RF
RESPONSE CONTROL
OUTPUT

RF
3.8k
INPUT

10k

GROUND

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 APPLICATION NOTE 74

Figure 8
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
SPA + 1 bit 15 baud rate divisor most significant byte bit 8 DLAB=1
SPA + 0 bit 7 baud rate divisor least significant byte bit 0 DLAB=1
SPA + 0 receive/transmit data register DLAB=0
SPA + 1 0 0 0 0 Interrupt enable; 0=disabled DLAB=0
SPA + 2 0 0 0 0 0 Interrupt ident. register, not DLAB=0
used
SPA + 3 DLAB, Set Stick Even Parity Nr. of WLS1 WLS0 DLAB=0
Divisor Break, Parity, Parity Enable, stop Word Word
Latch 0=dis- 0=dis- don’t 0=dis- bits, 0=1 Length Length
Address abled abled care abled stop bit
Bit
SPA + 4 0 0 0 Loop Out2 Out1 RTS, DTR, DLAB=0
Request Data
to Send Terminal
Ready
SPA + 5 0 TSRE, THRE, Break Framing Parity Overrun Data DLAB=0
transmit transmit Interrupt Error Error Error Ready
shift reg- hold reg-
ister ister
empty empty
SPA + 6 Modem Status Register, not used DLAB=0

Reset and Presence Detect fast 1–Wire communication. If the character code is 00,
The reset and presence detect cycle is performed by than a Write–Zero time slot is generated. A character
setting the baud rate to 10473 bps (Divisor Latch = code of FF will produce a Write–One time slot.
11decimal), the character length to 8 bits (WLS0=1,
WLS1=1) and transmitting the character code F0. As long as writing to the 1–Wire bus is desired, all char-
Including the start bit, this produces a pulse of 5 x 95.5 acters received by the UART must be read and can be
µs low (start bit plus four 0’s) followed by 5 x 95.5 µs high discarded. To read data, Write–One time slots must be
(four 1’s plus stop bit) at the serial output of the UART. If generated. Bits received from the iButton are returned in
an iButton is present, then it will assert its presence their true form in the least significant bit of the character
pulse during the time interval where the most significant code found in the receive data register. If the iButton
bits of the character code are transmitted. If after the sends a one, all bits of the character code will read one.
transmission the receive data register reads F0, then If the iButton sends a zero, one or more of the least sig-
there is no iButton. If one or more bits of the transmitted nificant bits of the character code will be zero, depend-
F are changed to 0s, than a presence pulse was ing on the internal time base of the iButton.
received.
Not all UARTs behave exactly the same as the 8250.
Read/Write One Bit Some of them do not support the character length of 6
To generate data time slots, the UART must be set to a bits. To circumvent potential problems from this restric-
baud rate of 115.2k bps (Divisor Latch = 1). With a char- tion, the software examples in this document always
acter length of 6 bits (WLS0=1, WLS1=0), any trans- use the character length of 8 bits. This extends the
mitted character will consist of a pulse train of 8 x 8.68 transmission of one bit by 17.36 µs and reduces the
µs, beginning with a low start bit, followed by true data effective baud rate from 14.4k bps to 11.5k bps, but
bits and a high stop bit. This matches the waveform for remains well within the specification of 1–Wire timing.

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 APPLICATION NOTE 74

IV. CIRCUITS FOR 5V INTERFACES (TTL If desired, a small signal bipolar transistor or any avail-
AND RS232) able open–drain or open–collector inverting driver can
A. TTL Read All be used instead of Q1. If Q1 is an npn–transistor, a
This is the simplest interface for iButton applications. It resistor bypassed by a small capacitor between the TX–
is suitable for reading all iButtons and writing NVRAM input and the base terminal is required to limit the input
based devices. The circuit diagram (Figure 9) conforms current.
to the principle of Figure 6. The diodes D1 and D2 pro-
tect transistor Q1 and the input of the microprocessor, The logic level high at TX will produce a low on the
respectively, against damage from electrostatic dis- 1–Wire bus. To generate a Write–One or Read Data
charge (ESD). R1 is the 1–Wire pullup resistor. If the time slot, a short high pulse (1 µs < t < 15 µs) must be
microprocessor runs on 5V, the same supply can applied to the TX input. A Write–Zero Time Slot is
directly be connected to R1. If only a higher supply volt- formed by a 60 µs high pulse at TX. Data from iButtons is
age than 5V is available, any monolithic or discrete posi- received in its true form. If idle, TX must be held at a logic
tive 5V regulator can be used to provide the pullup volt- low level. The reference pulse train and other relevant
age for the 1–Wire bus. waveforms for this circuit are shown on Figure 9a. The
timing for this type of interface is directly generated by
The characteristics of the components are not critical. the microprocessor. A software example for this type of
The transistor 2N7000 has been chosen since it is a interface is found later in this document.
very common product and has a low threshold voltage.

TTL READ ALL CIRCUIT Figure 9

+5V
R1
4.7K

RXD

TXD D2
D1 1N5232
1N5242 5.6V
12V

GND

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APPLICATION NOTE 74

TTL READ ALL WAVEFORMS Figure 9a

MASTER TX MASTER RX
“RESET PULSE” MASTER WRITE “1” SLOT
MATER WRITE “0” SLOT MASTER READ “0” SLOT MASTER READ “1” SLOT
480 us
60 us
480 us “PRESENCE 60 us 15 us 15 us
PULSE” <15 us
VCC
1–WIRE
BUS
GND
=RX

TX
 APPLICATION NOTE 74

B. 5V RS232 Read All and power for the inverter in the receive channel. Every-
This interface is required for equipment that uses a thing else is identical to Figure 9.
UART to provide all timing but does not conform to the
voltage levels of the RS232 standard. The logic levels, The reference pulse train and other important wave-
however, are the correct polarity so that it can be oper- forms for this circuit are shown on Figure 10a. Due to the
ated with the same software as the standard RS232 double inversion in both the transmit and the receive
interface. channel (inverters between UART and RS232 connec-
tor in Figure 7, Q1 and Q2 in Figure 10) the logic levels of
The circuit shown on Figure 10 is suitable for reading all the 1–Wire bus are the same as those at the UART. A 1
iButtons and writing NVRAM based devices. New written to the UART’s transmit register will appear as a 1
compared to Figure 9 are D3, Q2 and R2. D3 has the on the 1–Wire bus, a zero on the 1–Wire bus will be
same function as D2, i.e., ESD protection. Q2 and R2 received as a 0. No software–inversion is needed. Fur-
form an inverter to restore the correct polarity for the ther details on programming the UART for 1–Wire com-
receive channel of the UART. Since there is no pin munication are found section III.b. For software exam-
defined as a power supply with RS232, the DTR signal ples please refer to a later section of this document.
is used to provide the pullup voltage for the 1–Wire bus

5V RS232 READ ALL CIRCUIT Figure 10

+5V (OPTIONAL)

DTR D7
ERA–82–004
R2 R1
2.2k 4.7K

RXD

Q2
2N7000

D3
1N5232
5.6V

TXD
Q1 D2
2N7000 1N5232
D1 5.6V
1N5242
12V

GND

102698 15/40
102698 16/40
APPLICATION NOTE 74

MASTER TX MASTER RX
“RESET PULSE” MASTER WRITE “1” SLOT
MATER WRITE “0” SLOT MASTER READ “0” SLOT MASTER READ “1” SLOT
480 us
60 us
480 us “PRESENCE 60 us 15 us 15 us
PULSE” <15 us
VCC
1–WIRE
BUS
GND
5V RS232 READ ALL WAVEFORMS Figure 10a

(5V)

DTR

RXD

TXD ST 1 2 3 4 5 6 7 8 Stop ST 1 2 3 4 5 6 Stop Start 1 2 3 4 5 6 Stop Start 1 2 3 4 5 6 Stop Start 1 2 3 4 5 6 Stop

0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC–GND 0V

=1–WIRE SEND F0 HEX SEND 00 HEX SEND 3F HEX SEND 3F HEX SEND 3F HEX
GND 10473 BPS (6 BITS)
8 DATA BITS
NO PARITY, 1 STOP BIT
115200 BPS
6 DATA BITS
NO PARITY, 1 STOP BIT
 APPLICATION NOTE 74

C. TTL R/W All (Voltage Converter) more signals and the 12V programming supply can be
The circuits described so far can read all iButtons and provided by a DC–to–DC voltage converter.
write NVRAM–based devices. For other technologies,
however, voltage requirements other than 5V are nec- The complete circuit of such a universal interface in a
essary. One important group of iButtons, called Add– TTL–version is shown in Figure 11. It is a compatible
Only Memories, is based on EPROM technology and superset of Figure 9. The components Q1, R1, D1, D2
therefore needs a programming pulse of 12V to copy and their functions are the same as before. Additional
data from the scratchpad to the EPROM cells. Another requirements include the control input PGMEN with the
device, the Temperature iButton, will operate on 5V but diode D4 for ESD protection, the diode D5, the cas-
requires a low impedance pull–up to 5V while measur- caded inverters R3, Q3, R4 and Q4 & R5, C1, the
ing the temperature. To fulfill the requirements of these pull–up switch Q5 and the controlled voltage converter
and future devices, the circuits described above need to IC1 with its external components L1, D6 and C2.
be upgraded. These two new functions require two

TTL R/W ALL CIRCUIT Figure 11

L1
(SEE TEXT) D6
1N5818
3
SW
1 8
VCC VOUT
C2
7 10 uF
SHDN
GND R5
b c 4 47K
U1 S
SHDN LT1109CN8–12
a G

D Q5
+5V BSS110
C1
R4 150 pF
R3 100K D
100K G
D
S Q4
G
Q3 2N7000
PGMEN 2N7000
D4 S
1N5242
12V

R1
4.7K

RXD
D5
ERA–82–004

G
TXD D2
S Q1 1N5242
D1 2N7000 12V
1N5242
12V

GND

102698 17/40
 APPLICATION NOTE 74

PGMEN is the active low input to activate the pull–up withstanding current peaks of approximately 0.5 A with-
switch. If not connected, PGMEN will be held high out magnetic saturation. To avoid EMI problems, L1
through R3 to avoid unwanted activation of the pull–up should be a pot–core or toroid type; a rod core type is not
switch. The voltage converter can be controlled in three recommended. For further details on the voltage con-
ways: a) hard–wired for continuous operation, b) acti- verter and its external components please refer to the
vated by an external signal, or c) permanently shut appropriate data sheet and application notes. The
down. Case a) is intended for applications which never LT1109 is just one example of available parts. Other
require a strong 5V pull–up. If there is no control signal manufacturer’s components or modules can be used as
available from the master and strong 5V pull–up as well well.
as EPROM programming is required, then a mechanical
switch can be used to switch between case a) and c). The duration of the programming pulse (pulse width of
Case b) offers the most flexibility. For EPROM program- PGMEN) or the strong pull–up is determined by soft-
ming SHDN needs to be high, for strong 5V pull–up it ware. Program examples are given later in this docu-
should be low. If the voltage converter is shut down, L1 ment.
and D6 together with a conducting Q5 provide the
required low–impedance path to 5V. D. 5V RS232 R/W All (Voltage Converter)
The universal upgrade of the interface of Figure 10 is
If the signal PGMEN becomes active (i.e., is low) then shown in Figure 12. The components Q1, R1, D1, D2,
the voltage at the gate of Q4 rises from 0V to approxi- Q2, R2, D3 and their functions are the same as before.
mately 5V, causing Q4 to conduct. This is equivalent to Additional requirements include the control signal RTS
feeding a low level from PGMEN to the gate of Q5. The with the diode D4 for ESD protection, the diodes D5, D7,
capacitor C1 between gate and drain of Q4 slows down the cascaded inverters R3, Q3, R4 and Q4 & R5, C2, the
the rise and fall of Q4’s gate–source voltage and there- pull–up switch Q5 and the controlled voltage converter
fore determines the ramp rate of the programming IC1 with its external components L1, D6 and C2.
pulse. As soon as the gate voltage of Q5 changes from
the quiescent state of 5 or 12V (depending on mode of RTS is used to activate the pull–up switch Q5. DTR may
operation) to 0V, the P–channel transistor becomes act as power supply, if it is able to source 5V at 25 mA.
conducting and pulls the 1–Wire bus either to 12V (if the The strong pull–up is made possible by L1 and D6 if the
voltage converter is on) or to 5V, bypassing R1. voltage converter is shut down. If idle (i.e., the bit con-
trolling RTS in the Modem Control Register of the UART
From the strictly logical point of view, the double inver- is set to 1), RTS will be at 5V. To activate the pull–up
sion (Q3, Q4) is unnecessary. The reasons for this cir- switch, the RTS bit in the UART (see Figure 8) must be
cuit are to convert from a TTL–level system to a 12V cleared to 0. This will cause a 0V level at the RTS pin of
system (5 volts on the gate of Q5 is not sufficient to turn the RS232 connector. The DTR bit in the Modem Con-
the transistor off if the voltage converter is running), to trol Register of the UART must be set to 1. If power is
avoid high voltage feedback from the voltage converter supplied from the outside, the status of DTR becomes a
through R5 to the TTL–level control input and to extend don’t care. In this case, D7 prevents driving the DTR line
the rise and fall time of the 12V programming pulse to with the external power supply.
the required minimum of 5 µs. High voltage feedback
from the 1–Wire bus to the receive input of the micropro- For reliable operation of this circuit, DTR must reach a
cessor is avoided by the diode D5, which becomes con- high level of 5V minimum. If this is not possible, an exter-
ducting only when the voltage on the 1–Wire bus is nal 5V supply must be connected as shown in Figure 12.
lower than 5V.
The function of the other components of this circuit has
The monolithic voltage converter IC1 requires L1, C2 already been explained in the section IV.C. RTS is
and D6 for operation. It is activated by a low level at its equivalent to PGMEN in Figure 11. D5 now prevents
TTL–compatible input SHDN. The right choice of L1, D6 feedback from the 1–Wire bus to the internal power sup-
and C2 is essential for reliable operation. D6 is a ply during the programming pulse. The duration of the
Schottky diode, recommended part number 1N5818, programming pulse (pulse width of RTS) cannot be con-
C2 is a low ESR tantalum capacitor of 10 µF. L1 must be trolled by the UART alone. Software to provide the cor-
a low ESR device between 20 to 100 µH, capable of rect timing is found later in this document.

102698 18/40
 APPLICATION NOTE 74

5V RS232 R/W ALL CIRCUIT Figure 12

L1
(SEE TEXT) D6
1N5818
3
SW
1 V VOUT 8
CC

C2
7 10 uF
SHDN
GND R5
47k
b c 4
U1 S
SHDN LT1109CN8–12
a G

+5V D Q5
C1 BSS110
(OPTIONAL) 150 pF
R4 D
R3 100k
100k G
D
G S Q4
Q3 2N7000
RTS 2N7000
D4 S
1N5242
12V

DTR
D7
ERA–82–004
R2 R1
4.7k 4.7k

RXD

D
S
Q2
2N7000
G
D5
D3 ERA–82–004
1N5242
12V
D

TXD G
D2
S Q1 1N5242
D1 2N7000 12V
1N5242
12V

GND

102698 19/40
 APPLICATION NOTE 74

V. CIRCUITS FOR 12V RS232 INTERFACES age arrives as a zero in the UART’s receive data regis-
(COM PORT) ter.
A. Read All
If equipment has a true RS232 port using current limited Probing the 1–Wire bus at the data contact and the
drivers with voltage capabilities of at least ±8V, then a 1–Wire ground with an oscilloscope, would show noth-
simple passive circuit is sufficient to interface to the ing unusual, except that the voltage swing is at the
1–Wire bus. Figure 13 shows all details; the waveforms upper end of the tolerable range. Probing RXD and TXD
are found on Figure 13a. This interface operates on the with another oscilloscope hooked up at the computer’s
same software as the circuit shown in Figure 10. The ground, would also reveal quite normal waveforms. The
waveforms at RXD and TXD with respect to the comput- only thing one might be concerned about is the poor neg-
er’s ground are basically the same. The major differ- ative voltage of about –2.3V found at RXD. Probing all
ence is that instead of 0V, a true negative voltage will be three signals (1–Wire bus, TXD, RXD) with one oscillo-
found, representing the idle state or a logic 1. Neglecting cope hooked up at the computer’s ground, would show a
absolute voltage levels, the waveform observed at RXD nearly constant voltage of 3.9V at the 1–Wire bus.
is essentially an inversion of the waveform that would be
observed on a 1–Wire data line for a 0V to 5V system. The positive voltage of approximately +4.1V at RXD is
well within the RS232–specification, the negative volt-
The ground potential of the computer is different from age is slightly out of specification. Since the total swing
the 1–Wire ground. This allows the iButton to experi- on the 1–Wire bus is limited to approximately 6V by the
ence typical voltage levels (0V to 6V) on the 1–Wire data characteristics of iButtons, a more negative voltage
line relative to the 1–Wire ground, while the serial port could be produced by replacing D1 by a zener diode of
generates both positive and negative voltages relative 3.2V, for example. Unfortunately, this would increase
to the serial port ground. D1 clamps the data line to a the permanent current load for DTR.
constant potential of nominally 3.9V. The time slots for
1–Wire communication are generated by changing the Fortunately, real RS232 receivers are more sensitive to a
potential of the 1–Wire ground with respect to the weak positive voltage than they are to a poor negative
1–Wire data line. The 1–Wire pullup resistor is in the voltage. Although it is not completely within the specifica-
path from the 1–Wire ground to TXD, which provides the tion of RS232, this interface with the components speci-
voltage for the 1–Wire bus. D2 limits the voltage swing fied on Figure 13 has proven to be reliable with most desk-
on the 1–Wire bus to a maximum value of 6.2 Volts. top personal computers. Small computers, especially
Since DTR is kept at 3.9V, D2 also limits the most nega- battery powered models, might not have the required cur-
tive voltage occurring at RXD to –2.3V. D2 is conducting rent capability to run this interface. In case of difficulties,
only when the voltage at TXD is negative with respect to one should use the 5V RS232 interface instead.
the computer’s ground. D3 limits the voltage between
1–Wire ground and 1–Wire data when the voltage at This interface is sold as COM Port Adapter DS9097. It is
TXD is positive. D4 couples TXD with RXD when TXD is applicable for reading all iButtons and writing to SRAM–
positive and bypasses R1 to provide a low resistance based devices. Due to the high pullup voltage and the
path to initiate a time slot on the 1–Wire bus. D4 is non- low pullup resistor, this interface together with the right
conducting when the voltage at TXD is negative with software also allows operation of the Temperature
respect to the computer’s ground. If an iButton pulls the iButton directly through the COM Port. Software to oper-
1–Wire data line low (e. g. at a presence pulse or when ate this interface is explained later in this document.
sending out a zero data bit), it shorts DTR to RXD,
resulting in a positive voltage at RXD. This positive volt- 12V RS232 READ ALL CIRCUIT Figure 13
DS9092
DTR TOUCH
PROBE

GND

RXD

TXD

102698 20/40
 MASTER TX MASTER RX
“RESET PULSE” MASTER WRITE “1” SLOT
MATER WRITE “0” SLOT MASTER READ “0” SLOT MASTER READ “1” SLOT
480 us
60 us
480 us “PRESENCE 60 us 15 us 15 us
PULSE” <15 us
VCC
1–WIRE
BUS
GND

3.9V TO PC–GROUND

DTR
12V RS232 READ ALL WAVEFORMS Figure 13a

PC–GND 0V AS REFERENCE

4.1V 3.9V 4.1V 4.1V 4.1V 3.9V 4.1V

RXD

=1–WIRE
GROUND –2.3V –2.3V –2.3V –2.3V –2.3V –2.3V

4.3V 4.3V 4.3V 4.3V 4.3V

TXD ST 1 2 3 4 ST 1 2 3 4 5 6
–12V –12V –12V –12V –12V

5 6 7 8 Stop Stop Start 1 2‘ 3 4 5 6 Stop Start 1 2 3 4 5 6 Stop Start 1 2 3 4 5 6 Stop

0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SEND F0 HEX
10473 BPS SEND 00 HEX SEND 3F HEX SEND 3F HEX SEND 3F HEX
8 DATA BITS ( 6 BITS)
NO PARITY, 1 STOP BIT
115200 BPS
6 DATA BITS

102698 21/40
APPLICATION NOTE 74

NO PARITY, 1 STOP BIT

 APPLICATION NOTE 74

B. R/W All ing the negative voltage from RTS through D7 to the
The simple adapter of Figure 13 can be upgraded for 1–Wire ground. As soon as the voltage on the 1–Wire
programming Add–Only Memories. Figure 14 shows bus reaches 12V, D6 will become active as voltage lim-
the details. R1 and the diodes D1 to D4 are the same in iter. Thus the voltage on RTS is limited to approximately
both circuits. There is a new signal in use, called RTS. –5.4V. During the programming pulse, the voltage at
When doing normal 1–Wire communication, RTS is RXD will be –5.2V instead of –2.3V. This has no impact
constantly at a high positive voltage of nominally +12V. on the logic of the UART, since a positive voltage is
As long as the voltage at RTS remains positive, Q1 and required to trigger the reception of a character.
Q2 are conducting. This allows D1 and D2 to provide the
same functions as in Figure 13. Since D1 and D2 are The COM–Port powered mode of this circuit works
conducting, there is not enough voltage across D5 and properly if the RS232–drivers are able to provide
D6 to draw any current. The gate–source voltage of Q3 enough current for programming. If more than one bit of
is determined by R2, R4, the voltage between DTR and the addressed memory byte need to be altered, then
RTS and the position of the contacts inside the connec- more current is needed during the programming pulse.
tor for the external DC supply. D7 prevents current flow Depending on the RS232 drivers, the available energy
from source to drain through the substrate diode of Q3 may not be sufficient for programming all bits of a byte.
when VDS is negative. If no external power supply is There are two possible solutions to this problem. One
connected, R2 and R4 form a voltage divider providing a possibility uses an adaptive programming algorithm,
negative VGS for Q3. With an external power supply where multiple passes are made for each byte. For
connected, R2 will hold the gate of Q3 at the same level example the software may program the first four bits of
as the source (VGS = 0V). None of these conditions will every byte on the first pass, and the remaining bits on
allow any current flow through Q3. With a positive volt- the second pass. The other possibility is to provide an
age at RTS, the p–channel transistor Q4 remains non– auxiliary energy source, i.e., by connecting an external
conducting, regardless if an external power supply is 12V DC supply.
connected or not. Thus the upgraded circuit behaves
the same as the simple COM–Port adapter. If the external supply is connected and operating, the
contacts inside the connector will open. This prevents
To generate a programming pulse for EPROM based any current flow through Q3. As the voltage at RTS goes
devices, RTS needs to be switched to a negative volt- negative, Q1, Q2, D5, D6 will do the same as without the
age. This is done under software control by simply clear- external supply. Instead of having no function, Q4 now
ing the associated control bit in the UART and resetting will connect the negative end of the external voltage
the bit as soon as the programming pulse needs to be source with the 1–Wire ground, providing the desired
ended. Depending on whether an external supply is low–impedance programming voltage. Since RTS has
connected or not, the behavior of this circuit is slightly no other load than the gates of four transistors, there will
different. be the full voltage swing. The voltages at RXD and TXD
are again determined by D5 and D6 and exhibit the
If there is no external supply, Q4 has no function and the same waveforms as before.
following sequence occurs (Figure 14a): A negative
voltage at RTS will switch off Q1 and Q2, activating D5 This upgraded version of a COM–Port adapter is
and D6 instead of D1 and D2. This increases the voltage shipped with the iButton Starter Kit DS9092K and is also
at DTR from 3.9V to 6.8V and defines a limit of 12V for available as the DS9097E. It is applicable for reading
the voltage on the 1–Wire bus. Simultaneously, the neg- and writing all iButtons. Due to the high pullup voltage
ative voltage at RTS will make VGS of Q3 equal to the and the low pullup resistor, this interface together with
voltage between DTR and RTS, which is a positive the right software allows operation of the Temperature
value. This will switch Q3 into a conducting state, feed- iButton directly through the COM Port.

102698 22/40
 NC

D
••••

GND
G –
+
RTS
S Q4
BSS84 +12V
R4
R2 39 OHM
1M OHM
12V RS232 R/W ALL CIRCUIT Figure 14

DS9092
iButton
DTR PROBE
D6
D1 MMBZ5242B
MMBZ5228B D2 12V
3.9V S
MMBZ5234B
6.2V G
D
6.8V D Q3
G D 2N7002
D5 G
MMBZ5235B S Q1
2N7002
S Q2
D3 2N7002 D7
RB400D RB400D
GND

RXD

R1 D4
1.5K OHM RB400D
PART NUMBERS ARE SPECIFIED
FOR SURFACE–MOUNT TECHNIQUE.

TXD

102698 23/40
APPLICATION NOTE 74
 APPLICATION NOTE 74

12V RS232 R/W ALL PROGRAMMING WAVEFORMS Figure 14a

12V 12V
RTS

–5.4V

3.9V (D1) 6.8V (D5) 3.9V (D1)

DTR

–2.3 (D2) –2.3 (D2)

RXD
–5.2V (D6)

–12V
TXD

12V (D6)

6.2V (D2) 6.2 (D2)

1–WIRE
BUS

VI. INTRINSICALLY SAFE writer is available, any updates to the iButton would
A. Definition have to occur outside of the hazardous area. Should it
iButtons satisfy a very high safety standard which be necessary to read or update the iButton within the
makes them well suited for applications in hazardous hazardous area (record the fuel dispensed, for exam-
environments. iButtons meet the UL#913 (4th Edit.) ple), a certified intrinsically safe reader/writer must be
requirements as Intrinsically Safe Apparatus, Approved used.
under the Entity Concept for use in Class I, Division 1,
Group A, B, C, and D Locations. Intrinsically safe means There are two options available to provide an intrinsi-
that the probability of causing an explosion or accident cally safe reader/writer. The first involves taking any
in hazardous locations is not increased when using piece of equipment capable of reading or writing
approved equipment, even if this equipment should be iButtons and submitting it to an approved NRTL (Nation-
faulty. Since iButtons have been certified as intrinsically ally Recognized Testing LAB) to be tested and certified
safe under the entity concept, they may reside in a haz- under the same entity concept as the iButtons. The
ardous environment but cannot be read or written in that second option takes advantage of reader/writer equip-
environment unless the unit performing the reading or ment that has already been tested and certified as intrin-
writing has also been certified as intrinsically safe under sically safe (laptop computer, handheld reader, etc.)
the same entity concept. and uses those test results along with a specially
designed iButton probe adapter to create an entire sys-
The iButton might be affixed to a tanker truck and con- tem that is intrinsically safe. One such unit utilizing this
tain maintenance information. The truck could enter and second option is the PSION Organizer II, Model LZ64.
exit a hazardous location (fuel depot, for example) with- This unit is used as an example to show how an intrinsi-
out concern over an increased potential for an explosion cally safe system can be realized.
due to the iButton device. If no intrinsically safe reader/

102698 24/40
 APPLICATION NOTE 74

B. Example of an Intrinsically Safe System The self–resetting fuse with a trip point below 100mA
To use the LZ64 as an intrinsically safe iButton Reader/ will open in less than one second and thus prevent ther-
Writer, an adapter is required. This adapter limits volt- mal damage to the transistors. It will also serve as an
ages and currents to safe values in the event a fault indicator to the operator that a fault or malfunction has
occurs. In the case of a fault, due to its internal construc- occurred.
tion, a maximum voltage of 17.22V at the 16–pin con-
nector of the LZ64 may occur allowing a current of up to Although this adapter is designed for use with the LZ64,
1.55A. The adapter discussed here limits these values it can be used with similar intrinsically safe equipment
at the iButton Probe to a maximum voltage of 15V and a with the same or lower faulted open–circuit voltage or
maximum current of 10mA (Values required by the short–circuit current to form an iButton Reader/Writer.
iButtons in order to be certified as intrinsically safe). This adapter does not impede writing to EPROM based
These values together with the maximum inductance of iButtons.
18 µH and maximum capacitance of 0.2nF of an iButton
fulfill the requirements for a complete system that is
intrinsically safe according to UL specifications. VII. COMMENTED SOFTWARE
A. Software Architectural Model
Figure 15 shows the complete circuit of the adapter. The software that manages data transfer to and from
Essential components are the four current shunts iButtons is related to the ISO reference model of Open
Q1/R1 to Q4/R4, three Zener diodes D2 to D4 and one System Interconnection (OSI). This model specifies a
self–resetting fuse SS1. The Schottky diode D1 is layered protocol having up to seven layers, denoted as
optional. It protects iButtons by suppressing negative Physical, Link, Network, Transport, Session, Presenta-
undershoots on the 1–Wire bus. tion, and Application. The Application layer represents
the final application designed by the customer. A Ses-
If by fault the LZ64 presents up to 17.22V at its connec- sion layer may or may not be needed, depending on the
tor and there is an open circuit at the iButton Probe, then environment in which the iButtons are used.
the 12V Zener diodes D2 to D4 will limit the voltage at
the iButton Probe to a value well below 15V. The intrinsi- According to the ISO model, the electrical and timing
cally–safe regulations demand that this limitation will requirements of iButton and the characteristics of the
work correctly even if two of the protecting devices 1–Wire bus comprise the Physical layer. Details have
should fail. Therefore three Zener diodes are provided already been given in section II of this document.
instead of one. If a Zener diode fails, it will either repre-
sent a short or it will be non–conducting. In either case, The Link layer defines the basic communication func-
the voltage at the iButton Probe is limited to a safe value. tions of iButtons, which are the hardware dependent
functions of Reset, Presence Detect and bit transfer.
If by fault the LZ64 presents up to 17.22V at its connec- Circuits for interfacing iButtons and general information
tor and there is a short at the iButton Probe, then a cur- on the software to operate these interfaces have
rent will flow through the resistors R1 to R4. The voltage already been presented in sections III, IV, and V. In this
drop across these resistors acts to turn on their respec- section, the software itself, specifically the functions
tive transistors and causes base currents to flow. These TouchReset and TouchByte, are discussed in detail.
base currents multiplied by the current gain of the tran-
sistors will direct most of the current to ground and limit The Network layer provides the identification of iButtons
the current at the iButton Probe to less than 10mA. Q1 and the associated network capabilities based on the
will sink most of the current. Two of these Q/R stages unique lasered identification number. Software for this
are required to limit the current available at the iButton layer is built up using the low–level functions of the Link
Probe under worst case conditions to less than 10 mA. Layer. Since this software is independent of any particu-
The other two current shunts are redundant since again lar interface, it is not within the scope of this document.
the circuit must operate correctly with up to two faults.

102698 25/40
102698 26/40
APPLICATION NOTE 74

DS9092
R1 R2 R3 R4 iButton PROBE
SS1 82 OHM 82 OHM 82 OHM 82 OHM
RXE–010 0.25W 5% 0.25W 5% 0.25W 5% 0.25W 5%

D4 D3 D2
D1 ERA–82–004
Q1 Q2 Q3 Q4 FUJI
TIP32A TIP32A TIP32A TIP32A SCHOTTKY

1 2
1516
16 PIN MALE
DUL–HEADER

D2, D3, D4 1N4742

PIN 9 GROUND MOTOROLA
PIN 12 DATA LINE 12V ZENER
INTRINSICALLY SAFE ADAPTER (EXAMPLE) Figure 15

PIN 14 POWER UP LINE

 APPLICATION NOTE 74

The Transport layer is responsible for the data transfer Software Developer’s Kit DS0621–SDK. For software
between the non–ROM segments of iButtons and the examples beyond the hardware dependent functions
master, and the data transfer from the scratchpad to the TouchReset, TouchByte and PulWidth, please refer to
final storage areas and special registers of the iButton. the “Book of DS19xx iButton Standards” and the iButton
Due to their EPROM technology, Add–Only Memories Starter Kit DS9092K.
require special attention for writing data. The Tempera-
ture iButton may require special hardware together with A matrix that indicates which software of this section
appropriate software to do a temperature measure- matches with which hardware is given in Table 3. For the
ment. To comply these devices, the hardware specific 5V TTL type interface, assembly language code for the
function PulWidth has been provided on the Transport 8051 has been provided. For the group of interfaces
layer. Details are given in this chapter. All other software based on the UART 8250, code examples in Pascal and
of the transport layer is independent of the type of inter- C are included. This particular software has been
face, and therefore is not discussed here. adapted to and verified with IBM–compatible PCs
employing a 8253 timer at 2.3863633 MHz and running
The layers Link, Network, and Transport are the founda- under DOS. The timing is practically independent of the
tions of the Presentation layer. This layer provides a CPU clock rate. Under WINDOWS there is a lot more
DOS–like file system supporting functions like Format, software being executed around an application pro-
Directory, Type, Copy, Delete, Optimize, and integrity gram. This overhead introduces a significant influence
check. Since the Presentation layer itself is based on from the CPU clock rate to the desired timing with the
software of the lower layers, its software is independent function PulWidth. The functions TouchReset and
of any particular interface. Full details of the Presenta- TouchByte are timed by the UART only and therefore
tion layer are given in the iButton TMEX Professional are independent of the operating system.

SOFTWARE/HARDWARE MATRIX Table 3

LANGUAGE 8051 ASM PASCAL AND C
TIMING CPU CRYSTAL 8250 UART (1.8 MHz) and
8253 TIMER (2.4 MHz)
Electric Type 5V TTL 5V RS232, 12V RS232

SRAM R/W TouchReset, TouchByte 1.8 or 11 MHz TouchReset and TouchByte Pascal or C–Lan-
EPROM Read guage
EPROM Write 0.5 ms pulsewidth: 0.5 ms pulsewidth:
PULWIDTH(1) at 1.8 MHz PULWIDTH(1193)
PULWIDTH(6) at 11 MHz under DOS

B. TTL–Interface R/W All the 1–Wire bus, TouchReset will return a set carry flag;
As a representative for all microprocessor timed 1–Wire otherwise carry is cleared. To send one byte to the
interfaces the industry–standard 8051 microcontroller 1–Wire bus, the byte to be sent is loaded into the accu-
has been chosen. The following pages show two ver- mulator before calling TouchByte. If one intends to read,
sions of assembly language code to provide the func- the accumulator is loaded with FFH. This generates cor-
tions TouchReset and TouchByte. The first example is rect Read Data Time Slots and returns data from the
written for an 11.0592 MHz crystal, the second one for 1–Wire bus to the calling program through the accumu-
1.8432 MHz. The higher frequency is very common lator. These conventions are valid for both versions of
since it supports all standard baud rates with the highest TouchReset and TouchByte.
accuracy. The lower frequency is the lowest that can
comply with the 1–Wire timing. The port to be used as The procedure to generate a programming pulse is the
1–Wire bus is defined in the parameter DATA_BIT. same for both clock frequencies. It generates a 0.5 ms
Parameter passing from the subroutines TouchReset LOW pulse at the port named PROGRAM. If the clock
and TouchByte is very simple: If an iButton is present on frequency is 1.8 MHz, then the accumulator needs to be

102698 27/40
 APPLICATION NOTE 74

loaded with 1 before calling this procedure. For a clock lished as soon as the device is available. Generally, it is
frequency of 11 MHz the value of 6 loaded into the accu- not a difficult task to adapt the procedure PulWidth to a
mulator will generate a pulse of the same duration. Soft- pulsewidth of 2 seconds.
ware considering the Temperature iButton will be pub-

8051 ASSEMBLY LANGUAGE, 11.0592 MHz

DATA_BIT BIT P0.0

; The following 8051 code uses a bi–directional port pin (specified by

; DATA_BIT) for 1–wire I/O. This code was written for an 11.0592 MHz
; crystal.
;
; Procedure TouchReset
;
; This procedure transmits the Reset signal to the
; iButton and watches for a presence pulse. On return,
; the Carry bit is set if a presence pulse was detected,
; otherwise the Carry is cleared. The code is timed for
; an 11.0592 MHz crystal.
;
TOUCHRESET:
PUSH B ; Save the B register.
PUSH ACC ; Save the accumulator.
MOV A, #4 ; Load outer loop variable.
CLR DATA_BIT ; Start the reset pulse.
MOV B, #221 ; 2. Set time interval.
DJNZ B, $ ; 442. Wait with Data low.
SETB DATA_BIT ; 1. Release Data line.
MOV B, #6 ; 2. Set time interval.
CLR C ; 1. Clear presence flag.
WAITLOW:
JB DATA_BIT, WH ; Exit loop if line high.
DJNZ B, WAITLOW ; Hang around for 3360
DJNZ ACC, WAITLOW ; us if line is low.
SJMP SHORT ; Line could not go high.
WH:
MOV B, #111 ; Delay for presence detect.
HL:
ORL C, /DATA_BIT ; 222. Catch presence pulse.
DJNZ B, HL ; 222. Wait with Data high.
SHORT:
POP ACC ; Restore accumulator.
POP B ; Restore B register.
RET ; Return.
;
; Procedure TouchByte
;
; The procedure TouchByte sends the byte in the accumulator
; to the iButton and simulatneously returns one
; byte from the iButton in the accumulator. Note that
; the NOPs in the following code are intended to give the

102698 28/40
 APPLICATION NOTE 74

; optimum performance when using a 11.0592 MHz crystal.

; Their purpose is to make the pulses as long as
; possible consistent with the iButton timing
; constraints. When using other crystal frequencies,
; the delays in this code should be adjusted to conform
; to the timing requirements of the iButton.
;
TOUCHBYTE:
PUSH B ; Save the B register.
MOV B, #8 ; Setup for 8 bits.
BIT_LOOP:
RRC A ; 1. Get bit in carry.
CALL TOUCHBIT ; 2. Send bit.
DJNZ B, BIT_LOOP ; 2. Get next bit.
RRC A ; Get final bit in ACC.
POP B ; Restore B register.
RET ; Return to caller.
TOUCHBIT:
CLR DATA_BIT ; 1. Start the time slot.
NOP ; 1. Delay to make sure
NOP ; 1. that the iButton
NOP ; 1. sees a low for at
NOP ; 1. least 1 microsecond.
MOV DATA_BIT, C ; 2. Send out the data bit.
NOP ; 1. Delay to give the
NOP ; 1. data returned from
NOP ; 1. the iButton
NOP ; 1. time to settle
NOP ; 1. before reading
NOP ; 1. the bit.
MOV C, DATA_BIT ; 1. Sample input data bit.
PUSH B ; 2. Save B register.
MOV B, #12H ; 2. Delay until the end
DJNZ B, $ ; 36. of the time slot.
POP B ; Restore B register.
SETB DATA_BIT ; Terminate time slot.
RET ; Return to caller.
;
END ; End of module._

8051 ASSEMBLY LANGUAGE, 1.8432 MHz

; iButton I/O Procedures for use with a 1.8432 MHz crystal.

TOUCHRESET:
CLR DATA_BIT ; – Pull the data line low.
MOV B, #35 ; 2 Hold the data line
DJNZ B, $ ; 70 low for 481.77
NOP ; 1 microseconds.
SETB DATA_BIT ; 1 Release the data line.
MOV B, #130 ; 2 Short circuit timeout.

102698 29/40
APPLICATION NOTE 74

CLR C ; 1 Presence pulse detector.

WAITLOW:
JB DATA_BIT, WAITHIGH ; 260 Go look for Presence pulse.
DJNZ B, WAITLOW ; 260 Abort on short circuit.
SJMP ABORT ; Short circuit (3.8877 ms).
WAITHIGH:
MOV B, #18 ; 2 Prepare for high period.
HL:
ORL C, /DATA_BIT ; 36 Trap the Presence pulse.
DJNZ B, HL ; 36 Wait out 481.77 microsec.
ABORT:
RET Return.
TOUCHBYTE:
MOV B, #8 ; Prepare to move 8 bits.
BIT_LOOP:
RRC A ; Move LSB to Carry.
JC SENDONE ; If Carry then send 1.
CLR DATA_BIT ; Otherwise send 0.
SJMP DELAYSET ; 2 Wait out rest of time slot.
SENDONE:
CLR DATA_BIT ; Start read/write 1 slot.
SETB DATA_BIT ; 1 Set data line.
MOV C, DATA_BIT ; 1 Read data line.
DELAYSET:
NOP ; 1 Delay 7 more cycles
NOP ; 1 to produce enough
NOP ; 1 delay to complete
NOP ; 1 the time slot.
NOP ; 1
NOP ; 1
NOP ; 1
SETB DATA_BIT ; 1 Done (65.1 microseconds).
DJNZ B, BIT_LOOP ; Repeat to send 8 bits.
RRC A ; Align final result.
RET ; Return.

8051 ASSEMBLY LANGUAGE PULSEWIDTH (1.8432 AND 11.0592 MHz)

PROGRAM BIT Pn.i
;
; This procedure generates a 0.5 ms low pulse on port
; Pn.i of an 8051 microprocessor, where 0 <= n <= 3
; and 0 <= i <= 7. The frequency of the crystal, in
; multiples of the minimum frequency 1.8432 MHz, must
; be passed in the accumulator.
;
PULWIDTH:
MOV B, #38 ; Number of loops at 1.8432 MHz.
MUL AB ; AB = # of loops given frequency.
INC B ; Adjust count value for
; use with DJNZ instruction.

102698 30/40
 APPLICATION NOTE 74

PUSH PSW ; Preserve state of interrupts.

CLR EA ; Inhibit all interrupts.
CLR PROGRAM ; Bring the port pin low.
LOOP:
DJNZ ACC, LOOP ; Count while
DJNZ B, LOOP ; pin is low.
SETB PROGRAM ; Bring the port pin high.
POP PSW ; Restore state of interrupts.
RET ; Return.

C. RS232 Interface R/W All sible to provide machine–independent software to

UARTs like the 8250 can be connected to any micropro- generate the programming pulse.
cessor to implement a RS232 type interface. The soft-
ware to operate the UART mainly consists of reading The most common computer using a 8250 type UART to
and writing the UART’s internal registers (Figure 8). This implement a RS232 interface is the IBM–compatible
can easily be done in any high level language. Depend- PC. These machines employ a programmable interval
ing on the computer, the physical address of the UART timer 8253 running at 2.3863633 MHz for general timing
will be different, but the crystal will usually be a 1.8432 purposes. This timer is involved in controlling the timing
MHz type. Not regarding the UART’s physical address, of the software examples of PulWidth. The pulsewidth is
the software examples for TouchReset and TouchByte specified by a formal parameter passed to PulWidth.
given on the following pages are very general. The lan- For 0.5 ms the value of this parameter is 1193 decimal.
guages C and Pascal are very common and a variety of Under DOS, the software examples given below will
compilers is available. perform accurately and almost independent of the CPU
clock. Due to a very different environment and use of
Unfortunately, the UART does not control the timing of resources under WINDOWS, the pulses will be longer
the signals DTR and RTS. It only allows activation or and also dependent on the CPU clock. This can be com-
deactivation of these signals by setting or clearing bits pensated for experimentally by reducing the value of the
inside its control registers. The timing itself is left to the parameter passed to PulWidth. Software considering
microprocessor and its peripheral timing circuits. From the Temperature iButton will be published as soon as
the software developer’s point of view this is a step the device is available. For the 5V–type RS232 interface
backwards to assembly language, where every com- a pulsewidth of 2 seconds will be required for the strong
mand and its execution time at a specified clock fre- pullup to 5V. The 12V RS232 interface has enough
quency need to be counted. For this reason it is not pos- power available to run one Temperature iButton without
extra power switching.

C LANGUAGE FOR UART 8250 SYSTEMS

/*
In the following C language code, 1–wire I/O is accomplished using the
serial port of an IBM PC or compatible. The serial port must be capable
of a 115,200 bps data rate. Setup must be called before any of the
touch functions to verify the existence of the specified com port and
initialize it.

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
The setup function makes sure that the com port number passed to it
is from 1 to 4 and has a valid address associated with it.
*/
uchar Setup(uchar CmPt)
{
uint far *ptr = (uint far *) 0x00400000;
uint SPA;

102698 31/40
APPLICATION NOTE 74

/* check to see if it is a valid com port number and address */

SPA = *(ptr+CmPt–1); /* get the address */
if (CmPt < 1 || CmPt > 4 || !SPA )
return FL;

/* serial port initialization */

outportb(SPA+3,0x83); /* set DLAB */
outportb(SPA ,0x01); /* bit rate is 115200 */
outportb(SPA+1,0x00);
outportb(SPA+3,0x03); /* 8 dta, 1 stp, no par */
outportb(SPA+1,0x00); /* no interrupts */
outportb(SPA+4,0x03); /* RTS and DTR on */

return TR;
}

/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
* Do a reset on the 1 wire port and return 0 no presence detect
* 1 presence pulse no alarm
* 2 alarm followed by presence
* 3 short circuit to ground
* 4 no com port found
*
* The global variable ’com_port’ must be set to the com port that the
* DS9097 COM Port Adapter is attached to before calling this routine.
*
*/
uchar TouchReset( void )
{
uint SPA,F,X,Y,tmp,trst=0;
uint far *ptr = (uint far *) 0x00400000;
ulong far *sysclk = (ulong far *) 0x0040006c;
ulong M;

/* get the serial port address */

SPA = *(ptr+com_port–1);

/* return if there is no address */

if (!SPA) return 4;

/* serial port initialization */

outportb(SPA+3,0x83); /* set DLAB */
outportb(SPA ,0x01); /* bit rate is 115200 */
outportb(SPA+1,0x00);
outportb(SPA+3,0x03); /* 8 dta, 1 stp, no par */
outportb(SPA+1,0x00); /* no interrupts */
outportb(SPA+4,0x03); /* RTS and DTR on */

/* Initialize the time limit */

M = *sysclk +1;

102698 32/40
 APPLICATION NOTE 74

/* loop to clear the buffers */

do { tmp = inportb(SPA+5) & 0x60; } while (tmp != 0x60);

/* flush input */
while (inportb(SPA+5) & 0x1) X = inportb(SPA);

outportb(SPA+3,0x83); /* set DLAB */

outportb(SPA+1,0x00); /* baud rate is 10473 */
outportb(SPA ,0x0B);
outportb(SPA+3,0x03); /* 8 dta, 1 stp, no par */
outportb(SPA ,0xF0); /* send the reset pulse */

/* wait until character back or timeout */

do
{
Y = inportb(SPA+5);
F = Y & 0x1;
} while ( !F && (*sysclk <= M) );

if (F) X = inportb(SPA);
else return 3;

if (X != 0xF0) /* if more bits back than sent then there */

{ /* is a device if framing error or break */
trst = TR;
if ( (Y & 0x18) != 0 )
{
trst = 2;

/* loop to clear the buffers */

do { tmp = inportb(SPA+5) & 0x60; } while (tmp != 0x60);

/* wait until character back or timeout */

do
{
Y = inportb(SPA+5);
F = Y & 0x1;
} while ( !F && (*sysclk <= M) );

if (F) X = inportb(SPA);
else return 3;
}
}

outportb(SPA+3,0x83); /* set DLAB */

outportb(SPA ,0x01); /* bit rate is 115200 */
outportb(SPA+3,0x03); /* 8 dta, 1 stp, no par */

return trst;
}

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APPLICATION NOTE 74

/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
* This is the 1–Wire routine ’TouchByte’, sometimes called ’DataByte’.
* It transmits 8 bits onto the 1–Wire data line and receives 8 bits
* concurrently. The global variable ’com_port’ must be set to the
* com port that the serial brick is attached to before calling this
* routine. This com port must also be set to 115200 baud, 8 dta, 1 stp,
* and no parity. This routine returns the uchar 8 bit value received.
* If it times out waiting for a character then 0xFF is returned.
*/
uchar TouchByte(uchar outch)
{
uchar inch=0,sendbit,Mask=1;
uint SPA;
uint far *ptr = (uint far *) 0x00400000;
ulong far *sysclk = (ulong far *) 0x0040006c;
ulong M;

/* get the serial port address */

SPA = *(ptr+com_port–1);

/* Initialize the time limit */

M = *sysclk +2;

/* wait to TBE and TSRE */

do {} while ( (inportb(SPA+5) & 0x60) != 0x60 );

/* flush input */
while ( (inportb(SPA+5) & 0x1) )
inportb(SPA);

/* get first bit ready to go out */

sendbit = (outch & 0x1) ? 0xFF : 0x00;

/* loop to send and receive 8 bits */

do
{
outportb(SPA,sendbit); /* send out the bit */

/* get next bit ready to go out */

Mask <<= 1;
sendbit = (outch & Mask) ? 0xFF : 0x00;

/* shift input char over ready for next bit */

inch >>= 1;

/* loop to look for the incoming bit */

for (;;)
{
/* return if out of time */
if ( *sysclk > M )
return 0xFF;

102698 34/40
 APPLICATION NOTE 74

if ( inportb(SPA+5) & 0x01 )

{
inch |= ((inportb(SPA) & 0x01) ? 0x80 : 0x00);
break;
}
}

} while (Mask);

return inch; /* return the input char */

}

C LANGUAGE PULSEWIDTH FOR SYSTEMS USING 8253 AND 8250

// standard include header file
#include <dos.h>

// function prototype
void PulWidth(unsigned int);

// global variable
int SPA;

//–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
// This procedure creates a fixed pulse width for programming that is
// approximately independent of system clock speed. X is in units of
// 0.419 microseconds for values greater than about 1000.
//
void PulWidth(unsigned int X)
{
unsigned int N,M;

disable(); // turn off interrupts

outportb(SPA+4,(inportb(SPA+4) & 0xFD)); // apply program pulse to rts
outportb(0x43,0); // freeze value in timer
M = inportb(0x40); // read value in timer
M |= (inportb(0x40) << 8);
do
{
outport(0x43,0); // freese value in timer
N = inportb(0x40); // read value in timer
N |= (inportb(0x40) << 8);
}
while (X > (M – N));

outportb(SPA+4,(inportb(SPA+4) | 0x02)); // remove program Voltage

enable(); // turn interrupts on
}

102698 35/40
APPLICATION NOTE 74

PASCAL LANGUAGE FOR UART 8250 SYSTEMS

{
In the following pascal code 1–wire I/O is accomplished using the
serial port of an IBM PC or compatible. The serial port must be capable
of a 115,200 bps data rate.
}
Const
SPA : Word = 0; { Currently active serial port address }

Function TouchReset(N: Byte): Boolean;

{
This function transmits the one–wire protocol reset sequence to
the device connected to COM port number N. This sequence consists
of a low pulse lasting a mimimum of 480 us followed by a high dead
time lasting a mimimum of 480 us. The function returns True if a
presence detect pulse occurs during the dead time, otherwise
it returns False.
}
Const
Init : Array[1..4] of Boolean = (True, True, True, True);

Var
S : Array[1..4] of Word Absolute $40:0;
T : LongInt Absolute $40:$6C;
M : LongInt;
F : Boolean;
X, Y : Byte;

Begin
SPA := 0; TouchReset := False; { Assume failure }
If (N > 0) and (N < 5) and (S[N] > 0) then Begin { Legal port # }
SPA := S[N]; { Save active serial port address }
If Init[N] then Begin { Serial port requires initialization }
Port[SPA +3] := $83; { Set the DLAB }
Port[SPA] := 1; { Bit rate is }
Port[SPA +1] := 0; { 115200 bps }
Port[SPA +3] := 3; { 8 dta, 1 stp, no par }
Port[SPA +1] := 0; { No interrupts }
Port[SPA +4] := 3; { RTS and DTR on }
Init[N] := False; { Initialization completed }
End;
M := T +1; { Initialize the time limit }
Repeat until Port[SPA +5] and $60 = $60; { Await TBE & TSRE }
While Odd(Port[SPA +5]) do X := Port[SPA]; { Flush input }
Port[SPA +3] := $83; { Set DLAB }
port[SPA+1] := 0; { Baud rate is 10473 }
Port[SPA] := 11;
Port[SPA +3] := 3; { 8 data, 1 stop, no parity }
Port[SPA] := $F0; { Send the reset pulse }
Repeat { Wait until character back or timeout }
Y := Port[SPA +5];
F := Odd(Y);

102698 36/40
 APPLICATION NOTE 74

until F or (T > M);

If F then X := Port[SPA] else X := $F0;
If (X <> $F0) Then Begin { If more bits back than sent }
TouchReset := True; { then there is a device }
If ((Y and $18) <> 0) Then Begin { Framing error or break }
Repeat until Port[SPA +5] and $60 = $60; { TBE & TSRE }
Repeat F := Odd(Port[SPA +5]) until F or (T > M);
If F then X := Port[SPA];
End;
End;
Port[SPA +3] := $83; { Set the DLAB }
Port[SPA] := 1; { Bit rate is 115200 bps }
Port[SPA +3] := 3; { 8 dta, 1 stp, no par }
End;
End;

Function TouchByte(X: Byte): Byte;

{
This function transmits the byte X to the device attached to the
currently active serial port SPA, and returns a byte from the
device as its value.
}
Var
T : LongInt Absolute $40:$6C;
M : LongInt;
I, J : Byte;
Begin
If SPA = 0 then TouchByte := X else Begin
M := T +1; { Initialize the time limit }
Repeat until Port[SPA +5] and $60 = $60; { Await TBE & TSRE }
While Odd(Port[SPA +5]) do I := Port[SPA]; { Flush input }
I := 0; J := 0; { Initialize output & input bit counters }
Repeat
If Odd(Port[SPA +5]) then Begin
Inc(J); If Odd(Port[SPA]) then X := X or $80;
End else If (I<=J) and (Port[SPA+5] and $20 = $20) then Begin
If Odd(X) then Port[SPA] := $FF else Port[SPA] := 0;
X := X shr 1; Inc(I);
End;
Until (J = 8) or (T > M);
While (J < 8) do Begin
X := X shr 1 or $80;
Inc(J)
End;
TouchByte := X;
End;
End;

102698 37/40
 APPLICATION NOTE 74

PASCAL LANGUAGE PULSEWIDTH FOR SYSTEMS USING 8253 AND 8250

Procedure PulWidth(X : Word);
{
This procedure creates a fixed pulse width for programming
that is approximately independent of system clock speed. When
used in an IBM PC or compatible computer operating under MS–
DOS, X is in units of 0.419 microseconds for values of X
greater than about 1000. The procedure can be used with any
processor having an 8250 UART I/O mapped to base port address
SPA and an 8253 timer mapped to base port address $40,
operating with an input clock of 2.386363 MHz and with its
count limit set to the maximum value.
}
Var
M, N : Word;
Begin
Inline($FA); {Turn off interrupts}
Port[SPA +4] := Port[SPA +4] and $FD; {Apply Program Pulse on RTS}
Port[$43] := 0; {Freeze value in timer}
M := Port[$40] shl 8 or Port[$40]; {Read value in timer}
Repeat {Loop to consume real time}
Port[$43] := 0; {Freeze value in timer again}
N := Port[$40] shl 8 or Port[$40]; {Read new value in timer}
Until M – N >= X; {See if ”X” usec have elapsed}
Port[SPA +4] := Port[SPA +4] or 2; {Remove Program Voltage}
Inline($FB); {Turn interrupts on}
End;

VIII. SUMMARY There are other possible circuit implementations to

This application note explains the hardware of different create a 1–Wire interface. The circuits described in this
types of 1–Wire interfaces and software examples application note cover many different configurations.
adapted to this hardware. Depending on the types of For a custom application, one of the described options
iButtons required for a project and the type of computer can be adapted to meet individual needs. The circuits
to be used, the most economic interface is easily found. can be used for reading and writing SRAM based
The hardware examples shown are basically two differ- iButtons, for individually programming EPROM based
ent types: 5V general interface and 12V RS232 inter- iButtons and for temperature measurement with the
face. Within the 5V group a common printed circuit DS1920 Temperature iButton. For programming large
board could be used for all four circuits. The variations quantities of EPROM based iButtons with the same data
can be achieved by different population of components (gang programming) commercial programmers are
(Table 4). The same principle is used for the 12V RS232 available from several independent companies. A list of
interface. The population determines if it is a Read all or vendors is available from Dallas Semiconductor on
a Read/Write all type of interface (Table 5). request.

102698 38/40
 APPLICATION NOTE 74

PARTS LIST FOR 5V SERIAL TO 1–WIRE PORT ADAPTERS (FOUR OPTIONS) Table 4
POSITION TTL READ ALL 5V RS232 RD ALL TTL RW ALL 5V RS232 RW ALL
C1 empty empty 10µ tantalum 10µ tantalum
C2 empty empty 150p, ceramic 150p, ceramic
D1 1N5242 (12V) 1N5242 (12V) 1N5242 (12V) 1N5242 (12V)
D2 1N5232 (5.6V) 1N5232 (5.6V) 1N5242 (12V) 1N5242 (12V)
D3 empty 1N5232 (5.6V) empty 1N5242 (12V) optional
D4 empty empty 1N5242 (12V) 1N5242 (12V)
D5 empty empty ERA–82–004 ERA–82–004
D6 empty empty 1N5818 1N5818
D7 short short empty ERA–82–004 optional
IC1 empty empty LT1109CN8–12 LT1109CN8–12
Q1 2N7000 2N7000 2N7000 2N7000
Q2 short GD 2N7000 short GD 2N7000
Q3 empty empty 2N7000 2N7000
Q4 empty empty 2N7000 2N7000
Q5 empty empty BSS110 BSS110
R1 4.7 kΩ 4.7 kΩ 4.7 kΩ 4.7 kΩ
R2 empty 4.7 kΩ empty 4.7 kΩ
R3 empty empty 100 kΩ 100 kΩ
R4 empty empty 100 kΩ 100 kΩ
R5 empty empty 47 kΩ 47 kΩ
L1 empty empty see text see text

102698 39/40
APPLICATION NOTE 74

PARTS LIST FOR 12V COM PORT TO 1–WIRE ADAPTERS (TWO OPTIONS) Table 5
POSITION READ ALL RW ALL
D1 empty 1N5228 (3.9V)
D2 empty 1N5234 (6.2V)
D3 ERA–82–004 ERA–82–004
D4 ERA–82–004 ERA–82–004
D5 1N5228 (3.9V) 1N5235 (6.8V)
D6 1N5234 (6.2V) 1N5242 (12V)
D7 empty ERA–82–004
Q1 empty 2N7000
Q2 empty 2N7000
Q3 empty 2N7000
Q4 empty BSS110
R1 1.5 kΩ 1.5 kΩ
R2 empty 1000 kΩ
R3 empty empty
R4 empty 39 Ω

102698 40/40