Service Manual: LCT TV

LCT TV
Service Manual
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Model: LCT-32CHSTP
Chassis: LS-08
Model No.: LCT-32CHSTP

Version: 1.0
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CONTENTS
MAIN FEATURE..................................................................................................................................... 4
MAIN ICS FUNCTION INTRODUCTION ............................................................................................ 8
SYMPTOMS AND CORRECTION ...................................................................................................... 46
LIST OF BREAKABLE AND MAINTENANCE PARTS .................................................................... 47
FACTORY MODE AND NOTICE ........................................................................................................ 49
CIRCUIT DIAGRAM ............................................................................................................................ 53
WIRING DIAGRAM ............................................................................................................................. 66
EXPLODED VIEW................................................................................................................................ 67
PART LIST ............................................................................................................................................. 68

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MAIN FEATURES
Radio Frequency input; support CATV

Capable to receive the full-append cable programs in 470MHZ
SCART input/output
SCART1can input CVBS/RGB Video format, SCART2 can input CVBS Video format, both can
output TV signal
AV input
Capable to receive PAL, NTSC, SECAM color systems; Very convenient to watch VCR (video
cassette recorder), Pickup Camera, other Disc’s programs
Y/C component signal input (same to S-Video input)
Convenient to receive the Y/C high definition component signal from DVD
HDTV input
Capable to receive the high definition YPbPr signal in 480i, 480p, 576i, 720p, 1080i, and 1080p
formats
VGA input
Convenient to connect with the host computer
Capable to use as the display terminal
Connect the 3.5mm(diameter) audio cord to your computer’s audio main board, you can listening
the beautiful music transmitted from your host computer
DVI input
Convenient to receive DVI signal
Teletext decoder
PIP, POP, PBP function
Turn on with intelligence
Zoom mode
LTI, CTI, and black field
BBE sound technology
Trusurround sound technology
Full-light display
Picture amending display function
Super definition display panel
3:2, 2:2 Pull Down
TV program scan function
Timer function
Automatically on/off in certain preset time, and transmit automatically to the fixed channel
Blue background noise reduction
In TV, AV (S-Video), YCbCr, and YPbPr modes, screen displays soft blue background if there is
no signal input

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Auto Off if no signal input

In TV mode, the LCD TV will automatically power off within 15 minutes and enter into the
Power Energy Saving Mode if there is no signal input.
Chinese/English menu
Ordinary and graphical user interface makes the menu operation more convenient and
intuitionistic
Power Energy Saving Mode (power management mode)
In PC mode, the LCD TV will automatically power off within 30 seconds and enter into the
Power Energy Saving Mode if there is no VGA signal input. It will automatically exit from the
Power Energy Saving Mode and work again when it received a valid VGA signal or press any
button on the panel/remote control.
Plug and Play
It is no need to equip any installation software when the product is used as computer terminal
display equipment
Legerity, convenience, low power consumption

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Unit IC Compositions：
LS08 chassis LCD TV is mainly composed of regulator IC, RF IC, video processor IC, Power
Amplify IC, Analog Video IC, System Control IC and Key Control IC, see this IC frame as below:

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PCB Assembly：
It is mainly composed of TV Board、Remote Control Receiver (Signal Receiver), K Board and Main
Board. Hereunder function introduction to every PCB Assembly:
No. Parts Description

1 Main Board It is the core of signal processing for LCD TV, which takes responsibility
Assembly of transforming outer signal into the uniform digital signal identified by
LCD display with use of System Control IC TV and AV signals input from
TV Board are decoded by UOCIII to transport RGB signal which is to be
transformed by TDA8759 modulus to transport 24bit RGB digital signal,
then it is to be transformed by GM1601/GM1501 to produce LVDS signal
displayed on the screen, in addition, signals input from VGA, DVI
would directly enter into GM1501 procedure, format transformation and
on screen display.
2 TV Board It is mainly composed of two tuners (main and sub tuners), AV/S, HD
Assembly signal terminals and some peripheral processing IC. The main tuner
demodulates RF signal to IF signal, and the sub tuner produces CVBS
signal, all signals are sent to the main board after transfer.
3 Remote Control It is composed of one indicator light and one remote control receiver,
Receiver which enable Users operate the TV conveniently and know its current
Assembly working status simply with a remote control.
4 Built-in Power It can transform AC 220V into DC for ICs, including +24V, +12V, +5V
Board Assembly and +5VS power supply in standby mode.
5 K Board It consists of 7 function buttons by which users can operate the TV freely.
Assembly
6 Screen Assembly Screens for LS08 have built-in adverse transformer, which change DC to
high voltage AC signal lightening the back light; The LCD screen is used
to display the image after the image signal has been processed by the
main board.

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MAIN ICS FUNCTION INTRODUCTION
GENERAL INTRODUCTION
TV Board
Number Location Type Main Function
1 UT1 TAD5-E2I22RW2 Audio and image intermediate frequency
signal output
2 UT2 TMD2-E49IPWA Sub picture CVBS signal output
Main Board
3 U302, U303 24LC21A T/SN EEPROM
4 U701 24LC32A T/SN Buffer
5 U306, U307, FSAV330QSCX Switch selection
UA3
6 K201 K3953M Audio surface filter
7 K202 K9656M Audio surface filter
8 U6 TPA3002D2PHPR Audio amplifier
9 U801 AM29LV800DT-70EC Flash，control program inside
10 U700 GM1501-BD Video processor
11 U201 TDA15021H/N1B07 AV decoder
12 U402 SAA7115HL/V1 Sub channel video decoder
13 U305 SM5302AS-G-ET High definition signal filter
14 U400 TDA8759HV/8/C1 Video signal modulus transformer
15 U5 TDA9178T/N1 Video signal picture amendment
16 U600 MT46V2M32LG-4 Frame buffer

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ICs FUNCTION INTRODUCTION IN DETAILS

Main Tuner (TAD5-E2122RW2)
Pin Definition Description
1 AGC Auto gain control
2 UT NC
3 ADD Ground
4 SCL IIC bus (Clock)
5 SDA IIC bus (Data)
6 NC NC
7 +5V Power supply
8 NC NC
9 30V To produce 0~30V tune voltage
10 NC NC
11 IF Intermediate frequency TV signal
Intermediate frequency TV signal
Sub Tuner (TMD2-E49IPIWA):

Pin Definition Description
2 NC NC
3 ADD Ground
4 SCL IIC bus (Clock)
5 SDA IIC bus (Data)
6 NC NC
7 +5V Power supply
8 NC NC
9 33V To produce 0~30V tune voltage to 0~30V
10 NC NC
11 IF Intermediate frequency output (NC)
12 IF Intermediate frequency output (NC)
13 SW0 Band control
14 SW1 Band control
15 NC NC
16 SIF NC
18 VEDIO CVBS signal output
19 +5V Power supply
20 AUDIO NC

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GM1501
GM1501is a kind of processing chassis for dual channels image and video, which is mainly used for
LCD displays and integrative TV products. With the resolution of WUXGA, it not only supports PIP
technique, but possesses some IC functions applied to image catch, process and clock display. It
integrates high velocity AD converter, PLL, high reliability DVI receiver, X86 series mic control and
LCDS inverter. See the features as below:
Features
High quality image zoom function
Analog RGB signal input interface
Intelligent output signal auto identification
Integrated high-power PLL output
High-reliable self-adaptive DVI input interface
4:4:4/4:2:2/CCR656/601 8/16/24bit digital video interface
Embedded IC for adjustments of gain, contrast, brightness, color saturation, hue and flesh tone.
Efficiency in reducing EMI electromagnetism inference power consumption
Inclined grain processing with small angle
High quality video processing
Programmable output format
Embedded LVDS transport
Advanced OSD
Embedded micro controller

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Pin Description：
Pin Name Description

Analog signal input port
L3 AVSYNC ADC vertical synchronization signal input
L4 AHSYNC ADC horizontal synchronization signal
input
N2 VGA-SCL VGA lock input
N1 VGA-SDA VGA digital input
D1, D2 RED+, RED- Red analog signal input
C3 SOG Green synchronization signal
C1, C2 GREEN+, - Green analog signal input
B1, B2 BLUE+, BLUE- Blue analog signal input
A2, B3, E3, D3 ADC3.3 ADC3.3Vpower supply
A3, A4 ADC1.8 ADC1.8Vpower supply
A5, B4 ADC-DGND ADC digital ground
C4, D4, E1, E2, E4 ADC-AGND ADC analog ground
DVI input port
N4 DVI-SCL DDC interface , serial clock signal
N3 DVI-SDA DDC interface ，serial data signal
A6, B6 RXC+，RXC- DVI clock input signal
A8～A10 RX0+～RX2+ DVI input port
B8～B10 RX0-～RX2-
B11 REXT Exterior cut-off resistance
C6～C11 DVI-3.3 DVI 3.3V power supply
D6, D8～D10 DVI-1.8 DVI 1.8V power supply
A7, A11, B5, B7, C7, DVI-GND DVI ground
D7, D11
Low bandwidth ADC port
C13 LBADC-33 ADC3.3Vpower supply
A12, B12, C12 LBADC_IN1～ ADC analog input channel
LBADC_IN3
D12 LBADC_RETURN Channel analog ground
D13 LBADC-GND Power supply voltage analog ground
OCM bus port
AA1~AA3, Y1~Y3, OCMADDR0～ Address input output port
W1~W3, V1~V4, OCMADDR19
U1~U4, T1~T3

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AB1~AB3, AC1~AC3, OCMDATA0~ Data input output port

AD1~AD4, AE1~AE3, OCMDATA15
AF1~AF3
OCM port control signal
R1, T4, P1, P2 ROM_CSn~ Part selection signal
ROM_CS2n
R2 OCM_REn Read enable signal
R3 OCM_WEn Write enable signal
L1 OCM_INT2 Interrupt
L2 OCM_INT1
M1 OCM_UDO OCM data output
M2 OCM_UDI OCM data input
D25 OCM_TIMER1 OCM timer input
Standard definition video control port
D16 SVCLK SV pels clock input
C14 SVHSYNC SV horizontal synchronization signal input
B14 SVVSYNC SV vertical synchronization signal input
A14 SVODD Scan status input
A17 SVDV SV data input
Standard definition video data port
D14, D15, A15, A16, SVDATA7~ SV ITU656 data input
B15, B16, C15, C16 SVDATA0
Video Control Port
A20 VCLK Video pels clock signal
D19 VHS_CSYNC Video horizontal synchronization signal
input
C20 VVS Video vertical synchronization signal input
B20 VODD Scan status input
D20 VDV (VSOG) Video data input
B17 VCLAMP Video clamp enable output
A21, A22, A23, B21, VGRN7~ VGRN0 Green signal or Y signal input
B22, C21, C22, D21
C17, C18, C19, A18 VRED7~ VRED0 Red signal or V/Cr/Pr signal input
A19, B18, B19, D18
B23, B24, B25, A24 VBLU7~ VBLU0 Blue signal or U/Cb/Pb signal input
A25, C23, C24, D24
Screen Control Port
A26 PPWR Screen power control
B26 PBIAS Screen bias control

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D26, C25, C26 PWM2 ~PWM0 Pulse width modulation output

AC7 DCLK Pels clock output
AC16 OEXTR Connect external LVDS bias resistance
LVDS Port
AE14~AE16, AE19~ A0-~A3-, A0+~A3+ Low voltage difference data input
AE23, AF13~AF16 B0-~B3-, B0+~B3+
AF19~AF23, AF11
AD14, AD11, AE13 LVDS_SHIELD [5] ~ Low voltage difference protect output
AE11, AC11, AF10 LVDS_SHIELD [0]
AE12, AF12, AC+,AC-,BC+,BC- Low voltage difference protect input
AF20, AE20
Screen Port Power Supply
AD12, AD13, AC12 LVDSB_3.3 LVDS B channel power supply
AC13, AC14, AC15 LVDSB_GND B channel ground
AC20, AC21, AC22 LVDSA_3.3 LVDS A channel power supply
AD19, AC19, AC20 LVDSA_GND A channel ground
AE17 VDDD33_LVDS Analog power supply
AD17 VSSD33_LVDS Analog ground
Clock Composite and Power Supply
G4 XTAL Crystal oscillator interface
F2 VDDD33_PLL， Digital power supply
H1 VDDD33_SDDS
J1 VDDD33_DDDS
G2 VSSD33_PLL Digital ground
J4 VSSD33_SDDS
K4 VSSD33_DDDS
F4 VDDA33_RPLL Analog power supply
G1 VDDA33_FPLL
H3 VDDA33_SDDS
J3 VDDA33_DDDS
F3 VSSA33_RPLL Analog ground
H4 VSSA33_FPLL
H2 VSSA33_DDDS
J2 VSSA33_DDDS
G3 TCLK Reference clock signal input
K2 ACS_RSET_HD External resistance port

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System Signal
K1 RESETn Reset signal
M3, M4 IR0，IR1
P4 MSTR_SCL Main clock output signal
P3 MSTR_SDA Main data output/input signal
R4 EXTCLK External clock input
Frame Memorizer Interface

U24, U23 FSCLKp, FSCLKn Fine storage clock output
V24, V25 FSRAS, FSCAS Address output
V26 FSWE Write enable port
W26 FSCKE Read enable port
J24 FSVREF Reference voltage input
K26 FSVREFVSS Reference voltage ground
W25 FSVREF Reference voltage input
W24 FSVREFVSS Reference voltage ground
L26 FSDQS Data filter
F24~F26, G23~G26 FSDATA31~ FSDATA0 Data input output port
H24~H26, J25, J26,
R24~R26, P24~P26
N23~N26,
T24, T25, U25, U26 FSDQM3~ FSDQM0 Data output mark
Y26 FSBKSEL1，FSBKSEL0 Layer address
Y25
AA24~AA26 FSADDR11~ Range address output
AB24~AB26, FSADDR0
AC24~AC26
AD24~AD26
E23, F23, H23, J23, FS_2.5 2.5V power supply
L23, M23, P23, R23,
T23, V23, W23, Y23,
AA23, AB23, AC23
K23 VDDA18_DLL 1.8V power supply
K25 VSSA18_DLL Power supply ground
Digital power supply
K10, K11, K16, K17, CORE_1.8 1.8V power supply
L11, L16, T11, T16,
T17, U10, U11, U16,
U17

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D23, W4, Y4, AA4, IO_3.3 3.3V power supply

AB4, AC4, AC6, D17,
D22, AC8, AC10
K12, K13, K14, K15, D_GND Power ground
L10, L12, L13, L14,
L15, L17, M10, M11,
M12, M13
A1, AC, D5, AC17, NO_CONNECT NC
K3, F1

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GM1501Internal Block Diagram：

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TDA8759:
TDA8759 is a triple 8-bit video converter interface. The IC converts a RGB analog signal into a 24bit
RGB or YUV or YCbCr digital signal or converts a YUV or YCbCr analog signal into a YUV or RGB
digital signal with a sampling rate up to 81 Msps. The IC supports resolutions from 480i and VGA to
HDTV and XGA.
Features
Triple 8-bit Analog-to-Digital Converter (ADC)
Three independent analog video sources up to 81 Msps selectable by I2C-bus
Auto check on interval scan video signal
1.8Vand 3.3Vsupplies
Low gain variation with temperature
Output format RGB 4:4:4, YUV 4:4:4, YUV 4:2:2, CCIR 656 or YUV 4:2:2 semi-planar standard
on output bus
I²C bus control
Programmable clock phase adjustment cells
Amplifier bandwidth of 100 MHz
Integrated PLL divider
Power-Down mode

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TDA8759 Block Diagram

Version: 1.0
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Pin Description:

1 HREF Horizontal reference output
2 VCLK Video clock output
3, 13, 21, 29, VDDO Video port output supply voltage
37, 45, 164
4, 14, 22, 30 OGND Video port output
38, 46, 165 ground
7, 8, 9, 10, 15, 16, VPA0~VPA7 Video port A
17, 18
11, 116, 130, 132 VDDC Power supply port
12, 117, 159 CGND Ground
23~28, 31, 32 VPB0~VPB7 Video port B
35, 36, 39~44 VPC0~VPC7 Video port C
47, 53, 57, 58, 55 AGND Analog ground
60, 66, 70, 71, 75
81, 83, 85, 86,
48, 54, 59, 61, 67 VDDA Power supply port
69, 76, 82, 85, 87,
88
49 REFB/Pb Blue/blue-chrominance channel reference input
52, 51, 50 B/Pb1~ B/Pb3 Blue/blue-chrominance channel analog input
56 BIAS Bias input
62 REFG/Y Green/green-chrominance channel reference input
65,64,63 G/Y1~G/Y3 Green/green-chrominance channel analog input
74,73,72 SOG/Y1~SOG/Y3 Sync on green//brightness channel input
77 REFR/Pr Red/red-chrominance channel reference input
80,79,78 R/Pr1~ R/Pr3 Red/red-chrominance channel analog input
89~92,97~101 TST0~TST17 Reserved for test
112,121,122,
124,125,160~163
93 PD Power-down control input
94 OE Output enable input
96 A0 I²C bus address control input
102 COAST PLL control input
103 GAIN Gain input
104 CLAMP Clamp input

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105~107 VSYNC1~VSYNC3 Vertical synchronization input

108~110 H(C)SYNC1~ Horizontal (composite) synchronization input
H(C)SYNC3
111 CKEXT External clock input
113 TCLK Reserved for test
114 DIS I²C bus disable control input
118 SDA I²C bus data input/output
119 SCL I²C bus clock input
120, 126, 127, 131 IGND Input digital ground
133, 142, 148,
123, 138, 139, 145 VDDI Input digital supply voltage
151, 157
166 PL PLL disable output
167 DE Data enable output
168 HS Horizontal synchronization input
169 VS Vertical synchronization input
170 CS Color synchronization output
171 ORR/V Red / chrominance ADCoutput
172 ORB/U Blue /chrominance ADCoutput
173 ORG/Y Green / chrominance ADCoutput
174 VAI Video dynamic indication output
175 FREF Scan output
17 VREF Vertical channel reference input
TPA3002D2:
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied
stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8. The high efficiency of the
TPA3002D2 eliminates the need for external heat sinks when playing music.
Features:
9W /Ch into an 8Ω load from 12Vsupply;
Efficient, class D operation eliminates heat sinks and reduces power supply requirements;
32-step DC volume control from -40db~36db;
Line outputs for external headphone;
Thermal and short-circuit protection

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Pins Functions：

26, 30 AGND Analog ground for digital/analog cells in core
33 AVCC High-voltage analog power supply（8~14V）
29 AVDD 5V regulated output capable of 100mA output
7 AVDDREF Reference 5V output
13 BSLN Bootstrap I/O left channel
24 BSLP
48 BSRN Bootstrap I/O right channel
37 BSRP
28 COSC I/O for charge/discharge currents onto capacitor for ramp generator
triangle
6 LINN Negative differential audio input for left channel
5 LINP Positive differential audio input for left channel
16，17 LOUTN Class-D 1/2-H-bridge negative output for left channel

20，21 LOUTP Class-D 1/2-H-bridge positive output for left channel
34 MODE Input for MODE control. A logic high on this pin places the
amplifier in the variable output mode and the Class-D outputs are
disabled. A logic low on this pin places the amplifier in the
Class-D mode and Class-D stereo outputs are enabled. Variable
outputs (VAROUTL and VAROUTR) are still enabled in Class-D
mode to be used as line-level outputs for external amplifiers.
35 MODE_OUT Output for control of the variable output amplifiers. When the
MODE pin (34) is a logic high, the MODE_OUT pin is driven
low. When the MODE pin (34) is a logic low, the MODE_OUT
pin is driven high. This pin is intended for MUTE control of an
external headphone amplifier. Leave unconnected when not used
for headphone amplifier control.
18,19,42, PGNDR, PGNDL Power ground for left channel H-bridge Power ground for right
43 channel H-bridge
14,15,22, PVCCL Power supply for left channel H-bridge (tied to pins 22 and 23
23 internally), not connected to PVCCR or AVCC.
38,39,46, PVCCR PVCCL 22, 23 – Power supply for left channel H-bridge (tied to
47 pins 14 and 15 internally), not connected to PVCCR or AVCC.
PVCCR 38,39 – Power supply for right channel H-bridge (tied to
pins 46 and 47 internally), not connected to PVCCL or AVCC.
PVCCR 46, 47 – Power supply for right channel H-bridge (tied to
pins 38 and 39 internally), not connected to PVCCL or AVCC.

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12 REFGND Ground for gain control circuitry. Connect to AGND. If using a

DAC to control the volume, connect the DAC ground to this
terminal.
32 RINP Positive differential audio input for right channel
2 RINN Negative differential audio input for right channel
27 ROSC Current setting resistor for ramp generator. Nominally equal to
1/8*
44, 45, ROUTN, ROUTP Class-D 1/2-H-bridge negative output for right channel
40, 41 ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right
channel
1 SD Shutdown signal for IC (low = shutdown, high = operational).
TTL logic levels with compliance to VCC.
9 VARDIFF DC voltage to set the difference in gain between the Class-D and
VAROUT outputs. Connect to GND or AVDDREF if VAROUT
outputs are unconnected.
10 VARMAX DC voltage that sets the maximum gain for the VAROUT outputs.
Connect to GND or AVDDREF if VAROUT outputs are
unconnected.
31 VAROUTL Variable output for left channel audio. Line level output for
driving external HP amplifier.
32 VAROUTR VAROUTR 32 O Variable output for right channel audio. Line
level output for driving external HP amplifier.
25 VCLAMPL VCLAMPL 25 – Internally generated voltage supply for left
channel bootstrap capacitors.
36 VCLAMPR Internally generated voltage supply for right channel bootstrap
capacitors.
11 VOLUME DC voltage that sets the gain of the Class-D and VAROUT
outputs.
8 VREF Analog reference for gain control section.
4 V2P5 2.5-V Reference for analog cells, as well as reference for unused
audio input when using single-ended inputs.

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TPA3002D2 External Block Diagram：

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SM5301AS:
Order Butterworth low pass filter configuration. The filter characteristics have been optimized for
minimal overshoot and flat group delay, it has a variable cutoff frequency and guaranteed driver-stage
channel gain difference and phase difference values.
Features:
Supply voltage：5V±10%；
DC voltage level restore sync clamp function
Output buffer gain switching function: 0, 6dB (input-to-output AC signal gain)
Channel-to-channel gain difference: 0.5dB(±5% supply voltage variation)
Channel-to-channel phase difference: 3.5 degree
Output signal harmonic distortion (all channels): 1.5%
Cutoff frequency: 5.8 to 37MHz variable
SM5301AS Internal Block Diagram：

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Pin Description:

2 GSG1 GOUT/UOUT output buffer gain set input
1 GINA/UINA Analog GINA or UINA signal input. Sync signal is input on
3 GINB/UINB SYNCIN pin.
Analog GINB or UINB signal input. Sync signal is input on
SYNCIN pin.
5 BINA/VINA Analog BINA or VINA signal input. Sync signal is input on
7 BINB/VINB SYNCIN pin.
Analog BINB or VINB signal input. Sync signal is input on
SYNCIN pin
6 GSB1 BOUT/VOUT output buffer gain set input
9 DISABLE Power save function. Built-in pull-down resistor.
10, 13, 16, 19 GND Ground

11 BOUT/VOUT B/V signal output
14 GOUT/UOUT Analog 5V supply
17 ROUT/YINB R/Y signal output
12, 15, 18, 24 VCC Analog 5V supply

20 RFC LPF (low pass filter) cutoff frequency setting resistor connection
21 VFC LPF (low pass filter) cutoff frequency setting voltage input
22 MUXSEL Input select signal

23 SYNCIN Filter channel external H-Sync signal input.
26 GSR1 ROUT/YOUT output buffer gain set input
25 RINA/YINA Analog RINA or YINA signal input. Sync signal is input on
27 RINB/YINB SYNCIN pin.
Analog RINB or YINB signal input. Sync signal is input on
SYNCIN pin.
4, 8, 28 NC No connection (leave open or connect to ground)

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SAA7115:
The SAA7115 is a video capture device for various applications ranging from small screen products
like e.g. digital set top boxes, personal video recording applications to big screen devices like e.g. LCD
projectors due to it’s improved comb filter performance and 10 bit video output capabilities.
Features
Six analog inputs, internal analog source selectors;
Two improved 9 Bit CMOS analog-to-digital converter in differential CMOS style;
Automatic Clamp Control (ACC) for CVBS, Y and C;
Enhanced Horizontal and vertical Sync Detection;
PAL delay line for correcting PAL phase errors;
Automatic TV/VCR detection; TV/VCR

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SAA7115 Internal Diagram:

Version: 1.0
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Pin Function：

1,8,11,17,23,25,33 VDD Supply voltage port
43,51,58,68,75,83
93
2 TDO Test Data Output for Boundary Scan Test (2)
3 TDI Test Data Input for Boundary Scan Test (with internal
pull-up)(2)
4 XTOUT Crystal oscillator output signal, auxiliary signal
6 XTALO 24.576 (32.11) MHz crystal oscillator output; not connected if
7 XTALI XTALI is driven by an external single-ended oscillator.
Input terminal for 24.576 (32.11) MHz crystal oscillator or
connection of external oscillator with TTL compatible square
wave clock signal.
6 VXDD Crystal oscillator power supply
10,12,14,16 AI21~AI24 Analog signal input
13 AI2D Differential input for ADC channel 2 (pins AI24, AI23, AI22,
19 AI1D AI21) differential input for ADC channel 1 (pins AI12, AI11)
20 AI11 Analog input 11
18 AI12 Analog input 12
5,9,15,21,24,26,38 AGND Ground
50,63,76,88,100 VSS
22 AOUT Analog test output (do not connect)
27 CE Chip Enable or RESET input (with internal pull up)
28 LLC Line-locked system clock output (27 MHz nominal), for
backward compatibility, do not use for new applications
29 LLC2 line locked clock/2 output (13.5 MHz nominal) for backward
compatibility, do not use for new applications
30 RESON RESet Output Not signal
31 SCL IIC serial clock line (with inactive output path)
32 SDA IIC serial data line
34 RTS0 Real time status or sync information, controlled by subaddr. “11h
and 12h” RTS1 35 O real time status or sync information,
35 RTS1
controlled by subaddr. “11h and 12h”
36 RTCO Real time control output
37 AMCLK Audio master clock output
39 ASCLK Audio serial clock output

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40 ALRCLK Audio lift/right clock output

41 AMXCLK Audio master external clock input
42 ITRDY Target ready input, image port (with internal pull up)
45 ICLK Clock output signal for image-port, LCLK of LPB image port
mode, or optional asynchrony backend clock input
46 IDQ Output data qualifier for image port (optional: gated clock
output)
47 ITRI Image-port output control signal, effects all I-port pins incl.
ICLK, enable and active polarity is under software control (bits
IPE in subaddr. “87”) output path used for Testing: scan output
48 IGP0 General purpose output signal 0; image-port (controlled by
49 IGP1 subaddr. “84”,”85”)
General purpose output signal 1; image-port (controlled by
subaddr. “84”,”85”),
same functions as IGP0
52 IGPV Multi purpose vertical reference output signal; image-port
(controlled by subaddr. “84”,”85”)
53 IGPH Multi purpose horizontal reference output signal; image-port
(controlled by subaddr. “84”,”85”)
54~57,59~62 IPD0~IPD7 Image port data output
64~67,69~72 HPD0~HPD Host port data I/O, carries UV chrominance information in 16 bit
7 video I/O modes
80 XTRI X-port output control signal, effects all X-port pins (XPD[7:0],
XRH, XRV, XDQ and XCLK) enable and active polarity is
under software control (bits XPE in subaddr. “83”)
81,82,84,85, XPD0~XPD expansion-port data
89,90,86,87 7 expansion-port data
91 XRV vertical reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit
0.
92 XRH horizontal reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit
1.
94 XCLK clock I/O expansion port
95 XDQ data qualifier I/O expansion port
96 XRDY task flag or read signal from scaler, controlled by XRQT
(subaddr. 83H)

Version: 1.0
-30 -
97 TRSTN Test ReSeT Not for Boundary Scan Test (with internal pull-up);
for board design without Boundary Scan connect TRSTN to
‘ground’ (1)
98 TCK Test Clock for Boundary Scan Test (with internal pull-up) (2)
99 TMS Test Mode Select for Boundary Scan Test or Scan Test (with
internal pull-up) (2)
UOC (TDA15021h):
The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH
embedded TEXT/Control/Graphics -Controller (TCG -Controller) and US Closed Caption decoder.
Features
DVB/VSB IF circuit for preprocessing of digital TV signals;
Video switch with 3 external CVBS inputs and a CVBS output;
Automatic Y/C signal detector;
Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the
chrominance signal;
Picture improvement features with peaking (with switchable center frequency, depeaking, variable
positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic
skin tone control, gamma control and blue and black stretching. All features are available for
CVBS, Y/C and RGB/YPBPR signals.
The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to
the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that
the external band-pass filters can be omitted. In the stereo versions of UOCIII the use of this
demodulator is optional for special applications.
Normally the FM demodulators of the stereo demodulator/decoder part are used (see below).
The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second
sound channel can be demodulated. In such an application it is necessary that an external band pass
filter is inserted.
The vision IF and mono intercarrier sound circuit can be used for the demodulation of FM radio
signals. With an external FM tuner also signals with an IF frequency of 10.7 MHz can be
demodulated. For the QIP90 versions this is valid only for the “stereo” versions
Built-in adaptable brightness delay circuit
Switch able brightness signal transmission rate

Version: 1.0
-31 -
Pin Description：

1,2,12,18,28,40 VSS, GND Ground
68,81,89,92,95,101
121,125
3,4,45,69,82,88,90, VDD Power supply
91,93,94,96,100,
110,117,118,124
5 VREF_POS_LSL SDAC input signal
6 VREF_NEG_LSL+HPL
7 VREF_POS_LSR+HPR
8 VREF_NEG_HPL+HPR
9 VREF_POS_HPR
10 XTALIN Crystal oscillator input
11 XTALOUT Crystal oscillator output
13 VGUARD/SWIO V-guard input / I/O switch
14 DECDIG decoupling digital supply
15 VP1 decoupling digital supply
16 PH2LF phase-2 filter
17 PH1LF phase-1 filter
19 SECPLL SECAM PLL decoupling
20 DECBG bandgap decoupling
21 EWD/AVL East-West drive output or AVL capacitor
22 VDRB vertical drive B output
23 VDRA vertical drive A output
24 VIFIN1 IF input 1
25 VIFIN2 IF input 2
27 IREF reference current input
29 SIFIN1/DVBIN1 SIF input 1 / DVB input 1
30 SIFIN2/DVBIN2
31 AGCOUT tuner AGC output
32 EHTO EHT / overvoltage protection input
33 AVL/SWO/SSIF/REFO/ Automatic Volume Levelling / switch output
REFIN reference output / external reference signal DVB
operation
34 AUDIOIN5L audio-5 input (left signal)
35 AUDIOIN5R audio-5 input (right signal)

Version: 1.0
-32 -

36 AUDOUTSL audio output for SCART/CINCH (left signal)
37 AUDOUTSR audio output for SCART/CINCH (right signal)
SCART
38 DECSDEM decoupling sound demodulator
39 QSSO/AMOUT/AUDEE QSS intercarrier output / AM output / deemphasis
M QSS
41 PLLIF PLL filter
42 SIFAGC/DVBAGC AGC sound IF / internal-external AGC for DVB
applications
43 DVBO/IFVO/FMRO Digital Video Broadcast output / IF video output
44 DVBO/FMRO
46 AGC2SIF AGC capacitor second sound IF
47 VP2 2nd supply voltage TV processor (+5 V)
48 IFVO/SVO/CVBSI video output / selected CVBS output / CVBS
49 AUDIOIN4L audio-4 input (left signal)
50 AUDIOIN4R audio-4 input (right signal)
51 CVBS4/Y4 CVBS/Y input
52 C4 chroma-4 input
53 AUDIOIN2L/SSIF
54 AUDIOIN2R
56 AUDIOIN3L
57 AUDIOIN3R
30 AUDOUTLSL Audio input
61 AUDOUTLSR
62 AUDOUTHPL
63 AUDOUTHPR
59 C2/C3 chroma-2/3 input
64 CVBSO/PIP CVBS/PIP signal output
65 SVM scan velocity modulation output
66 FBISO/CSY flyback input/sandcastle output or composite H/V
67 HOUT horizontal output
70 VIN (R/PRIN2/CX) V-input for YUV interface
71 UIN (B/PBIN2) U-input for YUV interface

Version: 1.0
-33 -

72 YIN Y-input for YUV interface
(G/YIN2/CVBS-YX)
73 YSYNC Y-input for sync separator
74 YOUT Y-output (for YUV interface)
75 UOUT (INSSW2) U-output for YUV interface
76 VOUT (SWO1) V-output for YUV interface
77 INSSW3 3rd RGB / YPBPR insertion input
78 R/PRIN3 3rd R input / PR input
79 G/YIN3 G input / Y input
80 B/PBIN3 3rd B input / PB input
83 BCLIN Beam current limiter input
85 RO Red output
86 GO Green output
87 BO Blue output
97 INT0/P0.5 External interrupt 0 or port 0.5 (4 mA current
sinking direct drive of LEDs)
98,99,102~109 P0.0~ P0.4 Data port
111~116,119,120 P1.0~P1.7,P2.0~P2.5,
122,123,126~ 128 P3.0~P3.3

Version: 1.0
-34 -
UOC Block Diagram:
CHAPTER THREE
SIGNAL FLOW ANALYSIS AND KEY POINT MEASURE DATA

Version: 1.0
-35 -
The chapter mainly introduces the receipt and dispose of the AV signal, the power supply system and
system control process of this TV.
Video Signal Flow:

The IF signal which is demodulated from RF signal by main demodulator is sent through TV board
into video decode chassis UOC for decoding, together with the input signals via AV port and two-way
SCART ports, then the output analog video signal is sent into analog-to-digital converter
TDA8759HV/8/C1 for A/D transform to produce R, G, B digital signals which are transformed in
format by GM1601/GM1501, then, it transformed the different input formats into the uniform
up-screen signal format. In addition, that TV signal is processed by UOC would produce two-way
CVBS signal respectively used for video output of two-way SCART and AV ports.
The signal demodulated from RF signal by sub demodulator is directly sent into submenu video
decoder SAA7115HL/V1 for video decoding and A/D conversion, together with the input signals via
AV port and two-way SCART ports, then again sent into GM1601/GM1501 to do format transform,
the output up-screen is used for submenu display.
The alternative PC, HDTV (YPBPR) and DVI signals are sent directly into GM1601/GM1501 for
processing to form uniform up-screen signal.
Accompanying Sound Flow:

What input sound signal would be sent into UOC for demodulation and sound disposal after selection
and simple processing then, the output audio signal is zoomed in by D class TPA3002D2PHPR and is
sent into the speaker at last. The other is used for SCART and AV sound output.
TV Power Supply System:

4 channels voltage is transported from the power supply board, they are +24V, +12V, +5V and +5VS.
+24V is provided for inverter of LCD panel, +12V is provided for PA, +5V is transformed by the DO
(for example: LM1117, LM1084) into 3.3V, 2.5V and 1.8V for IC, it may be turned down under
standby mode, while +5VS is provided for MCU, infrared receiver, EEPROM.
5V is divided into two ways, one way is provided for other IC and apparatus, the 5V will be turned
down under standby mode, but can not be cut off. The other 5V is provided for MCU, infrared
receiver, EEPROM and so on, it would not be cut off under standby mode.

Version: 1.0
-36 -
U5 TDA9178
U3 MC78M08
The 20th pin
JP1 9,
1C PIN
JP701
U501 LM2596-5.0
12 V The 26-30th pin
JP11 9,
2 PIN
U6 TPA3002
UP3 IRF7134
14, 15, 22, 23, 33,
38, 39, 46, 47 pin
U201 UOCIII 100, 11,

UP7
7, 124, 15, 3, 118, 96,
LM1117-1.8
93, 47, 82 PIN
UP6 JP3 the 9th PIN

LM2596-5.0 parent/sub TUNER
UA3 the 16th PIN

JP11 7, U400 TDA8759 13, 64,
24V UA1 the 14th PIN
8 PIN 21, 29, 37, 43, 138, 3, 139,
145, 151, 157, 123 PIN
U503
LM1084IS-3.3
U402 SAA7115 1, 25, 51,
75, 33, 43, 58, 68, 93, 8, 83
PIN
U504
U502 LM1117-1.8
LM2596-5.0
U505 U700 GM1601

LM1117-2.5
JP1 the MCU5
6th PIN
U506 U305 the 2nd PIN
LM1117-3.3 CN70 the 4th PIN
CN70 the 3rd PIN

Version: 1.0
-37 -
U309
NLAS4052 the
16th PIN
JP1 4, 5
PIN U508 IRF7134
U305 SM5301
18, 22, 26 PIN
U403 U400 TDA8759 11,

LM1117-1.8 87, 16, 30, 32, 58 PIN
U400 TDA8759 88, 48,

U405
54, 61, 67, 69, 76, 82,
LM1117-3.3
59 PIN
Manostat Pin Voltage in Main Board Schedule
Name Type PIN1(V) PIN2(V) PIN3(V) PIN4(V) PIN5(V)

UP7 LM1117-1.8V 0 1.8 5 1.8
UP1 LM1117-3.3V 0 3.3 5 3.3
UP6 LM2596-5.0 24 5 0 5 0
U405 LM1117-3.3 0 3.3 5 3.3
U3 78M08 12 0 8
U403 LM1117-1.8V 0 1.8 5 1.8
U503 LM1806-3.3 0 3.3 5 3.3
U505 LM1117-2.5 0 2.5 5 2.5
U506 LM1117-3.3 0 3.3 5 3.3
U501 LM2596-5.0 12 5 0 5
U502 LM2596-5.0 24 5 0 5 0
U504 LM1117-1.8V 0 1.8 5 1.8

Version: 1.0
-38 -
Main Components and Socket Locations and Definitions:

Version: 1.0
-39 -
Outlet Definition:
Number Name Connected Object Function Description

1 JP400 TV board
JP401
2 JP2 Side AV
3 JP6 DVD AV output
4 JP7 Speaker
5 JP8 Speaker
6 JP4 DVD decode board
7 JP3 Outside AV input
8 JP9 Up screen (screen inverter
input)
9 JP10 Up screen (screen inverter
input)
10 JP12 Power supply board GND, GND, GND, +12V, +12V, +12V
11 J171 Prepare to use
13 JP11 Power supply board +12V, +12V, GND, GND, GND, GND, 24V,
24V
14 JP1 Power supply board SB, GND, GND, 5V, 5V, 5V, GND, GND, 12V,
12V
15 J700 Prepare to use
16 CN702 Prepare to use
17 CN700 Remote control
18 CN701 K board
21 JP701 Display
23 AVP303 DVI audio input
24 CN300 DVI port
25 AVP300 VG audio input
26 CN301 VGA port
27 JPY400 HDTV AV input
JPY401
JPY402
28 JPA400 SCART (1) interface
29 JPA401 SCART (2) interface

Version: 1.0
-40 -
Main Components Description:
Number Name Components Function Description

A U201 TDA15021H/N1B07 AV decoder
B U400 TDA8759HV/8/C1 Video signal AD converter
C U402 SAA7115HL/V1 Sub channel video decoder
D U600 MT46V2M32LG-4 Frame buffer memorizer
E U700 GM1601/GM1501-BD Video processor
F U305 SM5302AS-G-ET HD signal filter
G U801 AM29LV800DT-70EC Flash，the TV control procedure put in it
H U6 TPA3002D2PHPR Audio PA
I U5 TDA9178T/N1 Video signal image improve
J K202 K9656M Sound surface filter
K K201 K3953M Sound surface filter
L UA3 FSAV330QSCX Select switch
M U701 24LC32A T/SN Buffer
N U307 FSAV330QSCX Select switch
O U306 FSAV330QSCX Select switch
P U302 24LC21A T/SN EEPROM
Q U303 24LC21A T/SN EEPROM

Version: 1.0
-41 -
Main Points Undulance Illustrations:

RF input color stripe signal, TV signal undulance in the 19th pin of sub tuner UT1,The undulance of
the 10th of SAA7115 also like this:
RF input color stripe signal, the Pin85, Pin86, Pin87 of U201 output R,G,B signal undulance, the E
pole undulance of Q171,Q172,Q173:

Version: 1.0
-42 -
RF input color stripe signal, I²C bus clock signal UOCIII_SCL, the undulance of the 98th pin of U201,
the 11th pin of U5, the 4th pin of parent/sub RF tuner:
RF input color stripe signal, UOC vertical sync signal, the undulance of the 22th pin of U201, the
105th pin of U400:

Version: 1.0
-43 -
RF input color stripe signal，UOC vertical sync signal , the undulance of the 22th pin of U201,the
105th pin of U400:

Version: 1.0
-44 -
RF input gray ladder signal, the TV signal undulance in the 19th pin of SAA7115:
The 1KHz sound signal input, the undulance of the 60th, 61th pin of U201, the undulance of the 2th,
6th pin of U6 also like this:

Version: 1.0
-45 -
The 1KHz sound signal input, the undulance of 16th, 17th, 20th , 2140th , 41th, 44th, 45th pin of U6 and
pins:
Location Type PIN1(V) PIN2(V) PIN3(V) PIN4(V) PIN5(V)

No.
UP7 LM1117-1.8V 0 1.8 5 1.8
UP1 LM1117-3.3V 0 3.3 5 3.3
UP6 LM2596-5.0 24 5 0 5 0
U405 LM1117-3.3 0 3.3 5 3.3
U3 78M08 12 0 8
U403 LM1117-1.8V 0 1.8 5 1.8
U503 LM1806-3.3 0 3.3 5 3.3
U505 LM1117-2.5 0 2.5 5 2.5
U506 LM1117-3.3 0 3.3 5 3.3
U501 LM2596-5.0 12 5 0 5
U502 LM2596-5.0 24 5 0 5 0
U504 LM1117-1.8V 0 1.8 5 1.8

Version: 1.0
-46 -
SYMPTOMS AND CORRECTION
Symptom Reason and resolve

The display board of PC no If some display board of DVI can not receive the data when turning
image in DVI. on the TV, there is no output; if pull out the DVI line abruptly, there
is also no DVI output; Before starting PC, connect the DVI line with
LCD TV steadily. So DVI can receive the correct date from DDC
(Display Data Channel) when turning on the TV, DDC is in chassis
24LC21.
No picture but sound, on Check the connect line in up screen, and connect the line.
LOGO when turning on the
TV, poor light is bright.
No picture, no sound, no Check the outside of RF (also bus and power supply), there is no
snowflake in TV condition, problem but no output from RF, so the RF is disabled.
but AV is normal.
LCD TV can not be The LCD TV can not work abruptly, power off and turning it on
controlled (inc red lamp is again.
no but the TV is off, remote
control and key press in TV
can not control the TV, etc.)

Version: 1.0
-47 -
LISTS OF BREAKABLE AND MAINTENANCE PARTS
This list is provided for reference, if change the parameters of those maintain parts of an apparatus, we do
not notice in the future. The newest data regard as the correct type or specification.
27″series：
Breakable
No Name Code Number PCB Number Proportion
(%)
1. Frame 8807400310J JUJ8.074.031 0.1
2. Suspend screen 8864000190J JUJ8.640.019 0.1
3. Back cover 8807400341J JUJ8.074.034-1 0.1
4. Base decorate board 8735600050J JUJ7.356.005 0.1
5. Base 8807000130J JUJ8.070.013 0.1
6. Main board assembly 8669000353J JUJ6.690.035-3 PCB JUJ7.820.088 1
7. AV board assembly 8669300150J JUJ6.693.015 PCB JUJ7.820.103 0.5
8. TV board assembly 8669700040J JUJ6.697.004 PCB JUJ7.820.128 1
Remote receive board
9.
assembly 8669400180J JUJ6.694.018 PCB JUJ7.820.104 0.5
Key press board
10.
Inside power supply
11.
module 67128017905 FSP179-4F01 5
12. LCD display screen 68219602735 V270W1-L04 0.1
13. Electron tuner 8289100063E TMI4-C22P2RW 1
14. Electron tuner 8289100454E TAD5-C2IP1RW 1
15. Electric speaker 56224605080 Y2929-01-5W-8Ω 2
16. Electric speaker 562D6608082 Y50138-01-8W-8Ω 2
17. Remote controller 8201803760L KLC5A 1

Version: 1.0
-48 -
37″series：
Breakable
No Name Code Number PCB Number Proportion
(%)
1 Frame 8807400430J JUJ8.074.043 0.1
2 Back cover 8807400442J JUJ8.074.044-2 0.1
3 Base 8807000160J JUJ8.070.016 0.1
4 Main board assembly 8669000354J JUJ6.690.035-9 PCB JUJ7.820.088 1
5 AV board assembly 8669300150J JUJ6.693.015 PCB JUJ7.820.103 0.5
6 TV board assembly 8669700040J JUJ6.697.004 PCB JUJ7.820.128 1
Remote receive board
7
Key press board
8
Inside power supply
15
module 68213700105 LC370W01 0.1
16 LCD display screen 8864000150J JUJ8.640.015 0.1
17 Electron tuner 8289100063E TMI4-C22P2RW 1
18 Electron tuner 8289100454E TAD5-C2IP1RW 1
19 Electric speaker 56232971081 Y3297-L-10W-8Ω 1
20 Electric speaker 56232971082 Y3297-R-10W-8Ω 1
21 Remote controller 56239390580 Y3939-01-5W-8Ω 2
22 Remote emitter 8201803510L KLC5B 1

Version: 1.0
-49 -
FACTORY MODE AND NOTICE
Enter into factory menu

Enter into child lock of main menu in TV mode, press “OK”, the password input box will appear;
USE remote control to input the follows in order: 7, red key, 9, blue key, then you can enter into
factory mode menu. After entering into factory mode menu, sign of the factory menu M will appear.
Factory menu and setup

Factory menu display is below:
M
Index: 1
HWUC_BRI 0x1F
The M denotes entering into factory mode now, the figures of index denotes the index number now,
the HWUC_BRI denotes the name of adjusting item now, the 0X1F denotes the numerical value.
Each adjusting item have only one index number, the operator press the numeric key or press P+/P-
directly.

Version: 1.0
-50 -
Optional and adjustable items, the corresponding relation of index number and adjusting item is
below:
Operating
(Index) Name Definition Remark
key
1 HWUC_BRI UOCIII subsidiary Tune subsidiary brightness
V+/V-
brightness
2 HWUC_SAT UOCIII saturation V+/V- Tune subsidiary saturation
3 HWUC_CON UOCIII contrast V+/V- Tune subsidiary contrast
4 HWUC_AGC UOCIII AGC V+/V- Tune AGC
5 PIP Brightness 7115 subsidiary Open sub picture When
V+/V-
brightness tuning it
6 PIP VGA Contrast 7115 contrast Open sub picture When
V+/V-
tuning it
7 Balance Sound balance The tuning value is 50,
V+/V-
-50, 0
8 Volume Sound Volume V+/V- Step is 10
9 Sound System Sound System V+/V- DK/I/BG/M
10 Auto Search Auto searching V+/ok Source of Signal is TV
11 White Balance White balance V+/ok
12 Auto Color Auto color revise Source of Signal VGA
V+/ok
/YPbPr /TV
13 DVD DVD preset V+/V- 1 represent preset
14 BBE BBE preset V+/V- 1 represent preset
15 TruSurround TruSurround preset V+/V- 1 represent preset
16 SALESFOR SALESFOR V+/V- Set sell country
17 Factory Out initialization V+/ok Leave factory set
18 ClearEEProm initialize EEPRom V+/ok Initialize the storage date
19 D Mode Enter into design Adjustable design mode
V+/ok
mode all the parameter
20 DPF DPF preset V+/V- 1represent preset
21 BBE_CONT BBE plus set V+/V- Tune BBE plus
22 BBE_PROC BBE plus set V+/V- Tune BBE plus
23 Newcom Newcom set V+/V- 1represent preset
Notice:
1. If no especial demand, please do not enter into the 20th item (design mode).
2. When tuning the 16th item, the storage data will be cleaned off. Therefore, if not necessary, please
do not adjust it, the items of index number 1, 2, 3, 4, 5, 6 are not necessary to adjust.

Version: 1.0
-51 -
Methods of adjustment for factory menu

1. Select the adjusting item operator can skip to the adjusting items by pressing the number key,
also can select the adjusting item in the order of P+/P-.when pressing the number key. If the
adjusting item is 1~9,input the corresponding number keys and press down “OK”. If the adjusting
items tens digit, input a tens digit for example, press number key 8 when adjusting the volume,
you can see the color which become green, then press down “OK”. The color of index number
turns red, so you already selected corresponding volume adjusting item.
2. Adjusting methods adjust it according to the operating key in above list. For one acting operation.
Press OK/V+ example AutoColor. For some variable add/reduce, example Volume, press V+/V-.
All menu functions are on in factory mode, if necessary you can use menu to check the items and
effect test.
Factory debug item

1. Auto color revise (AutoColor)
You should finish auto color revise first before factory debug. Revise in TV, YPBPR and PC
respectively.
① Requisite Meters
PC one
HD signal source one
② Debug (Revise in TV, YPBPR and PC respectively)

Park the channel in C-3 under TV mode, then do AutoColor.
Input color stripe signal in YPbPr and do AutoColor.
Input window signal in PC, the window is white with black signal around.
The result will appear on screen after AutoColor adjustment. As for TV, you should make
the adjustment results of Rgain, Ggain and Bgain close to 0×80; If the difference is too
great, adjust the value of HWUC_CON(auxiliary saturation),and readjust the AutoColor.
2. White balance, color temperature adjustment
① Requisite Meters
CHROMA 7120 color analyze instrument (or same function instrument, contain color
coordinate – chroma diversion card) one
White balance adjusting frock（request the video output range 0-1V is adjustable, 750hm
load) one
② Preparation
a. Connect all equipment, switch the condition of LCD TV to AV.
b. Set the picture of LCD TV for standard condition
Set the distance of light receiver of white balance from center place of LCD display screen
for 15cm±3cm.
Make sure that the environmental brightness is below 2cd/m2.

Version: 1.0
-52 -
③ White balance, color temperature adjustment

Before adjusting it, put the first LCD TV in AV condition, and the image in standard
condition, white balance adjust frock send the white vertical signal output from video into
AV, adjust output range of balance adjust frock, make the brightness of the LCD TV
200±20cd/m2 (use CHROMA 7120 color analyze instrument to obtain the brightness), then
fix the video output range of white balance adjust frock (until all the LCD TV are adjusted).
Enter into white balance adjusting item of factory mode, change R, G, B value (try best to
adjust this 3 value to maximum).
Make color temperature coordinates value same to this table below: (Error limitation ± 4%):
X Y
K12000 0.270 0.277
Note:
After color temperature and color coordinates meet the above requirements, you should judge whether
is any abnormal color or not, that is to say, is the value of Δuv 0, if not, it means abnormal color,
then you should adjust values of R, G, B to 0, meanwhile, meet the color coordinates requirements.

Version: 1.0
-53 -
CIRCUIT DIAGRAM
FSDATA[0..31]
RGB/YPbPr_SEL
Ls08-Frame Memory-02
FSDQS
Ypbpr/RGB_EN
Ls08-Frame Memory-02 Ls08-AD convert-01
FSDQM[0..3] Ls08-AD convert-01 LS08-Gm1601-03 ls08-Graphics_Components In-04
PWM3
FSDATA[0..31] FSDQM[0..3]
FSCKE MSTR_SDA MSTR_SCL LS08-Gm1601-03 ls08-Graphics_Components In-04
HV_SEL
FSDQS FSCKE FSBKSEL1 VGRN[7..0] MSTR_SDA MSTR_SCL /OCM_WE GREEN+ BLUE-
23SDD[31..0] FSBKSEL1 /FSCAS 23SDD[31..0] VGRN[7..0] /FSRAS /OCM_WE GREEN+ RXC- VGA_SDA BLUE- RGB/YPbPr_SEL
/FSCAS 23SDD[31..0] /FSRAS RXC- VGA_SDA PWM3
/FSRAS /FSRAS 23SDCLK 23SDCLK OCMADDR[0..19] OCMADDR[0..19] AHS AHS BLUE+ BLUE+ Ypbpr/RGB_EN
/FSWE /FSWE 23SDDQM 23SDDQM MSTR_SCL MSTR_SCL RED- RED- HV_SEL
FSBKSEL0 FSBKSEL0 23SDCS# 23SDCS# FSCLK+ FSCLK+ VGA_SCL VGA_SCL GREEN+ GREEN+
FSCLK- 23SDBA0 /FSCAS SVCLK DVI_CAB
FSCLK- FSCLK+ 23SDBA1 23SDBA0 OCMDATA[0..7] /FSCAS SVCLK RXC+ RX1+ DVI_CAB
FSCLK+ 23SDA[10..0] 23SDCAS# 23SDBA1 MSTR_SDA OCMDATA[0..7] RXC+ GREEN- GREEN- RX1+
23SDA[10..0] 23SDCAS# MSTR_SDA GREEN- GREEN-
23SDDQM 23SDDQM 23SDCAS# 23SDRAS# /ROM_CS /ROM_CS ITRU[7..0] ITRU[7..0] RX1- RX1-
23SDBA0 23SDBA0 23SDWE# 23SDWE# PBIAS PBIAS RED+ RED+ RX0- RX0-
23SDBA1 23SDBA1 23SDA[10..0] 23SDA[10..0] /FSWE /FSWE BLUE- BLUE- RED+ RED+
23SDWE# DVI_SDA BLUE+ RXC-
23SDWE# 23SDCAS# FSCKE DVI_SDA BLUE+ RX1- RX2- RXC-
23SDCAS# 23SDRAS# VVS VGA_SDA FSCKE RX1- DVI_SCL RX2+ RX2-
23SDRAS# VVS VGA_SDA DVI_SCL RX2+
23SDCS# 23SDCS# VCLK VCLK FSDQS FSDQS RX1+ RX1+ RXC+ RXC+
23SDCLK 23SDCLK FSBKSEL1 FSBKSEL1 RX2+ RX2+ RX0+ RX0+
FSADDR[0..11] FSADDR[0..11] VHS VHS FSCLK- FSCLK- RX2- RX2- DVI_SCL DVI_SCL
VBLU[7..0] FSBKSEL0 VGA_CAB
VRED[7..0] VBLU[7..0] FSDATA[0..31] FSBKSEL0 RX0- DVI_SDA VGA_CAB
Scart2_CIn VRED[7..0] PPWR FSDATA[0..31] RX0- AVS VGA_SCL DVI_SDA
Scart2_VideoIn Scart2_CIn /OCM_RE PPWR AVS RX0+ SOG VGA_SCL
Scart2_VideoIn /OCM_RE RX0+ SOG
Video1_C_IN Video1_C_IN FSADDR[0..11] FSADDR[0..11] RED- RED- AVS AVS
Video1_Y_IN Video1_Y_IN PWM3 PWM3 SOG SOG AHS AHS
SubchannelTV FSDQM[0..3] Scart2_CIn
ITRU[0..7] SubchannelTV SEC_SDA FSDQM[0..3] Scart2_VideoIn Scart2_CIn
7115_RSON ITRU[0..7] SEC_SDA VGA_CAB Video1_C_IN Scart2_VideoIn
ls08-Memory I_F-05 SVCLK 7115_RSON RGB/YPbPr_SEL VGA_CAB DVI_CAB Video1_Y_IN Video1_C_IN
SVCLK RGB/YPbPr_SEL DVI_CAB Video1_Y_IN
ls08-Memory I_F-05 POWER_OFF POWER_OFF SubchannelTV SubchannelTV
/ROM_CS /ROM_CS SAA7115_EN SAA7115_EN Set_tristate2 Set_tristate2 VCLK VCLK Scart1VideoIN Scart1VideoIN
/OCM_RE Tv_BOUT Set_tristate2 VVS Set_tristate2
/OCM_RE /OCM_WE Tv_GOUT Tv_BOUT ChannelSel2 Set_tristate1 VVS VHS Set_tristate1 Set_tristate2
/OCM_WE OCMADDR[0..19] Tv_ROUT Tv_GOUT ChannelSel1 ChannelSel2 VHS ChannelSel2 Set_tristate1
OCMADDR[0..19] OCMDATA[0..7] TV_Csync Tv_ROUT Sel_HsVs ChannelSel1 SCRT2-FSEL ChannelSel1 ChannelSel2
OCMDATA[0..7] TV_Csync Sel_HsVs CC_INT1 ChannelSel1
Scart1VideoIN Scart1VideoIN Teltext_MUTE Teltext_MUTE VRED[7..0] VRED[7..0] Sel_HsVs Sel_HsVs
Yout Yout Communication Communication VGRN[7..0] VGRN[7..0] Yout Yout
PRout AudioSelADDB VBLU[7..0] PRout
PBout PRout AudioSelADDA AudioSelADDB VBLU[7..0] ITRU[7..0] PBout PRout
8759PowerDown PBout SAA7115_EN AudioSelADDA ITRU[7..0] SVCLK AudioSelADDA PBout
AVS 8759PowerDown 8759PowerDown SAA7115_EN SVCLK AudioSelADDB AudioSelADDA
AVS 8759PowerDown AudioSelADDB
LS08-Power_Display-06 SVCLK SVCLK 7115_RSON 7115_RSON Teltext_MUTE Teltext_MUTE
LS08-Power_Display-06 AHS AHS IRDATA IRDATA Ypbpr/RGB_EN Ypbpr/RGB_EN IRDATA IRDATA
PBIAS SAA7115_EN M_SCL HV_SEL Communication
PBIAS PPWR SAA7115_EN M_SDA M_SCL HV_SEL Communication
PPWR POWER_OFF M_SDA
POWER_OFF
NEW5-ls08-Sound Amplifier
NEW5-ls08-Sound Amplifier.Sch
NEW1-ls08-12029 MOL LS08-TV-scart
MOL
NEW1-ls08-12029 NEW2-ls08-INPUT PORT MOR MOR LS08-TV-scart
SC1_RIN SC1_RIN SC_AVOUT SC_AVOUT NEW2-ls08-INPUT PORT MUTE MUTE SC2_OR FBLIN1
SC1_GIN AV_R
SC1_BIN SC1_GIN TV_Rout SCOL AV-R AV_L SC2_OL AVS1
FBLIN1 SC1_BIN TV_Gout SC_AVOUT SCOR AV-L FBLIN1 UOC_SW1 SC1_LIN
C_3D FBLIN1 TV_Bout TV_Csync UOC_SW1 SC_AVOUT FBLIN1 AVS1 UOC_SW2 SC1_RIN
C-3D TV_Csync UOC_SW1 AVS1 SCOL AVS2
Y_3D Y-3D AGC AGC UOC_SW2 UOC_SW2 SC1_Laudio SC1_Laudio SCOR SC2_CIn
AV_R AV-R SCOL AGC AGC SC1_Raudio SC1_Raudio SC_AVOUT SC2_YIN
AV_L UOCIII_SDA AVS2
AVS2 AV-L SCOR MOL UOCIII_SCL UOCIII_SDA AVS2 Scart2_Cin txt Tuner_IF SC1_VIN
UOCIII_SCL AVS2 MOL MOR SubchannelTV UOCIII_SCL Scart2__CIn Scart2_VideoIn txt.Sch AGC SC2_LIN
SC1_Laudio UOCIII_SCL MOR 3D_IN MM_SCL SubchannelTV Scart2_VideoIn Video1_Y_IN UOCIII_SDA SC2_RIN
SC1_Laudio 3D_IN MM_SCL Video1_Y_IN Teltext_MUTE UOCIII_SCL SC1_RED
SC1_Raudio SC1_Raudio Communication Communication MM_SDA MM_SDA Video1_C_IN Video1_C_IN IRDATA SC1_GREEN
MUX_L MUX_L UOC_SW1 UOC_SW1 Scart1VideoIN Scart1VideoIN SC1_BLUE
MUX_R UOC_SW2
PH-SW MUX_R UOC_SW2 DVD_id Scart1_R SC1_OR
Scart2_Cin PH-SW DVD_id 3D_reset Scart1_G SC1_OL
Scart2_VideoIn Scart2_CIn 3D_reset Scart1_B SC2_LIN
Scart2_VideoIn SC2_LIN
Video1_C_IN Video1_C_IN SC2_RIN SC2_RIN
Video1_Y_IN Video1_Y_IN SC1_RIN SC1_RIN
Scart1VideoIN SC1_GIN
AVS1 Scart1VideoIN SC1_GIN SC1_BIN
SC2_LIN AVS1 SC1_BIN
SC2_RIN SC2_LIN DVD_id Tuner_IF NEW3-ls08-POWER
SC2_RIN Tuner_IF
Tuner_IF Tuner_IF R_YPBPR R_YPBPR NEW3-ls08-POWER.SCH
MM_SCL MM_SCL Y_YPBPR Y_YPBPR Power_off Power_off
MM_SDA B_YPBPR Backlight_on_off
MUTE MM_SDA B_YPBPR YPBPR_R DVD_On/Off Backlight_on_off
UOCIII_SDA MUTE YPBPR_R YPBPR_L IRDATA/SCL DVD_On/Off
UOCIII_SDA YPBPR_L State/SDA IRDATA/SCL
State/SDA

Version: 1.0
-54 -
+2.5V_DDR
C602 C603 C604 C605 C606 C607 C608 C609 C610 C611 C612 C613 C614 C615
C600
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GND
L600
5.6uH/5%
FSDATA[0..31] FSDATA[0..31] +3.3V_SW
FSVREF
+2.5V_DDR FSVREF
C616
C617 47uF/6.3V
1
0.1uF
14
22
59
67
73
79
86
95
15
35
65
96
58
U600
2
8
FB600 GND
GND
FB601
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
FSADDR[0..11] 97 FSDATA0 3.3VSDRAM2 3.3VSDRAM1
2
FSADDR[0..11] FSADDR0 31 DQ0 98 FSDATA1
FSADDR1 32 A0 DQ1 100 FSDATA2
15
29
43
35
41
49
55
75
81
A2 DQ3
3
9
FSADDR3 34 A3 DQ4 3 FSDATA4 U601
23SDA[10..0]
FSADDR5 48 6 FSDATA6
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A5 DQ6
FSADDR7 50 A7
FSADDR8 51 23SDA0 25 2 23SDD0
FSADDR9 45 A8/AP 23SDA1 26 A0 DQ0 4 23SDD1
FSADDR10 36 A9 23SDA2 27 A1 DQ1 5 23SDD2
23SDA[10..0]
FSADDR11 37 A10 23SDA3 60 A2 DQ2 7 23SDD3
A11 60 FSDATA8
A3 DQ3
DQ8
DQ9 61 FSDATA9 23SDA4 61 A4 DQ4 8 23SDD4
FSBKSEL0 FSBKSEL0 29 BA0 DQ10 63 FSDATA10 23SDA5 62 A5 DQ5 10 23SDD5
FSBKSEL1 FSBKSEL1 30 BA1 DQ11 64 FSDATA11 23SDA6 63 A6 DQ6 11 23SDD6
DQ12 68 FSDATA12 23SDA7 64 A7 DQ7 13 23SDD7

FSCLK- 54 69 FSDATA13
FSCLK- FSCLK+ 55 CLK DQ13 71 FSDATA14 23SDA8 65 74 23SDD8
FSCLK+ FSCKE 53 CLK DQ14 72 FSDATA15 23SDA9 66 A8 DQ8 76 23SDD9
FSCKE 28 CKE DQ15 23SDA10 24 A9 DQ9 77 23SDD10
/FSRAS 27 CS A10 DQ10 79 23SDD11
/FSRAS RAS DQ11
/FSCAS /FSCAS 26 CAS 14 NC
/FSWE /FSWE 25 WE DQ16 9 FSDATA16 21 NC DQ12 80 23SDD12
FSDQS 94 DQS DQ17 10 FSDATA17 30 NC DQ13 82 23SDD13
DQ18 12 FSDATA18 57 NC DQ14 83 23SDD14

FSDQM[0..3] FSDQM0 23 13 FSDATA19 69 SDRAM-64MBX32 85 23SDD15
FSDQM[0..3] FSDQM1 56 DM0 DQ19 17 FSDATA20 70 NC DQ15
FSDQM2 24 DM1 DQ20 18 FSDATA21 73 NC 31 23SDD16
FSDQM3 57 DM2 DQ21 20 FSDATA22
NC DQ16 33 23SDD17
DM3 DQ22 86 PIN TSOP DQ17
DQ23 21 FSDATA23
DQ18 34 23SDD18
DQ19 36 23SDD19
38 NC 23SDDQM 23SDDQM 16 DQM0
39 NC DQ20 37 23SDD20
40 NC 71 DQM1 DQ21 39 23SDD21
41 40 23SDD22
GND 42 NC 74 FSDATA24 28 DQ22 42 23SDD23
FSDQS 43 NC DQ24 75 FSDATA25
DQM2 DQ23
44 NC DQ25 77 FSDATA26 59 45 23SDD24
87 NC DQ26 78 FSDATA27
DQM3 DQ24 47 23SDD25
NC DQ27 DQ25
DQ26 48 23SDD26
23SDBA0 23SDBA0 22 BA0 DQ27 50 23SDD27
91 DNC DQ31 84 FSDATA31
23SDBA1 23SDBA1 23 BA1 DQ28 51 23SDD28
93 53
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MCL
23SDD29
NC DQ29
VSS
VSS
VSS
VSS
54 23SDD30
23SDWE# 17 DQ30 56 23SDD31
23SDWE# WE DQ31
MT46V2M32LG-4 18
5
23SDCAS#
11
19
62
70
76
82
92
99
16
46
66
85
52
TQFP-100 23SDCAS# CAS
23SDRAS# 23SDRAS# 19 RAS

GND 23SDCS# 23SDCS# 20 CS
23SDCLK 68
23SDCLK CLK
1K R601 67
+3.3V_SW CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
+2.5V_DDR
MT48LC2M32B2TG-5
86
72
58
44
6
12
32
38
46
52
78
84
GND
R600 FSVREF 23SDD[31..0] 23SDD[31..0]
10K
FSVREF
R602 3.3VSDRAM1
10K
C618 C619 C620 C621 C622 C623 C624 C625
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GND
GND
3.3VSDRAM2
C626 C627 C628 C629

FSCLK+
0.1uF 0.1uF 0.1uF 0.1uF
R603
150(140)
FSCLK- GND
3ODFH WKLV S DUDOOHO WHUPLQDW LRQ FORVH WRFRUUHVSRQGLQJ PHPRU\ ,& 3LQV

Version: 1.0
-55 -
OCMDATA[0..7]
OCMDATA[0..7]
+3.3V_DIG
U801
37
13
14
29LV800BT
OCMADDR[0..19]
OCMADDR[0..19]
+3.3V_DIG
VCC
VPP
WP#
OCMADDR19 16 47
A18 BYTE#
OCMADDR18 17
A17
OCMADDR17 48 45 OCMADDR0
A16 A-DQ15
OCMADDR16 1 43 C800 C801
A15 DQ14
OCMADDR15 2 41 47uF/6.3V 0.1uF
A14 DQ13
OCMADDR14 3 39
A13 DQ12
OCMADDR13 4 36
A12 DQ11
OCMADDR12 5 34
A11 DQ10
OCMADDR11 6 32 GND
A10 DQ9
OCMADDR10 7 30
A9 DQ8
OCMADDR9 8 44 OCMDATA7
A8 DQ7
A7 DQ6
A6 DQ5
A5 DQ4
A4 DQ3
/OCM_WE OCMADDR4 22 33 OCMDATA2
/OCM_WE A3 DQ2
/OCM_RE OCMADDR3 23 31 OCMDATA1
/OCM_RE A2 DQ1
/ROM_CS OCMADDR2 24 29 OCMDATA0
/ROM_CS A1 DQ0
OCMADDR1 25
A0
+3.3V_DIG
/OCM_RE 28 10
OE# A20/NC
/OCM_WE 11 9
R802 WE# A19/NC
4.7K
/RESET3.3V 12 15
RST# RY/BY#
27
VSS
/ROM_CS 26 46
CE# VSS
8
7
6
5
8
7
6
5
RN800 RN800A R803
10k 10KX4 10K
1
2
3
4
1
2
3
4
Custom1 10: LOW (Use TCLK)

Custom2 R804 0
R805 0 11: LOW (set all display output to '0')
R806 0 12: LOW
RN801 10K 13: LOW(disable serial interface debug)
R807 NC
OCMADDR10 1 8 Serial Interface Debug1 14: LOW
OCMADDR11 2 7 15: LOW
OCMADDR9 3 6 Serial Interface Debug2 16: HIGH (use crystal)
OCMADDR8 4 5 Serial Interface Debug3 17: LOW (8bit bus with OCM access external ROM)
OCMADDR13 1 8 18: HIGH
OCMADDR14 2 7 19: LOW
OCMADDR12 3 6 BOOTSTRAP HEADER
OCMADDR15 4 5 OPEN=1
RN801A
SHUNTED=0 GND
10K INT_OSC
OCMADDR16
OCMADDR18 8-BIT_FLASH2
OCMADDR17 R800 10K 8-bit_flash1
OCMADDR19 R801 10K 8-bit_flash3
GND
GND

Version: 1.0
-56 -
R519 NC
R521A NC
R521 NC
1
32V-EN
CP7
C501A 1u
0.1uF +5V_MCU CP9
U501 3 3 1u
LM2596-5.0 DP3A
L500 TP504 R505 DP3 BAS62-A13
+12V_3A 4 U502
1 Feedback Panel_Power LM2596-5.0 1.2/0.5W BAS62-A13
Vin 33uH D502
ON/OFF
output 2 L501
SMB05
12
12
+24V_1A 4
GND
C502 Feedback
C500 R502 + 1 Vin 33uH +5V
ON/OFF
470uF 0.1uF 47K 2
output CP8
C503
GND
C502A 1u
C505 C501 100uF/35V C519
3
0.1uF 3 3
0.1uF 470uF CP10
D500 C504 0.1uF
1N5824 470uF DP4 DP4A 1u
3
D501 BAS62-A13
1N5824 BAS62-A13 +50V
C517
2
0.1uF
GNDL
3
RP4
R501 10K 2.2k/0.5W
PPWR 1 Q500 +32V
2SC2712Y
+5V +5V +32V
2
CP21
50V100uF DP2
UPC574
GND R508 R510
47K 22K
+5V U503 +3.3V GND

R508A
LM1086CS-3.3 R503 R504 NC GND CP31
0 0 Backlight_on_off 0.1uF
3 VIN TAB 4
3
GND
2 GNDL GND GNDL GND R506 R509
PBIAS 1 1 Q502
TO-263 PBIAS 2SC2712Y
C506 C509 10K Q501 10K
1
47uF/10V 47uF/6.3V 2SC2712Y
2
GND GND
GND U505
+5V LM1117DTX-2.5
+1.8V +1.8V_CORE +5V TO-252
Leave 1sq inch- exposed copper area attached to Tab of U902

Leave room for heat sink
U504 3 VIN TAB 4
LM1117DTX-1.8
GND
FB500 2
3 4 1 2
VIN TAB C513
GND
2 C511 C515
1
D504
47uF/10V 0.1uF 47uF/6.3V
SOD4001 C508 TO-252 C510
C507 47uF/6.3V
1
47uF/10V 0.1uF
GND

GND +5V
R507
47K +3.3V_ADC
R507A
2
+3.3V_ADC +3.3V_DVI +1.8V +1.8V_DVI +3.3V_ADC +3.3V_PLL +3.3V_ADC +3.3V_I/O_BGA +3.3V_ADC +3.3V_LBADC 0 +2.5V_DDR
GND D506
L505 L504 L507 L510 L512 3 BAV99

R513 +3.3V U507
1 8
2 S1 D1 7 +3.3V_SW
47K G1 D1
2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R R516 3 6
100K Q503 4 S2 D2 5
G2 D2
2SC2712Y
1
GND R511 IRF7314 +1.8V
47K SO-8
GND
+3.3V_ADC +3.3V_LVDSA +1.8V +1.8V_ADC +3.3V_ADC +3.3V_LVDSB +3.3V_ADC +3.3V_LVDS +3.3V_ADC +3.3V_DIG
L506 L503 L508 L509 L511

POWER_OFF
R514
POWER_OFF
47K
2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R R517
100K Q505
2SC2712Y
GND
GND
+5V_4A
Leave 1sq inch- exposed copper area attached to Tab of U907 +5V_ANG
U506 U508
+5V LM1117DTX-3.3 +3.3V_ADC R512 1 S1 D1 8 +5V_SW
TO-252 47K 2 7
3 G1 D1 6
4 S2 D2 5
3 VIN TAB 4 G2 D2
GND
2 IRF7314
SO-8
R515
C512 C514 C516
1
47uF/10V 0.1uF 47uF/6.3V 47K

R518
100K
Q504
2SC2712Y
GND GND
GND

Version: 1.0
-57 -
RN401 22X4 5
R406A ADUB00 4 VBLU0
U400A ADUB11 3 6 VBLU1

75 ADUB22 2 7 VBLU2
C420 TDA8759 ADUB33 1 8 VBLU3
R406 49 ADUB44 4 5 VBLU4
REF_B/Pb
Q172 c4119 75 10n RN404A22X4 ADUB55 3 6 VBLU5
R183 2SC1815Y 10n 50 44 ADUB7 1 8 ADUB77 ADUB66 2 7 VBLU6
TV_Bout 100 B/Pb3 VP27 43 ADUB6 2 7 ADUB66 ADUB77 1 8 VBLU7
TV_Bout L174 PBout c4120 51 VP26 42 ADUB5 3 6 ADUB55 RN401A
R174 B/Pb2 VP25 22X4
75 2.2uH 10n VP24 41 ADUB4 4 5 ADUB44
TV_BBout c415 52 B/Pb1 VP23 40 ADUB3 1 8 ADUB33 RN410 22X4
10n 39 ADUB2 2 7 ADUB22 RN404 ADVR00 4 5 VRED0
R402 56 VP22 36 ADUB1 3 6 ADUB11 22X4 ADVR11 3 6 VRED1
R173 C179 C180 R175 R175A BIAS VP21 35 ADUB0 4 5 ADUB00 ADVR22 2 7
12K VRED2
470 330pF 330pF NC 75 R400 75 c416 62 VP20 22X4 ADVR33 1 8 VRED3
REF_G/Y RN408A
R400A 10n VP17 32 ADYG7 1 8 ADYG77 ADVR44 4 5 VRED4
75 c4121 63 31 ADYG6 2 7 ADYG66 ADVR55 3 6 VRED5
10n G/Y3 TDA8795 VP16 28 ADYG5 3 6 ADYG55 ADVR66 2 7 VRED6
Yout c417 64 VP15 27 ADYG4 4 5 ADYG44 ADVR77 1 8 VRED7
G/Y2 VP14
10n VP13 26 ADYG3 1 8 ADYG33 RN410A 22X4 X400
Q173 c410 65 25 ADYG2 2 7 ADYG22 RN408
R184 10n G/Y1 VP12 24 ADYG1 3 6 ADYG11 RN400 13.5MHz
100 2SC1815Y VP11 22X4 22X4 1 2
TV_Gout c418 72 23 ADYG0 4 5 ADYG00 ADYG00 4 5 VGRN0 C401
TV_Gout L175 10n SOG/Y3 VP10 ADYG11 3 6 VGRN1
C400 22pF
R180 RN406A 0.1uF 0.1uF
75 2.2uH c412 73 SOG/Y2 VP07 18 ADVR7 1 8 ADVR77 ADYG22 2 7 VGRN2
22pF C402 C403
3
TV_GGout 10n 17 ADVR6 22X4 2 7 ADVR66 ADYG33 1 8 VGRN3
C419A 74 VP06 16 ADVR5 3 6 ADVR55 ADYG44 4 5 VGRN4
R403A SOG/Y1 VP05
75 10n 15 ADVR4 4 5 ADVR44 ADYG55 3 6 VGRN5
+ +
R179 C182 C183 77 VP04 10 ADVR3 1 8 ADVR33 ADYG66 2 7 VGRN6
GND C405 C406
REF_R/Pr VP03 R401 22uF/6.3V 22uF/6.3V 187R/1%
470 330pF 330pF c4122 R403 c419 VP02 9 ADVR2 2 7 ADVR22 ADYG77 1 8 VGRN7
470K/1% R404
75 10n 78 8 ADVR1 3 6 ADVR11 RN400A 22X4
10n R/Pr3 VP01 7 ADVR0 4 5 ADVR00 GND
Yout c413 79 VP00 RN411 22X4 DACRST#
R181A R/Pr2 RN406 ADHS 1 8 VHS
R181 10n 1 VHS
22R/5%
22R/5%
22R/5%
75 HREF 22X4 ADVS 2 7 VVS C411 0.1uF
NC c414 10n 80 R/Pr1 3 6 VVS GND RDACOUT
95 168 4 5 ADHS
102 HE HS 169 3 6 ADVS ADCLK 4 5 VCLK VCLK GDACOUT
103 COAST VS 2 7 3.3VS23 GND BDACOUT
R405 1K GAIN
104 1 8 ADCLK
R416
R417
GND CLAMP
uoc_vs 105 2 DAC1.8V
R409
R410
R411
VCC5A L171 VSYNC1 CKP RN402
106 DAC3.3V
75R/1%
R418
R452 VSYNC2 47X4
47 107 PLL1.8V
75R/1%
R413 VSYNC3 C4123 When FLI2300 is not installed,where should SHREF be connected?
TV_Csync 108 94 MA1MA2 MA3
75R/1%
C172 C174 TV_Csync HSYNC1 OE NC
NC 109 PP PP PP
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
10V22uF 0.1uF 110 HSYNC2 166 GND
Q171 uoc_hs R451 111 HSYNC3 PL 167 GND 1.8VS23
2SC1815Y CKEXT DE U401
TV_Rout R182 22 113 TCLK
FID_PORT2
HS_PORT2
VS_PORT2
IN_CLK_PORT2
AVSS_PLL_BE2
AVSS_PLL_BE1
DAC_COMP
TEST2
TEST1
TEST0
VSSio
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
D1_IN_0
VDD9(3.3)
DAC_PVSS
VDDcore8(1.8)
DAC_PVDD(3.3)
DAC_AVSS
DAC_AVDD(3.3)
DAC_AVSSG
DAC_VSS
DAC_AVDDG(3.3)
DAC_VDD(1.8)
AVDD_PLL_SDI(1.8)
DAC_GR_AVDD(3.3)
DAC_GR_AVSS
DAC_AVDDR(3.3)
DAC_AVDDB(3.3)
PLL_PVSS
AVDD_PLL_FE(1.8)
DAC_VREFIN
DAC_GOUT
DAC_VREFOUT
DAC_ROUT
DAC_BOUT
DAC_RSET
R456
XTAL OUT
VSScore
DAC_AVSSR
DAC_AVSSB
AVSS_PLL_FE
AVSS_PLL_SDI
PLL_PVDD(1.8)
AVDD_PLL_BE2(1.8)
AVDD_PLL_BE1(1.8)
XTAL IN
TV_Rout L172 CS 170 VHS GND
100 171 NC
R172 2.2uH SDA_V R414 118 ORR/V 172
75 TV_RRout SCL_V R412 119 SDA ORB/U 173 3.3Vcore
100 SCL ORG/Y ADHS VGRN[7..0]
100 114 174 R415 VGRN[7..0]
DIS VAI ADVS
R171 C171 C173 96 A0 FREF 175 4.7K 1 156 2300OE# RN403A 22X4
470 330pF 330pF VREF 176 ADCLK 2 HSYNC1_PORT1 OE 155 FLIGRN7 5 4 VGRN7
VSYNC1_PORT1 G/Y/Y_OUT_7
3.3V_out U400B 3 FIELD ID1_PORT1 G/Y/Y_OUT_6 154 FLIGRN6 6 3 VGRN6
4 153 FLIGRN5 7 2 VGRN5
R176 R176A GND TDA8759 5 IN_CLK1_PORT1 G/Y/Y_OUT_5 152 FLIGRN4 8 1 VGRN4
NC 75 6 HSYNC2_PORT1 G/Y/Y_OUT_4 151 FLIGRN3 5 4 VGRN3
164 165 VSYNC2_PORT1 G/Y/Y_OUT_3
3 Vp OGND 4 7 FIELD ID2_PORT1 G/Y/Y_OUT_2 150 FLIGRN2 6 3 VGRN2
3.3V_out 13 Vp OGND 14 8 VDD1(3.3) G/Y/Y_OUT_1 149 FLIGRN1 7 2 VGRN1

R454 Vp OGND 9 148 FLIGRN0 8 1 VGRN0 VRED7..0]
21 Vp OGND 22 ADUB00 10 VSSio G/Y/Y_OUT_0 147 VRED[7..0]
1K R444 29 30 IN_CLK2_PORT1 VSSio RN403 22X4
Vp OGND ADUB11 11 146 22X4
1
4.7K 37 38 B/Cb/D1_0 VDD8(3.3) RN405

45 Vp OGND 46 ADUB22 12 B/Cb/D1_1 R/Y/Pr_OUT_7 145 FLIRED7 5 4 VRED7
11 Vp OGND ADUB33 13 B/Cb/D1_2 R/Y/Pr_OUT_6 144 FLIRED6 6 3 VRED6 VBLU[7..0]

VBLU[7..0]
1.8Vcore Vcore ADUB44 14 143 FLIRED5 7 2 VRED5
MSTR_SDA 3 2 SDA_V 116 Vcore DGND 12 ADUB55 15 B/Cb/D1_3 R/Y/Pr_OUT_5 142 FLIRED4 8 1 VRED4
130 Vcore TDA8759 DGND 117 ADUB66 16 B/Cb/D1_4 R/Y/Pr_OUT_4 141 FLIRED3 5 4 VRED3
U404 2N7002E 132 127 VDDcore1(1.8) R/Y/Pr_OUT_3
158 Vcore DGND 131 ADUB77 17 VSScore R/Y/Pr_OUT_2 140 FLIRED2 6 3 VRED2
3.3V_out Vcore DGND 18 139 FLIRED1 7 2 VRED1
R455 DGND 159 19 B/Cb/D1_5 VSScore 138 FLIRED0 8 1 VRED0
3.3Vcore 138 Vcore DGND 133 20 B/Cb/D1_6 VDDcore7(1.8) 137
1k R453 139 142 B/Cb/D1_7 FLI2310 R/Y/Pr_OUT_1 RN405A 22X4
1
4.7k 145 Vcore DGND 148 ADVR00 21 R/Cr/CbCr_0 R/Y/Pr_OUT_0 136

151 Vcore DGND 154 ADVR11 22 R/Cr/CbCr_1 B/U/Pb_OUT_7 135 RN407 22X4
Vcore DGND ADVR22 23 134 FLIBLU7 5 4 VBLU7
MSTR_SCL 3 2 SCL_V
157 Vcore ADVR33 24 R/Cr/CbCr_2 B/U/Pb_OUT_6 133 FLIBLU6 6 3 VBLU6
3.3Vcca 48 Vcca AGND 47 GND ADVR44 25 R/Cr/CbCr_3 B/U/Pb_OUT_5 132 7 2 VBLU5
U406 HIGH: 8759PowerDown 54
VccA AGND
53
ADVR55 26
R/Cr/CbCr_4 B/U/Pb_OUT_4
131
FLIBLU5
FLIBLU4 8 1 VBLU4
2N7002E 61 55 R/Cr/CbCr_5 B/U/Pb_OUT_3 VBLU3
67 Vcca AGND 57 ADVR66 27 R/Cr/CbCr_6 B/U/Pb_OUT_2 130 FLIBLU3 5 4
Vcca AGND ADVR77 28 129 FLIBLU2 6 3 VBLU2
69 Vcca AGND 58 ADYG00 29 R/Cr/CbCr_7 VSSio 128 FLIBLU1 7 2 VBLU1
76 60 G/Y/Y_0 VDD7(3.3)
8759PowerDown 82 Vcca AGND 66 30 VDD2(3.3) B/U/Pb_OUT_1 127 FLIBLU0 8 1 VBLU0
59 Vcca AGND 68 31 VSSio B/U/Pb_OUT_0 126

Vbias AGND ADYG11 32 125 FLICLK R432 RN407A 22X4
L402 AGND 70 ADYG22 33 G/Y/Y_1 CLKOUT 124 22R/5%
+3.3V_SW 10uH 3.3V_out L404 3.3Vcore 123 Vi2c AGND 71 ADYG33 34 G/Y/Y_2 VSScore 123 1 TP400 1 TP401
+1.8V_SW 10uH 1.8Vpll 75 G/Y/Y_3 VDDcore6(1.8)
C427 8759Powerdown R408 93 AGND 81 ADYG44 35 G/Y/Y_4 CTLOUT4 122
C430 C433 C436 C438 C440 C443 C445 +C446 85 PD AGND 83 36 VDDcore2(1.8) CTLOUT3 121
22u/10V 100 3.3Vcca Vfro AGND 37 120 FLIHREF
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u VSScore CTLOUT2
C450 + C457 ADYG55 38 119 FLIVS R434
22u/10V 1.8Vpll 87 Vpll_1.8v ADYG66 39 G/Y/Y_5 CTLOUT1 118 FLIHS 22R/5%
GND 0.1uF 88 84 G/Y/Y_6 CTLOUT0
3.3Vpll Vpll_3.3v AGND_pll 86 TP402 ADYG77 40 G/Y/Y_7 TEST OUT1 117
L401 GND AGND_pll 1 R437 100R/5% 41 IN_SEL TEST OUT0 116 1 TP403 1 TP404
42 115
+3.3V_DEC 10uH 3.3Vcca DGNDi2c 120 DEVADDR1 43 TEST TEST3 114
C454 C455 156 126 DEV_ADDR1 SDRAM CLKIN
L405 0.1uF 155 NC DGNDi2c DEVADDR0 44 DEV_ADDR0 VSSio 113
+C444 0.1uF NC SCL_V R438 100R/5% 45 112
C423 C425 C428 C431 C434 C437 C439 22u/10V +3.3V_DEC 10uH 3.3Vpll 153 NC GND SDA_V R439 100R/5% 46 SCLK VDD6(3.3) 111 SDCKO 100R/5% R44023SDCLK
0.1u 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 152 SDATA SDRAM CLKOUT 23SDCLK
NC RESET_2310 R442 100R/5% 47 110 23SDDQM
150 NC RESET_2310 48 RESET_N SDRAM DQM 109 23SDCS#
23SDDQM
GND 149 VDD3(3.3) SDRAM CSN 23SDCS#
C451 + C458 147 NC 49 VSSio SDRAM BA0 108 23SDBA0
23SDBA0
0.1uF 22u/10V 146 NC 163 Reset SAA7115 on the same time. 23SDD0 50 SDRAM D0 SDRAM BA1 107 23SDBA1
23SDBA1
NC TST17 23SDD1 51 106 23SDCAS#
144 NC TST16 162 23SDD2 52 SDRAM D1 SDRAM CASN 105 23SDRAS#
23SDCAS#
SDRAM ADDR10
GND 143 161 SDRAM D2 SDRAM RASN 23SDRAS#
SDRAM ADDR9
SDRAM ADDR8
SDRAM ADDR7
SDRAM ADDR6
SDRAM ADDR5
SDRAM ADDR4
SDRAM ADDR3
SDRAM ADDR2
SDRAM ADDR1
SDRAM ADDR0
L400 141 NC TST15 160 23SDWE#
23SDWE#
SDRAM WEN
VDDcore3(1.8)
VDDcore4(1.8)
VDDcore5(1.8)
NC TST14 23SDA[10..0]
SDRAM D10
SDRAM D11
SDRAM D12
SDRAM D13
SDRAM D14
SDRAM D15
SDRAM D16
SDRAM D17
SDRAM D18
SDRAM D19
SDRAM D20
SDRAM D21
SDRAM D22
SDRAM D23
SDRAM D24
SDRAM D25
SDRAM D26
SDRAM D27
SDRAM D28
SDRAM D29
SDRAM D30
SDRAM D31
+3.3V_SW 10uH 3.3Vcore L403 140 125 23SDA[10..0]
SDRAM D3
SDRAM D4
SDRAM D5
SDRAM D6
SDRAM D7
SDRAM D8
SDRAM D9
NC TST13 23SDD[31..0]
VDD4(3.3)
VDD5(3.3)
+1.8V_SW 10uH 1.8Vcore 137 124 23SDD[31..0]
TEST IN
NC TST12
VSScore
VSScore
VSScore
136 NC TST11 122 R449
VSSio
VSSio
135 121
C422 C424 C426 C429 C432 + C435 + 134 NC TST10 112 22R/5%
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22u/10V C442 C447 C448 C449 C452 C453 + C456 129 NC TST9 101 +3.3V_SW GND
470u/10V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22u/10V NC TST8 RN409 C4125
128 NC TST7 100 22 NC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
GND 115 NC TST6 99 FLICLK 1 8 VCLK
GND 34 98 VCLK
NC TST5 FLIHREF 2 7
10K/5%
33 97
NC TST4 3 6 VHS
10K/5%
10K/5%
FLIHS
R445
R447
20 NC TST3 92 4 5 VVS VHS
TDA8759 AD Power Supply. 19 NC TST2 91
FLIVS
VVS
R446
6 90
23SDA10
NC TST1
23SDA9
23SDA8
23SDA7
23SDA6
23SDA5
23SDA4
23SDA3
23SDA2
23SDA1
23SDA0
5 89
23SDD10
23SDD11
23SDD12
23SDD13
23SDD14
23SDD15
23SDD16
23SDD17
23SDD18
23SDD19
23SDD20
23SDD21
23SDD22
23SDD23
23SDD24
23SDD25
23SDD26
23SDD27
23SDD28
23SDD29
23SDD30
23SDD31
NC TST0
23SDD3
23SDD4
23SDD5
23SDD6
23SDD7
23SDD8
23SDD9
GND GND
GND 23SDA[10..0]
2300OE#
+3.3V_SW L406 3V3D DEVADDR1
23SDD[31..0]
DEVADDR0
10uH
NOTE: FLI2300 could be used in place of FLI2310

+3.3V_DEC L407 3V3A
10uH
R425 100R/5% SCL_V

R426 100R/5% SDA_V
FB411 +1.8V_SW
+3.3V_SW 1 2 3.3VS23
+
L409
98
99
97
23
17
11
25
51
75
33
43
58
68
83
93
72
71
70
69
67
66
65
64
77
78
79
31
32
22
3
2
U402 C480 5.6uH/5%

C459 GND
22uF/6.3V DAC1.8V
SubchannelTV R420 47nF 10 54
TEST3
TEST4
TEST5
TMS
SDA
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
HPD0
HPD1
HPD2
HPD3
HPD4
HPD5
HPD6
HPD7
VDDA0
VDDA1
VDDA2
VXDD
TDI
TRSN
VDDE
VDDE
VDDE
VDDE
AOUT
SCL
SubchannelTV AI24
TDO
IPD7 GND
TCK
+
18R IPD6 55 C471 C472 C473 C474 C475 C476 C477 C478 C479
C460 IPD5 56 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C486 C487
Scart1VideoIN R419 47nF 12 57 22uF/6.3V 0.1uF
Scart1VideoIN AI23 IPD4 59
0 IPD3 FB412
C461 IPD2 60
Scart2_CIn R424 47nF 14 61 1 2 L410
Scart2_CIn AI22 IPD1 62 +1.8V_SW 1.8VS23 GND 5.6uH/5%
0 IPD0
+
C462
Video1_C_IN R422 47nF 16 42 C4104 PLL1.8V
Video1_C_IN AI21 ITRDY
+
0 22uF/6.3V
C463 SAA7115HL ICLK 45 GND C4105 C4106
13 46 C495 C496 C497 C498 C499 C4100 C4101 C4102 C4103 22uF/6.3V 0.1uF
47nF AI2D IDQ 47 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
ITR1 48 L412
IGP0
C464 IGP1 49 5.6uH/5%
Scart2_VideoIn R423 47nF 18 52 GND
Scart2_VideoIn AI12 IGPV 53 +3.3V_SW DAC3.3V
0 IGPH
+
C465 AMCLK 37 C4118
Video1_Y_IN R421 47nF 20 39
Video1_Y_IN AI11 ASCLK 40 22uF/6.3V
0 ALRCLK GND
41 C4111 C4112 C4113 C4114 C4115 C4116 C4117
C466 AMXCLK 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
XTOUT
RESON
TEST0
TEST1
TEST2
ALRCLK is used to seleted to 24.576MHZ crystal.

VSSA0
VSSA1
VSSA2
AGND
XRDY
XCLK
RTCO
LLC2
XTRI
VXSS
XPD7
XPD6
XPD5
XPD4
XPD3
XPD2
XPD1
XPD0
RTS0
RTS1
47nF 19 6
VSSE
VSSE
VSSE
VSSE
XRI1
XDQ
XRV
LLC
VSSI
VSSI
VSSI
AI1D XTAL
CE
XTAL1 7
24.576MHz
SAA7115HL
27
24
15
9
21
5
26
38
50
63
76
88
28
29
30
34
35
36
44
73
74
81
82
84
85
86
87
89
90
92
91
96
95
94
80
4
Strapping' Clock
100
C4004
R429 R433 22P Frequency
NC R430 R431NC R435 Y400
NC NC TP405 TP406
R428 NC GND C404 GND
ITRU7
ITRU6
ITRU5
ITRU4
ITRU3
ITRU2
ITRU1
ITRU0
56R GND 22P C4124

R436 NC DECOUPLING FOR FLI2310 +5V_SW +1.8V_SW
4.7K
3V3D R450 SVCLK SVCLK
+5V_SW U405 +3.3V_DEC U403
22 LM1117DTX-3.3 LM1117DTX-1.8
ITRU[0..7] ITRU[0..7] 3 4 3 4
VIN TAB VIN TAB
GND
GND
2 2
'Strapping' I2C Slave Address TO-252 TO-252

C407 C408 C409 C491 C492 C490
1
1
3V3D 47uF/10V 47uF/6.3V 47uF/10V 47uF/6.3V
R441 0.1uF 0.1uF
3V3A ASSEMBLE RN700 TO RN707.
Open C494A
+ C467 C468 C469 C470 C481 C482 C483 C484 C485 C488 C489 C493 R443 100n C494 C4003 C4001 + C4002 WHEN FLI2310 IS PRESENT
10u 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 4.7K 100n 100n 100n 10u DO NOT ASSEMBLE RN710, RN711,RN712,RN713
Leave 1sq inch- exposed copper area attached to Tab of U408 Leave 1sq inch- exposed copper area attached to Tab of U408
GND GND
GND GND
ASSEMBLE RN710, RN711,RN712,RN713
WHEN FLI2310 IS NOT PRESENT
DO NOT ASSEMBLE TO RN700 TO RN707.

Version: 1.0
-58 -
RN700
22X4 5 RN701
FSDATAU0 4 FSDATA0
FSDATAU1 6 3 FSDATA1 FSCKEU
22X4 5 4 FSCKE
FSCKE
FSDATAU2 7 2 FSDATA2 /FSRASU 6 3 /FSRAS
/FSRAS
FSDATAU3 8 1 FSDATA3 /FSCASU 7 2 /FSCAS FSDQM[0..3]
C701 C700 C702 C703 +1.8V_CORE 5 4 8 1 /FSCAS FSDQM[0..3]
FSDATAU4 FSDATA4 FSDQMU1 FSDQM1
47uF/6.3V 47uF/6.3V 0.1uF 0.1uF FSDATAU5 6 3 FSDATA5 /FSWEU 5 4 /FSWE
/FSWE
C704 C705 C706 C707 C708 C709 C710 FSDATAU6 7 2 FSDATA6 FSDQMU2 6 3 FSDQM2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +3.3V_LBADC FSDATAU7 8 1 FSDATA7 FSDQMU3 7 2 FSDQM3
C711 C712 C713 C714 C715 RN700A FSDQMU0 8 1 FSDQM0
22X4 RN701A
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +1.8V_CORE +3.3V_I/O_BGA +2.5V_DDR +3.3V_LVDSB +3.3V_LVDSA +3.3V_LVDS FSVREF +1.8V_DVI +3.3V_DVI+1.8V_ADC +3.3V_ADC +3.3V_PLL FSDATAU[0..31] RN702 22X4
FSDATA[0..31]
FSDATAU8 5 22X4 4 FSDATA8
FSDATA[0..31]
FSDATAU9 6 3 FSDATA9
GND FSDATAU10 7 2 FSDATA10
AA23
AD12
AD13
AD20
AC10
AB23
AC23
AC12
AC22
AC21
AE17
AA4
W23
W25
AC4
AC6
AC8
AB4
M23
K17
U17
U11
K10
K16
U16
U10
K11
K23
D17
D23
D22
H23
V23
Y23
D10
C13
R23
C11
C10
L16
T16
T17
L11
T11
L23
T23
E23
U700 8 1
P23
F23
W4
J23
J24
E3
FSDATAU11 FSDATA11
Y4
D6
D8
D9
A3
A4
A2
D3
G1
H3
H1
C9
C8
C6
B3
F4
F2
J3
J1
GM1601 FSDATAU12 5 4 FSDATA12
RN703
+2.5V_DDR FSDATAU13 6 3 FSDATA13
7 2 5 22X4 4
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
VDDA33_DDDS
VDDA33_DDDS
FSDATAU14 FSDATA14 FSADDRU9 FSADDR9
LVDSA_3.3
LVDSA_3.3
LVDSA_3.3
VDDD33_LVDS
LVDSB_3.3
LVDSB_3.3
LVDSB_3.3
LBACD-33
VDDA33_RPLL
FSVREF
FSVREF
BGA416
DVI_1.8
DVI_1.8
DVI_1.8
DVI_1.8
DVI_3.3
DVI_3.3
DVI_3.3
DVI_3.3
DVI_3.3
VDDA33_SDDS
VDDA33_SDDS
ADC_1.8
ADC_1.8
ADC_3.3
ADC_3.3
ADC_3.3
ADC_3.3
VDDA33_FPLL
VDDA33_PLL
VDDA18_DLL
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
C716 C718 C719 C720 C721 C722 C723 C724 C725 C726 FSDATAU15 8 1 FSDATA15 FSADDRU4 6 3 FSADDR4
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF RN702A FSADDRU5 7 2 FSADDR5
C727 C728 C729 E24 FSDATAU0 FSADDRU6 8 1 FSADDR6
FSDATA0 E25 22X4 5 4
FSDATAU1 FSADDRU7 FSADDR7
0.1uF 0.1uF 0.1uF N4 FSDATA1 E26 FSDATAU2 FSADDRU8 6 3 FSADDR8
DVI_SCL DVI_SCL FSDATA2
DVI_SDA N3 DVI_SDA FSDATA3 G26 FSDATAU3 FSBKSELU1 7 2 FSBKSEL1
FSBKSEL1
A8 G24 FSDATAU4 FSBKSELU0 8 1 FSBKSEL0
RX0+ B8 RX0+ FSDATA4 H26 22X4 FSBKSEL0
RX0- RX0- FSDATA5 FSDATAU5 RN704A RN703A 22X4
GND RX1+ A9 RX1+ FSDATA6 H24 FSDATAU6 FSDATAU16 5 4 FSDATA16
RX1- B9 RX1- FSDATA7 J25 FSDATAU7 FSDATAU17 6 3 FSDATA17 RN705 22X4

+3.3V_I/O_BGA A10 T26 FSDATAU8 FSDATAU18 7 2 FSDATA18
RX2+ B10 RX2+ FSDATA8 R25 FSDATAU9 FSDATAU19 8 1 FSDATA19 5 4
RX2- RX2- FSDATA9
RXC+ A6 RXC+ FSDATA10 P24 FSDATAU10 FSDATAU20 5 4 FSDATA20 6 3 FSADDR[0..11] FSADDR[0..11]
B6 P26 FSDATAU11 FSDATAU21 6 3 FSDATA21 FSADDRU0 7 2 FSADDR0
C735 C736 C737 C738 C739 C740 C741 C742 C743 R700 RXC- D5 RXC- FSDATA11 N24 7 2 8 1
FSDATAU12 FSDATAU22 FSDATA22 FSADDRU1 FSADDR1
C733 270 C5 NO_CONNECT FSDATA12 N26 FSDATAU13 FSDATAU23 8 1 FSDATA23 FSADDRU2 5 4 FSADDR2
NO_CONNECT FSDATA13
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +3.3V_DVI B11 REXT FSDATA14 M25 FSDATAU14
RN704 FSADDRU3 6 3 FSADDR3
L24 FSDATAU15
22X4 FSADDRU10 7 2 FSADDR10
FSDATA15 L25 8 1
FSDATA16 FSDATAU16 FSADDRU11 FSADDR11
BLUE- B1 M26 FSDATAU17
22X4
BLUE- BLUE- FSDATA17 RN706 RN705A
GND BLUE+ BLUE+ B2 BLUE+ FSDATA18 M24 FSDATAU18 FSDATAU24 5 4 FSDATA24
22X4
+1.8V_DVI GREEN- C1 N25 FSDATAU19 FSDATAU25 6 3 FSDATA25
GREEN- GREEN+ C2 GREEN- FSDATA19 N23 FSDATAU20 FSDATAU26 7 2 FSDATA26
GREEN+ GREEN+ FSDATA20
RED- RED- D1 RED- FSDATA21 P25 FSDATAU21 FSDATAU27 8 1 FSDATA27
RED+ D2 R26 FSDATAU22 FSDATAU28 5 4 FSDATA28
C746 C747 C748 C749 RED+ SOG C3 RED+ FSDATA22 R24 6 3
FSDATAU23 FSDATAU29 FSDATA29
SOG A1 SOG FSDATA23 K24 FSDATAU24 FSDATAU30 7 2 FSDATA30 3ODFH6 HULHV W
HUP LQDW
LRQ
UHVLVW
RUV RQDOO
DGGUHVV DQG FRQWUROOLQHV YHU\ FORVHW
RJP %* $
NO_CONNECT FSDATA24
0.1uF 0.1uF 0.1uF 0.1uF +3.3V_PLL GND +3.3V_PLL VGA_SCL VGA_SCL N2 VGA_SCL FSDATA25 J26 FSDATAU25 FSDATAU31 8 1 FSDATA31 Unloaded trace impedance on this interface is 90 Ohm
VGA_SDA N1 H25 FSDATAU26 RN706A Loaded trace impedace with DRAM load is 65 Ohm (for 2.5 inch total trace
R701 VGA_SDA AHS L4 VGA_SDA FSDATA26 G23 length)
AHS AHSYNC FSDATA27 FSDATAU27
C756 C757 10K/5% AVS L3 G25 FSDATAU28
22X4
AVS AVSYNC FSDATA28
3
GND R4 EXTCLK FSDATA29 F24 FSDATAU29

22pF 22pF F25 FSDATAU30
+3.3V_DVI 2 1 GND FSDATA30 F26 FSDATAU31 FSADDRU[0..11]
FSDATA31
XTAL G4 XTAL
TCLK G3 Place Series termination resistors on bidirectional lines-DATA and DQS midway between gm1601 BGA and memory
F1 TCLK
X700 NO_CONNECT
C752 C753 C754 C755 14.318MHz K3 NO_CONNECT FSADDR0 AD25 FSADDRU0
C750 ACS_RSET_HD K2 AD26 FSADDRU1 Max trace length on this interfce is 2.5 inches
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF ACS_RSET_HD FSADDR1 AC24 0LQLPL]H W
UDFHOHQJW KGLIIHUHQFHEHW Z HHQ' 46 DQGGDW
DDQG DPRQJ W
KHGDW
DOLQHV
FSADDRU2
VRED0 C19 FSADDR2 AC25
VRED0 FSADDR3 FSADDRU3
R703 VRED1 B19 VRED1 FSADDR4 AB26 FSADDRU4
3.3K VRED2 A19 VRED2 FSADDR5 AA24 FSADDRU5
GND VRED3 D18 AA25 FSADDRU6
VRED[7..0] VRED4 C18 VRED3 FSADDR6 AA26 FSADDRU7
VRED[7..0] VRED4 FSADDR7
VRED5 B18 VRED5 FSADDR8 Y24 FSADDRU8
VRED6 A18 AB25 FSADDRU9
C17 VRED6 FSADDR9 AC26 FSCLK+, FSCLK- should be routed like a differentail pair
GND VRED7
VRED7 FSADDR10 FSADDRU10
2SWLRQDO )LOWHU &DSV LQ EHWZHHQ D SDLU RQ /%$'& GLIIHUHQWLDO
WUDFNV FORVH WR WKH 0DOLEX FKLS AB24 FSADDRU11
FSADDR11
VGRN0 A23 VGRN0
VGRN1 C22 U24 FSCLK+
VGRN2 B22 VGRN1 FSCLKp U23 FSCLK+
VGRN2 FSCLKn FSCLK- FSCLK-
VGRN[7..0] VGRN[7..0] VGRN3 A22 VGRN3
VGRN4 D21 VGRN4 FSDQS L26 FSDQSU R705 FSDQS FSDQS
VGRN5 C21 33
VGRN6 B21 VGRN5 T25 FSDQMU0
VGRN6 FSDQM0 R71 NC
VGRN7 A21 VGRN7 FSDQM1 U25 FSDQMU1
JP701
U26 FSDQMU2
B25 FSDQM2 T24 +5V R72 NC 1
VBLU0 FSDQMU3
Set VOL-、 VOL+、 CH-、 CH+、 AV/TV、 MENU and POWER totally 7keys on Keyboard. VBLU1 A25 VBLU0
VBLU1
FSDQM3
FSWE V26 /FSWEU 2
VBLU[7..0] VBLU[7..0] VBLU2 D24 VBLU2 FSCAS V25 /FSCASU 3 J700
VBLU3 C24 V24 /FSRASU 4
+3.3V_DIG VBLU4 B24 VBLU3 FSRAS W26 PanelP R704 5 +3.3V_SW 1
VBLU4 FSCKE FSCKEU
VBLU5 A24 Y25 FSBKSELU0 NC 6 +5V_SW 2
VBLU5 FSBKSEL0
VBLU6 C23 VBLU6 FSBKSEL1 Y26 FSBKSELU1 7 R740 100 3
C760 VBLU7 B23 8 MSTR_SCL 4
47uF/6.3V VBLU7 TXA3+ 9 MSTR_SDA 5
C799 C798 TP700 VCLK VCLK A20 VCLK C730 + C731Panel_Power JP700 TXA3- 10 6
GND 0.1uF 0.1uF Q700 B20 0.1uF 20PIN TXAC+ 11 R741 100 C290 C291
2SC1815Y C20 VODD 0.1uF 12 0.1uF 0.1uF
VVS TXAC-
VVS VHS D19 VVS AC18 1 13 CON6
VHS VHS_CSYNC GPIO_G06_B0
CN700 R706 Q701 TP711 TP712 CHKARM D20 VDV GPIO_G06_B1 AD18 2 14 GND
CN-5 1 GND GND 2SC1815Y B17 Gm1601 AE18 3 R708GND R729 R730 GND TXA2+ 15 GND GND
220 ENBARM
VCLAMP GPIO_G06_B2
2 LED1_KEYPAD
GPIO_G06_B3 AF18 GNDL 4 NC NC NC R732 TXA2- 16
3 LED2_KEYPAD C26 AE19 TXA3+ 5 R728 R731 NC TXA1+ 17
R719 1K PWM0 A3+ NC NC
4 IRDATA PWM1 C25 PWM1 A3- AF19 TXA3- 6 TXA1- 18
5 PWM2 D26 AE20 TXAC+ 7 TXA0+ 19
R707 PWM3 D25 PWM2 AC+ AF20 TXAC- 8 TXA0- 20 Panel_Power
220 R711 1K OCM_TIMER1 AC-
GND GNDL 9 21
CN701 To programable filter. DVDKEY A12 LCD TV / MONITOR CONTROLLER 10 22
1 B12 LBADC_IN3 AD21 11 23 PanelP
ADC_IN2
CN-4 2 ADC_IN1 C12 LBADC_IN2 GPIO_G05_B0 AD22 12 24
LBADC_IN1 GPIO_G05_B3
3 D12 LBADC_RETURN A2+ AE21 TXA2+ 13 PanelP 25 R3 U1
4 C796 C797 AF21 TXA2- 14 R734 26 IRF7314
ITRU0 C16 A2- AE22 TXA1+ 15 R733 27 C1 3.3K 1 8
SVDATA0 A1+ 0 0 R737 0.1 S D
470pF 470pF R717 R718 GND ITRU1 B16 SVDATA1 A1- AF22 TXA1- 16 28 2 S D 7
R717A 10K/5% ITRU[7..0] ITRU2 A16 AE23 TXA0+ 17 0 29 3 6
100K 10K/5% ITRU[7..0] D15 SVDATA2 A0+ AF23 18 30 4 S D 5
GND GND GND ITRU3
SVDATA3 A0- TXA0-
G D
ITRU4 C15 SVDATA4 19
ITRU5 B15 AD23 R702 20
A15 SVDATA5 GPIO_G04_B0 AD24 22k R735 R736 FLATCABLE30 R2
IRDATA +3.3V_DIG ITRU6
SVDATA6 GPIO_G04_B1 3.3K Q1
+5V +3.3V_DIG ITRU7 D14 AE24 +3.3V_DIG GND 0 0 GNDL
To KeyControlBoard. +3.3V_DIG SVDATA7 GPIO_G04_B2 AF24 2SC1815Y
GPIO_G04_B3
TP701 A17 AF25
R746 R738 RXD A14 SVDV
SVODD
GPIO_G04_B4
GPIO_G04_B5
AF26 For LG LC300W01 panel. +3.3V
0 NC TXD B14 SVVSYNC GPIO_G04_B6 AE25 R726 R720
R739 C760A C14 AE26 4.7k 22K
NC SVHSYNC GPIO_G04_B7 R715
C732 100pF +5V SVCLK SVCLK D16 SVCLK
C795 0.1uF CN703 AE8 22 M_SCL TP777 R1 GNDL
0.1uF GND R738A GPIO_G07_B0 AF8 M_SDA M_SCL 1K M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
1 100 GPIO_G07_B1 R716 M_SDA
2 M1 OCM_UDO GPIO_G07_B2 AC9 8759PowerDown 8759PowerDown PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP
M2 AD9 22 LCD-ON
3 OCM_UDI GPIO_G07_B3 AE9 SCART_TXT_SEL
GND GND 4 R738B GPIO_G07_B4
U702 100 GPIO_G07_B5 AF9 AudioSelADDA AudioSelADDA
VCC 3 HEADER 4 K1 /RESET GPIO_G07_B6 AD10 AudioSelADDB AudioSelADDB
GPROBE M4 AE10 Communication
GND GND IR1 GPIO_G07_B7 Communication
RSTN 2 /RESET3.3V M3 IR0
MSTR_SCL MSTR_SCL P4 MSTR_SCL
GND
1
MSTR_SDA MSTR_SDA P3
MSTR_SDA LVDS_SHIELD[0]
AF10 HIGH:
AC11 8759PowerDown
LVDS_SHIELD[1] AD11
LVDS_SHIELD[2]
MAX809LEN GND +3.3V_DIG LVDS_SHIELD[3] AE11 MA4 MA5
SOT23 TP709 TP710 /OCM_WE R3 AF11 / 9 ' 6 3DQHO
FRQQHFW
RU,QW
HUI DFHV GLUHFW
O\ WR6; * $ DQG8; * $ / 9' 6 3DQHO
V
/OCM_WE R2 /OCM_WE B3+ AF12 MA30 MA31 MA32 MA33 PP PP
/OCM_RE /OCM_RE /OCM_RE B3- PP PP PP PP
C717A /ROM_CS /ROM_CS R1 /ROM_CS BC+ AE12
CN702 1000pF CC_INT1 L1 /OCM_INT2 BC- AF13
CON3 CC_INT L2
TP702 /OCM_CS2 P2 /OCM_INT1
/OCM_CS2
1 TP703 /OCM_CS1 P1 /OCM_CS1 +3.3V_I/O_BGA
2 GND /OCM_CS0 T4 AE13
3 /OCM_CS0 LVDS_SHIELD[4] AD14
TP704 OCMADDR[0..19] LVDS_SHIELD[5] AF14 +5V
OCMADDR[0..19] B2+
C717 OCMADDR19 T3 OCMADDR19 B2- AE14 Reserved The Route. MA34 MA35 MA36 MA37
GND OCMADDR18 T2 AF15
1000pF T1 OCMADDR18 B1+ AE15 R744 R745 PP PP PP PP
OCMADDR17 OCMADDR17 B1-
OCMADDR16 U4 AF16 10K 10K TP705 TP706 TP707 TP708 +3.3V_DIG
OCMADDR16 B0+
FSVREF GND +1.8V_ADC OCMADDR15 U3 OCMADDR15 B0- AE16 H1
OCMADDR14 U2 PPP10
OCMADDR13 U1 OCMADDR14
OCMADDR13 R742 R710
OCMADDR12 V4 R709
1
2
3
4
5
6
7
8
9
10
C767 C768 C769 C770 V3 OCMADDR12 AC7 100 NC 2.7K MA38 MA39 MA40 MA41
OCMADDR11 DCLK
V2 OCMADDR11 DCLK AF17 PP PP PP PP
OCMADDR10 DHS RESET_2310
0.1uF 0.1uF 0.1uF 0.1uF OCMADDR9 V1 OCMADDR10 GPIO_14 AD16 DVS
OCMADDR9 GPIO_15
OCMADDR8 W3 OCMADDR8 GPIO_16 AD7 DEN Standby
OCMADDR7 W2
W1 OCMADDR7 R743 TP714
OCMADDR6 OCMADDR6
GND GND OCMADDR5 Y3 OCMADDR5 100
OCMADDR4 Y2 OCMADDR4
+3.3V_ADC +3.3V_DIG OCMADDR3 Y1 AD8 JTAG_TRST
OCMADDR2 AA3 OCMADDR3 GPIO_G08_B5/JTAG_RESET AF7
OCMADDR2 GPIO_G08_B4/JTAG_TDO
OCMADDR1 AA2 OCMADDR1 GPIO_G08_B3 AE7
TP758 OCMADDR0 AA1 AF6 MEC1 MEC2 MEC3 MEC4 MEC5 MEC6 MEC7
C772 C773 C774 C775 C776 OCMADDR0 GPIO_G08_B2/JTAG_TDI AE6 PP PP PP PP PP PP PP
47uF/6.3V C771 GPIO_G08_B1/JTAG_MODE AD6 R723 R727 R727A
GPIO_G08_B0/JTAG_CLK 100 10K
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GPIO_G09_B5 AF5 100 IRDATA/SCL
POWER_OFF AB3 AE5 State/SDA
POWER_OFF RGB/YPbPr_SEL AB2 OCMDATA15 GPIO_G09_B4 AD5 R724 MUTE
OCMDATA14 GPIO_G09_B3 +5V
+3.3V_PLL Set_tristate1 Set_tristate1 AB1 OCMDATA13 GPIO_G09_B2 AC5 100 HV_SEL HV_SEL
GND GND Set_tristate2 AC3 AF4 VGA_CAB R721 R722
Set_tristate2 ChannelSel1 AC2 OCMDATA12 GPIO_G09_B1 AE4 VGA_CAB 4.7K 4.7k
DVI_CAB
ChannelSel1 ChannelSel2 AC1 OCMDATA11 GPIO_G09_B0 DVI_CAB +3.3V_DIG
ChannelSel2 OCMDATA10 R725
C778 C779 C780 C781 C782 C783 C784 Sel_HsVs Sel_HsVs AD1 OCMDATA9 100
C777 TXT_or_Video1_SEL AE1
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AF1 OCMDATA8 A26 C785
OCMDATA7 PPWR
OCMDATA6 AD2 OCMDATA7 PPWR B26 PBIAS
PPWR
OCMDATA6 PBIAS PBIAS I2C address: A2H and A3H
OCMDATA5 AE2 OCMDATA5 R712 R713 0.1uF
OCMDATA4 AF2 AC17 +3.3V_DIG 2.7K 2.7K
+3.3V_LVDSA +3.3V_LVDS AD3 OCMDATA4 NO_CONNECT AC16 U701
GND OCMDATA3 OCMDATA3 OEXTR OEXTR
OCMDATA2 AE3 OCMDATA2 D_GND AD15 8 VCC A0 1
C786 OCMDATA1 AF3 OCMDATA1 7 WP A1 2
C788 C789 C790 OCMDATA0 AD4 R714 MSTR_SCL 6 3
C787 0.1uF OCMDATA0 3.3K MSTR_SDA 5 SCK A2 4
SI VSS
47uF/6.3V 0.1uF 0.1uF 0.1uF
24LC32A-I/SN
VSSA33A_LVDS
VSSA33A_LVDS
VSSA33A_LVDS
SOIC8 (150mil BODY)

GND GND
VSSA33_DDDS
VSSD33_DDDS
VSSD33_LVDS
VSSA33_RPLL
VSSA33_SDDS
VSSD33_SDDS
VSSA33_FPLL
LBADC_GND
VSSA18_DLL
LVDSB_GND
LVDSB_GND
LVDSB_GND
GND GND
VSSD33_PLL
ADC_DGND
ADC_AGND
ADC_AGND
ADC_DGND
ADC_AGND
ADC_AGND
ADC_AGND
FSVREFVSS
FSVREFVSS
GND +3.3V_LVDSB GND

DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
C792 C793 C794

C791 OCMDATA[0..7]
47uF/6.3V 0.1uF 0.1uF 0.1uF OCMDATA[0..7]
E2
E1
E4
F3
P15
P16
P12
P14
P13
P11
P17
P10
A13
U14
U15
N11
N17
N10
K12
N12
U12
N13
K14
N14
K25
K15
N15
N16
K13
U13
AD19
AD17
K26
D13
W24
D4
A5
A7
D7
A11
D11
G2
H4
H2
K4
R15
R11
R10
R13
B13
R16
R12
R14
R17
AC13
AC14
AC15
AC19
AC20
M15
M11
M13
M12
M16
M14
M10
M17
B4
C4
B7
C7
B5
L15
L12
T12
L13
L10
T13
T10
L14
T14
T15
L17
J4
J2
GND
GND GND

Version: 1.0
-59 -
DVI CONNECTOR
CN300
TP308 TP316
25 TP300
1 RX2-
RX2- 2 RX2+
RX2- GND GND
RX2+ RX2+ TP309 TP317
GND 3
RX4- 4
5 TP305
RX4+ 6 DVISCL
GND GND
SCL
SDA 7 DVISDA
TP310 TP318
8
VS TP301
RX1- 9 RX1-
RX1-
10 RX1+
GND GND
RX1+ 11 RX1+ Static Protection.
GND 12 TP311 TP319
RX3-
RX3+ 13 TP306
14 R300 DVI Test Points are just SMTobservation points on the traces with no stub
5V 15 10K/5% GND GND
GND 16 HOT_PLUG
R304 TP312 TP320
HP DVI_CAB
TP302 1K
17 RX0-
RX0- 18 RX0- GND GND
RX0+ RX0+ RX0+
GND 19 R305 TP313 TP321
RX5- 20 TP303 100K
21
RX5+ 22 TP304
GND GND GND
RXC+ 23 RXC+
RXC+
24 RXC-
RXC- RXC-
C1 +5V_AUD GND TP314 TP322
RED
GRN C2 TP307
C3
BLU GND GND
2
HS C4
C5 D300
GND TP315 TP323
26 2 DVI_5V 3 3 3 3 3 3 3 3 3 3
3 D301 D302 D303 D304 D305 D306 D307 D308 D309 D310 GND GND
GND DVI-I GND BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L
1 BAV99L TP327
1
R302 R303 +5V TP1 TP2
10K/5%
10K GND
BASY3 GND
GND GND
DVISCL R301 100 DVI_SCL DVI_SCL
DVISDA R314 100 DVI_SDA DVI_SDA
VGA_SCL
VGA_SDA
VGA_SCL
VGA_SDA
U303
1 A0 VCC 8 +5V_AUD Static protection.+5V can be changed to +5V_ANG according to PCB layer.
2 A1 WP 7
3 6 C301 +5V_MUX
4 A2 SCL 5
GND SDA
0.1uF
GND 24LC21
2
DIGITAL DDC GND D313A D313 D314 D315 D317
BAV99L BAV99L BAV99L BAV99L BAV99L
3 3 3 3 3 3 3 3 3
U311 +5V
VGA_SDA1 1 14
2 A1 VCC 13 D312A D312 D316 D318
B1 C1 C358 BAV99L BAV99L
3 A2 C4 12 0.1uF BAV99L BAV99L
1
4 11
5 B2 B4 10
6 C2 A4 9 GND
C3 B3 GND GND
7 GND A3 8
VGA_SDA2 VGA_SCL2 A-BLUE A-GREEN A-RED A-VS A-HS
MC14016BDR2
VGA_SCL1
GND GND
VGA_5V
+5V UOCIII_write_ctrl R315
VGA_CAB
+5V 10K R317 R320
2
22uF/6.3V 5K +5V_MUX +5V_ANG 100K

Graphic Inputs 1%
D311 RA12 R313 R312 R354
10K 47 47 CN301 47K C302 C304 C305 C306
BASY3 0.1uF 0.1uF 10uF/16V C308 C309
DB15 HD GND
S2
GND C307
GND 0.1uF 10uF/16V 0.1uF 0.1uF
3
R399 15 5
3
VGA_SCL2
VGA_SDA2
1k 10 GND
1 GND
A-VS 14 4 C303 GND
Q309 9 R316
C300 A-HS 13 3 A-BLUE 5K
2SC1815Y
2
8 1% TP324 +5V_AUD
0.1uF R311 GND 12 2 A-GREEN
U302 R310 22K 7 R318 470 C310 0.01uF SOG Q300
3
1 8 22K TP328 11 1 SOG 2SC1815Y R350
A0 VCC A-RED GND
2 A1 WP 7 GND 6 R319 20 C311 0.01uF BLUE+ BLUE+ 1 47K YPBPR_L
3 A2 SCL 6 TP329 C328 0.01uF BLUE- BLUE- YPBPR_L
+
4 5 +5V_MUX R333 TP325
GND SDA 0.1uF 5K R339 20 C329 0.01uF GREEN+ C333
GND GREEN+
2
+5V 1% C330 0.01uF GREEN- L300 YPbPr_LL 47uF/16V
S1
24LC21 C326 GREEN-

GND U306 TP326 +5V_ANG 22uH/0.5A/<1R +5V_AUD
ANALOG DDC R325 R340 20 C331 0.01uF RED+ R351
+3.3V_SW FSAV330M RED+ R349
GND 5K R331 C332 0.01uF RED- RED- 2.2K 47K
C323 1% 75 R334 +5V_MUX
R306 0.1uF R330 5K 1 16 +5V_AUD
SEL VCC C335 GND
R342
R343
R344
10K 75 1% C334
RED_GR 2 1B1 /OE 15 10uF/16V 0.1uF
R396 R326 R332 C324
1
3
10K 5K 75 22uF/6.3V Pr_FIL 3 14 Q301 R366 C348
+5V_ANG +5V_FIL 1B2 4B1 GND 2SC1815Y 47k 47uF/16V
1% GND
56
56
56
4 1A 4B2 13 GND 1 YPBPR_R YPBPR_R
MSTR_SDA 3 2 GND GNDGND YPbPr_RR
+
L301 C319 R335 5 12 W %
V
GRN_GR
U312 2N7002E 100uF/6.3V GND 0.1uF 5K 2B1 4A
2
22uH/0.5A/<1R 1% Y_FIL 6 2B2 3B1 11 BLU_GR GND GND GND R367
R327 C327 +5V_AUD
U309 R365 47K
5K 7 10 Pb_FIL 2.2K
+3.3V_SW +5V_FIL 1% 2A 3B2 This pin set H indicate output is set to tristate. 1 NO0B VCC 16
3
C318 R336 8 GND 3A 9 2 15 R384
R307 +3.3V_SW 5K R338 R341 NO1B NO1A GND Q304 47K
47uF/6.3V C320 R337 NC NC 2SC1815Y 1
10K 1% GND NC MUX_R 3 14
+
C314 C315 C316 330nF C325 MUX_R COMB NO2A
R398 22uF/6.3V C354
1% DPF_Raudio 4 13 VGA_L
1
2
10k C317 0.1uF 0.1uF 0.1uF NO3B COMA 47uF/16V
0.1uF GND 5 12
GND C321 NO2B NO0A R380 R385
MSTR_SCL 3 2 GND C366 100uF/6.3V R328 GND 2.2K 47K
C365 C367 5K 6 Inhibit NO3A 11 DPF_Laudio
U313 10uF/6.3V 10uF/6.3V 10uF/6.3V
7 10 +5V_AUD
2N7002E VEE ADDB GND
GND U305 GND GND R357 1
8 GND ADDA 9
GND R386 10K 2
3
1 REF1 REF2 28 A-HS
NLAS4052 Q305 47k R356
GND 2SC1815Y 22K 3
2 27 A-VS VGA_R 1 AVP300
VDD REF3 R345 100 AV-1
+
R397 100 U307 FSAV330M Set_tristate1 DVI_R GND
3 SDA VCC1 26 +5V_MUX Set_tristate1 C355
1 16 R346 100 ChannelSel1 R358 GNDVGA Audio Input
2
R360 100 SEL VCC ChannelSel1 47uF/16V 10K
4 SCL OUT1A 25 Y_OUT R321 R323
2 15 R347 100 ChannelSel2 +5V_AUD R383
47K 47K 1B1 /OE ChannelSel2 2.2K R391
C359 5 VSS OUT1B 24 +5V_MUX Set_tristate2 Set_tristate2 47K R375
Scart1_R 3 14 R348 100 R387
3
2.2uF/6.3V 6 23 1B2 4B1 47K 22K
MUXSEL GND1
GNDGND 4 1A 4B2 13 C347 MUX_L 1 GND
7 22 10uF/16V MUX_L GND
Component Video Inputs ADS VCC2
+
+5V_MUX 5 12 R348A
Y_YPBPR C312 0.1uF GND 8 21 PB_OUT
2B1 4A R348B C356
Y_YPBPR IN1A OUT2A 100
2
Scart1_G 6 2B2 3B1 11 U308 GND 100 Q306 47uF/16V
C360 DPF_G 9 20 1 16
2.2uF/6.3V IN1B OUT2B R362 7 10 Scart1_B NO0B VCC DELETE BUFFER 2SC1815Y R388
R359 2A 3B2 R373
10 ISET GND2 19 5K Teltext_VS 2 NO1B NO1A 15 Teltext_HS R381 47K 1
8 9 SN74LVC14AD SN74LVC14AD 10k
1.8k 1% GND 3A 2.2K
B_YPBPR GND 11 18 C339 3 14 DPF_H U310A U310C +5V_AUD 2
B_YPBPR IN2A VCC3 0.1uF GND COMB NO2A GND
3
C313 DPF_B 12 IN2B OUT3A 17 PR_out
FSAV330M Truth Table 4 NO3B COMA 13 1 2 5 6 AHS R372 AVP303
0.1uF 22K
GND AV-1
3
R_YPBPR 13 16 R363 S /OE FUNCTION DPF_V 5 12 Q307 R389
R_YPBPR IN3A OUT3B 5K NO2B NO0A U310B U310D +5V_AUD 2SC1815Y 47k C357 GND
C336 X H DISCONNECT 47uF/16V R374 DVI Audio Input
TAB1
TAB2
0.1uF DPF_R 14 IN3B GND3 15 1% 6 Inhibit NO3A 11 Schmitt Triggers 1 10K

L L A=B1 3 4 9 8 R369
+
C361 7 10 Low:Select VGA HS/VS. AVS DVI_L
2.2uF/6.3V L H A=B2 VEE ADDB 2.2K
SM5301AS C338 L302 High:Select TeltextHSVS. +5V_MUX
2
R376
100uF/6.3V GND +5V_ANG 22uH/0.5A/<1R +5V_MUX 8 9 SN74LVC14AD SN74LVC14AD
29
30
GND ADDA R382 R390 22K

C362 R5 2.2K 47K
2.2uF/6.3V NLAS4052 4.7K GND
GND GND GND GND +5V_MUX HV_SEL
C340 C341 C342 C343 C344 HV_SEL
C345 10uF/16V 0.1uF 0.1uF 0.01uF 0.01uF GND
CN306 0.1uF C363 R4
1 DPFR 2.2uF/6.3V DPF_R 4.7K
3
2 R364 +5V_AUD Q303
3 DPFG R377 Sel_HsVs 2SC2712Y
4 GND 100 1 R371 AudioSelADDB
75 C349 U301 R368 AudioSelADDB
5 DPFB 2.2K 10K
6 0.1uF DPF_G C351 EL1883L +5V_MUX
3
+3.3V_DIG R392
7 DPF_H 0.1uF 1 8
2
8 DPF_V Teltext_HS Scart1VideoIN 620 2 CYSNCout VDD 7 Q302
GND Video-in HSYNCout GND
1 R370 AudioSelADDA
9 R379 Teltext_VS 3 VSYNCout RESET 6 2SC1815Y AudioSelADDA
10 DPF_Raudio 75 4 5 10K
C364 C346 GND Burst/Porchout R393
11 2.2uF/6.3V C353 C352
2
12 DPF_Laudio R355 R361 470pF C4680K 0.1uF
13 GND 47K 47K 0.1uF 0.1uF GND
DPF_B GND
CON-13 R324 R395
47K C350 R394 47K
GND 0.1uF GND GND GND GND GND GND
R355A R329 R378 47K NLAS4052 Truth Table
0 47K 75 B A FUNCTION
GND 0 0 COMA=NO0A; COMB=NO0B
GND GND 0 1 COMA=NO1A; COMB=NO1B
GNDGND GND
GND 1 0 COMA=NO2A; COMB=NO2B
R361A 1 1 COMA=NO3A; COMB=NO3B
0
Inhabit=1:All output is open.

Version: 1.0
-60 -
C204 U201B
To TDA9178
R_IN1 0.1uF 78
R_IN R3/Pr 100 YY_out
74 RT11
YOUT 100 U_out
G_IN1 C203 79 75 RT12 V1_8V1_A L1 V1_8V1
SCART1 RGB INPUT G_IN G3/Y UOUT/INSSW2 100 V_out L201 U201A
0.1uF C211 76 RT13 VCC5A 10uH
VOUT/SWO1 10uH
B_IN B_IN1 0.1uF 80 B3/Pb VDD5A_1 15 VDD5A_1 VDDC 124
64 R265 1K 3D_IN 100
CVBSO/PIP VDDC
FB_IN1 R202 77 C215 C218 C221 117 C226 C227 C228
SCART1 RGB CONTROL FB_IN FBLIN VDDC
10K 85 R205 100 10V47uF 0.1uF 0.1uF 0.1uF 0.1uF C231 C256
ROUT TV_Rout
86 R206 100 0.1uF 101 10V47uF 0.1uF
GOUT TV_Gout VSSC
C-3D CT1 0.1uF 70 87 R207 100 18 121
C-3D V/R2/Pr BOUT TV_Bout GNDA1 VSSC
125
VSSC
upc64084 OUTPUT U_IN CT2 0.1uF 71 83 C212 10V47uF L202 VDD5A_2 47 V3_3A
U/B2/Pb BCLIN VDD5A_2
10uH 90
VREF
Y-3D CT3 0.1uF 72 84 A1 C213 C216 C222A C222
Y-3D Y/G2/Y BLKIN L204
R201 100 SVM 65 1000pF R208 C219 2.2uF C224 10uH
YY_out C207 0.1uF 73 66 100 TV_Csync 0.1uF 10V47uF 0.1uF 0.1uF
YSYNC FBISO TV_Csync
40
R204 VCC5A GNDA2
89 L205
C201 27K D201 VSS_REF
Video1_Y_IN 0.1uF C208 0.1uF 55 VCC5A L203 82 10uH VCC5A
SCART1 VIDEO INPUT CVBS2/Y2 VDD5A_3
SCARTVideo1&TXT_Video 58 67 uoc_hs R210 2CK75D 10uH 69 VCOMB
VIDEO1/Y INPUT CVBS3/Y3 HOUT VCOMB
Scart2_VideoIn C209 0.1uF 51 10K R211 C217 C223
SCART2 VIDEO/Y INPUT Scart2_VideoIn CVBS4/Y4 R266 C220
C202 59 4.7K 68K C225
S-VIDEO1 C INPUT Video1_C_IN C2/C3 10V47uF
Scart2_Cin 0.1uF C210 0.1uF 52 0.1uF 0.1uF C230
SCART2-C INPUT Scart2_Cin C4
31 R212 10k AGC 81 0.1uF 10V47uF
AGC AGC GNDA3
43 68
SC_AVOUT R203 1K 48 IFVO 44 R209 C214 V3_3A 1 VSSCOMB
SC_AVOUT SVO/CVBSI FMRO 680 GNDA L212
SCART OUTPUT 10nF C248 V1_8ANA
10uH
VIFIN1 24 41 R221 C247 16V22uF L207 VDD3A 4 96
VIFIN1 PLLIF VDD3A VADC
390 0.1uF 10uH
VIFIN2 25 C249 C257 C261 C264
VIFIN2 C253
42 C243 1uF
SIFAGC 10V47uF
SIF1 29 0.1uF 0.1uF 0.1uF 0.1uF
SIF1
46 C244 1uF 12 95
AGC2SIF GNDA VSSADC
SIF2 30
SIF2
AV-L C238 2.2uF 53 AUDIO2_INL AUDOUTSL 36 R217 1K SCOL SCOL L208 88 VDD3 VDDA 93 L213
C234 2.2uF 54 10uH 10uH
AV-R AUDIO2_INR
C239 2.2uF 56 37 R218 1K SCOR C250 C258 C262 C265
MUX_L AUDIO3_INL AUDOUTSR SCOR
C235 2.2uF 57 C255
MUX_R AUDIO3_INR
VDD5A_1 R213 47K 21 60 R219 100 MOL 0.1uF 10V47uF 0.1uF 0.1uF 0.1uF
EWD/AVI AUDIO_OUT_LSL MOL
C240 50V220nF 19 Sound Amplifier 92
SECPLL GNDAUD
61 R220 100 MOR
AUDIO_OUT_LSR MOR V1_8V1
L211 10uH
62 L209 110 3
AUDIO_OUT_HPL VDDP VDDC
C241 2.2uF 49 10uH L218 V3_3A
SC2_LIN AUDIO4_INL D3.3V VCC5A
SC2_RIN C236 2.2uF 50 AUDIO4_INR AUDIO_OUT_HPR 63 C251 C259 VDD3A 94 VDD3A_94
10uH
C242 2.2uF 34 R225 R238 0.1uF 0.1uF C263A C263 C263B
SC1_Laudio AUDIO5_INL
C237 2.2uF 35 97 10K 10K C266
SC1_Raudio AUDIO5_INR INT0
33 0.1uF 0.22uF 10V100uF 0.1uF
SSIF
106 V1_8V1_A
P00/I2SDI1/0 R227 R234
R214 4.7K 105 100 100 L210 118
P01/I2SDO1 VDD18
23 104 IRDATA/SCL To DVD IR 10uH 2 +5VB
VDRA P02/I2SDO2 IRDATA/SCL VSSC
uoc_vs 22 103 DVD_On/Off C260
VDRB P03/I2SCLK
20 102 C252 5 45 VDD5A_2
DECBG P04/I2SWS VREF_SDAC1 V8SWTCH RT201
2.2uF 0.1uF
C232 C233 R216 39K 27 98 R224 47 UOCIII_SCL 10K
IREF P10/INT1 UOCIII_SCL
C273 50V220nF 26 99 R237 47 UOCIII_SDA
VSC P11/T0 UOCIII_SDA QT201
10V10uF 0.1uF 126 R253 DECDIG V1.8CONTROL
P12/INT2 C288 2SC1815Y
R231 100K 32 107 +5VB V3_3A 6
EHT P13/T1 10K GREF_SDAC1 0.22uF
28 127 R222 100 DVD_id
GNDIF P14/RX DVD_id RT202
128 L216 7 14
P15/TX VREF_SDAC2 DECDIG
17 108 R235 100 MM_SCL 10uH 47K
PH1LF P16/SCL MM_SCL
109 R236 100 MM_SDA C280
R228 P17/SDA MM_SDA C279
C268 C271 R232 1K 16 C278 10
12K PH2LF R262 100 10V10uF XIN
6.8nF 111 Communication 0.1uF 0.1uF
1uF C276 P20/TPWM 112 Communication 8 Y201
10V4.7uF P21/PWM0 GREF_SDAC2 24.576MHz
38 113 R261 100 UOC_SW2 11
DECSDEM P22/PWM1 UOC_SW2 VCC5A XOUT
114 9
P23/PWM2 100 VREF_SDAC3
C277 39 122 R260 UOC_SW1 C281
QSSO P24/PWM3 100 UOC_SW1 RT21 C282
3900pF 123 R270 SAW_SW CT11 22pF
P25/PWM4 NC(15K) 22pF
91 SUB-TUNER SWITCH TDA12029_2
REFAD 100
115 R259 AVS1 1000pF Select Y2 -- Saronix 9922 520 20264
P30/ADC0 100 AVS1
C270 13 116 R258A MUTE
VGUARD P31/ADC1 100 MUTE
10V100uF C274 119 R258 AVS2
P32/ADC2 AVS2 U3
4
0.1uF 120 5VSW RT20
P33/ADC3 MC78M08CDT
RT15 100 NC
TDA15063H-N1B06557 R243
GND 4
R239 10K
OUT
10K V3_3A VCC5A
IN
VIFIN2 VCC5A +12V_3A LT1 10uH
VCC5A
VCC5A VIFIN1
3
K201 R223 R226
R240
R229 K3953M(K7262D CHINA) 22K 22K 20
L214 10K R241 R242 VCC
3216M800MT R233 L215 CT4 CT9 CT5 YY_out 6
10uH 4.7K 4.7K CT4A CT8 YIN
1
2
3
4
5
180 1uH R271

C269 0.1uF 100uF16V
10K 0.1uF 100uF16V 0.1uF U_out 8 19 Y-3D
UOCIII_SDA
UOCIII_SCL
10V100uF C286 UIN YOU
MM_SDA
MM_SCL
nc
V_out 9 17 U_IN
C272 C275 R247 VIN UOUT
0.1uF 0.01uF 4.7K
R250 C287 16 C-3D
R263 R263A VOUT
nc 4700 TV_Csync 1
0 CHINA:R263 0; R264 NC SC
NC CT7
Tuner_IF CHINA:R263 NC; R264 0 0.1uF
Tuner_IF Q201
CT6 CT10 UOCIII_SDA RT3 100 14 15
2SC388 SDA DECDIG
100pF 100pF
UOCIII_SCL RT4 100 11 7
SCL ADR
SW 10
R246 TP
SIF filter 18
VEE
1
2
3
4
5
3.3K MM_SDA RT5 100 3 2

C285 R252 ADCEXT1 NC
NC 27 RT6 100 4 23
MM_SCL JP201 ADCEXT2 NC
RT7 100 5 24
CON-4 ADCEXT3 NC
R264 R264A K202 4 U5
NC K9656M(K9352M/D CHINA)) VCC5A R256
10 TDA9178T UOCIII TAD12019H
R248 0 3
4.7K UOCIII TAD12019H
D205
R245 2CK75D 2
+12V_DC
100
R254 1
R249 22K
2.2K Q202 SAW_SW
C283 R251 2SC1815Y
0.01uF 2.2K
H: L' L:BG/DK/I (EUROPE)
H: BG/DK/I L:M/N (CHINA)

Version: 1.0
-61 -
+5VOUT
VCC5A CA6
0.1uF
RA35
4.7k
RA18
10k SC1_GIN CA20
SC1_GIN
+
VCC5A QA6
JP3 10uF 2SC1815Y
9
8 Video1Y_IN RA36
7 CA1 0.1uF 4.7k RA45
6 Video1C_IN 330
5
4 AVR RA19
3 10k
2 AVL +5VOUT
1 VCC5A VCC5A
CON-9 RA16 RA17 RA37

10k 10k 4.7k
CA21 QA7
SC1_BIN 2SC1815Y
SC1_BIN Scart1_G
+
Scart1_G
+5VOUT 10uF
RA20 RA21 RA38 Scart1_B
10k 10k CA5 4.7k Scart1_B
0.1uF RA46
330 Scart1_R Scart1_R
RA33
4.7k
CA19 QA5
SC1_RIN SC1_RIN 2SC1815Y
+
Video1_C_IN Video1_C_IN
Video1_Y_IN 10uF
DVD_id Video1_Y_IN RA34
DVD_id 4.7k
VCC5A
CON-12 1 16 RA44
JP4 SEL VCC 330
1 DVD_C 2 15 CA4 RA34A
1B1 /OE 0
2 0.1uF
3 DVD_Y 3 14 DVD-L
4 1B2 4B1 To Board Side.
5 DVD-L RA9 4 1A 4B2 13 AVL
6 75
7 DVD-R 5 2B1 4A 12 AV-L AV-L JP5
8
9 DVD_Video RA13 6 11 DVD-R SC1_BIN Y_YPBPR
75 2B2 3B1 1 26 Y_YPBPR
10
11 SPDIF 7 2A 3B2 10 AVR AVS1 AVS1 2 27 B_YPBPR B_YPBPR
12
8 GND 3A 9 AV-R AV-R SC1_GIN 3 28 R_YPBPR R_YPBPR
SC1_RIN 4 29 SC1_Laudio SC1_Laudio
JP6
UA3 The DVD Player Must Output With DC-LEVEL Signal. FBLIN1
FBLIN1
5 30
SC1_Raudio
SC1_Raudio
CON-7
FSAV330M Scart1VideoIN YPBPR_L
7 Scart1VideoIN 6 31 YPBPR_L
6 +5VOUT YPBPR_R
5 7 32 YPBPR_R
4 +12V_dc SCOL
RA10 8 33 SCOL
3 470
2 RA49
1 9 34
220
AVOUT SCOR
1035 SCOR
1136
VCC5A SC_AVOUT
SC_AVOUT 1237
QA12
UA1 CA8 2SC1015Y
0.1u 1338
MC14016BDR2 +32V
M_SDA 1 14 SC2_RIN SC2_RIN 1439
2 A1 VCC 13 GND
VGA_SDA1 3 B1 C1 12 SC2_LIN SC2_LIN 1540
MM_SDA 4 A2 C4 11
MM_SDA B2 B4 AVS2
5 C2 A4 10 VGA_SCL1 AVS2 1641
6 C3 B3 9 Scart2_CIn
7 GND A3 8 M_SCL Scart2_CIn +5VB 1742
GND 1843
Scart2_VideoIn
Scart2_VideoIn 1944
UOCIII_write_ctrl VCC5A +5VOUT SubchannelTV
VCC5A RA47 2045 SubchannelTV
MM_SCL MM_SCL 22
2146
R322 UOC_SW1
10K 2247 UOC_SW1
CA7 CA9 2348 UOC_SW2 UOC_SW2

R352
3
CA31
47K 0.1uF 10V220uF 0.1uF UOCIII_SDA UOCIII_SDA
2449 Tuner_IF Tuner_IF
1
Q308 UOCIII_SCL UOCIII_SCL
2550 AGC AGC
2SC1815Y
2
SDA-7166102050
UOCIII_write_ctrl= +5V, UOC CONNECT WITH 1601 GND

UOCIII_write_ctrl= 0V, UOC CONNECT WITH VGA

Version: 1.0
-62 -
+12V_3A +12V_DC
LA2
+
RA1 33uH
10 CA2 CA3
100uF/16V 0.1u
GND GND CA42 CA24
0.47uF 0.1uF
DA1 1 JP7
NC DA2 QA1
2CK75D 2SA1015Y CA25 2
LA1
+12Vaudio_ctrl 33uH 0.1uF CON2
RA15 + CA38
RA2 10n
470K 10K RA3 +12V_AUDIO CE1
CA53 150K +12V_AUDIO RE2
47uF/16V 1u 10K
+
CA39 CA33
CA55
+24V_4A RA50 0.1u 10n 0.1u RE1 When mode_in is Low,AMP is in class_D.
DA3 100K U6 10K
48
47
46
45
44
43
42
41
40
39
38
37
CA37
W05Z6.8B RA11 220uF/16V TPA3002D2
470K
And the Mode_out is output High.
CE2
PVCCR
PVCCR
PVCCR
PVCCR
BSRN
BSRP
PGNDR
PGNDR
ROUTN
ROUTN
ROUTP
ROUTP
MUTE
Low is mute/shutdown. CA49 1u RE4
10K
MUTE 1u
CA44 1u 1 36 +12V_AUDIO
SD VCLAMPR RE3
MOL MOL 2 RINN MODE_OUT 35
CA46 1u 3 34 Mode_in CA10 10u 10K
4 RINP MODE 33
+
CA45 CA47 1u V2P5 AVCC
1u CA48 1u 5 LINP VAROUTR 32 +5VE CA34
MOR 6 31 0.1u
MOR LINN VAROUTL
7 AVDDREF TPA3002D2 AGND 30
15K 8 29 CA51 100n
RA4 9 VREF AVDD 28
VARDIFF COSC CA52 220P
15k RA5 10 VARMAX ROSC 27
11 26 RE6
VOLUME AGND RE5 10K RA14
10k RA6 12 REFGND VCLAMPL 25 RA54 120K
120K 10K
PGNDL
PGNDL
LOUTN
LOUTN
PVCCL
PVCCL
PVCCL
PVCCL
LOUTP
LOUTP
RA55 4.7k
BSLN
BSRP
CA50
RA7 10k CE3 1 8 CE4 Mode_in 4
1u BYP IN1
0.47u 100u
RA8 2 7 SPDIF/L 3
+
15k GND VO1
13
14
15
16
17
18
19
20
21
22
23
24
+12V_AUDIO +12V_AUDIO +5VE
SPDIF_SW 3 6 CE5 2
SD AVDD
100u
CA41 4 5 1
+
CA35 IN2 VO2
0.1u CA36 High is shut down the erphone JP2
10n 0.1u UE1 CON-4
CA40 CA27
10n TPA6110A2 0.1uF
LA3
33uH
CA26 JP8
1
CA43 0.1uF
RA0 JUMP LA4 0.47uF 2 RE7 RE8
CA28 1K 1k
33uH 0.1uF CON2

Version: 1.0
-63 -
JP1
CON-10 +12V_3A
10 For GM1601 Board supply.
9 +5V_4A +5V_4A
8 +5V_4A For panel supply. LP3
7 +5V_MCU +5VB 22uH VCC5A
+
6 +5V CP13 CP2 CP15
5 470uF 0.1uF 0.1uF
4 +
3 CP3 + CP5
RP2 CP4
2 470uF 0.1uF
22k 32V-EN 0.1uF
1 StandBy_power
+24V_4A UP6 CP6

+24V_4A LP1 470uF
LM2596-5.0 33uH
JP9 JP10 +24V_1A 4
14 14 Feedback
+24V_1A 13 13 1 Vin
ON/OFF
JP11 2
8 12 12 output
GND
11 11 CP34
7 0.1uF CP37
6 10 10 DP1
9 9 CP35 1N5824 0.1uF
5 8 8 CP36
4 0.1uF 100uF/35V
3
3 +12V_3A 7 7 J171
6 6
2 NC
1 5 5 1
4 4 Backlight_on_off
3 3 Backlight_on_off 2
CON-8 3
2 2
CON-14 1 1 4
5
Low is Normal on mode. UP2 CP1 6
JP12 +24V_4A +5VB CON-14 +5VB IRF7314
6 High is standby mode. 1 8 0.1uF 7
S D 8
5 Standby 2 7
4 3 S D 6
RP8 S D
3 RP6 +5VB QP2 10k DVD_On/Off DVD_On/Off 4 G D 5
2 nc
1 Backlight_on_off 2SC1815Y IRDATA/SCL IRDATA/SCL
RP10
RP5 CP34A NC State/SDA
CN-6 nc 0.1uF R6 State/SDA
Brightness
UP4 0
RP11 V1_8ANA
UP7 Si2311DS 2
4
0 CP32 3
0.1uF CP26 LM1117-1.8V
RP11 RP10
CHIMEI: 0 NC 0.1uF P_CHANNEL UP1
OUT 4
LM1117-3.3V
GND
LG 30: NC OK
4
VIN
LG 26: 2.2k 1k
1
AU 26: 1K 3.3k
OUT 4
V1.8CONTROL
+5VB
GND
V1_8V1
VIN
3
1
RA53 UP3 +12V_AUDIO
+12V_3A 0.27/0.5W IRF7134 LP5
1 S1 D1 8 DP6 CP23 CP22 +5VB D3.3V 10uH V3_3A
2 7 0.1uF
1
G1 D1 SOD4001 47uF
3 S2 D2 6 CP14 CP18
+12Vaudio_ctrl 4 5 GND GND GND GND 0.1uF
G2 D2 CP11
CP20 0.1uF
CP24 0.1uF 10V100uF
0.1uF
GND CP16 CP17
GND 0.1uF 10V100uF

Version: 1.0
-64 -
CN303
+5V_ANG
1
2
UOCIII_SCL R308 20 Tel_SCL 3
UOCIII_SDA R309 20 Tel_SDA 4
5
6
7
+5V_MUX
Teltext_R 8
GND CON8
VCC5A
RA29
4.7k CN304
U2 FSAV330M
C2 Teltext_G 1
SCART_TXT_SEL 1 16 10uF/16V Teltext_B 2
SEL VCC
FB_TXT 3
Scart1_R 2 15 4
1B1 /OE
+12V_DC uoc_hs 5
Teltext_R 3 14 FBLIN1 uoc_vs 6
1B2 4B1
7
R_IN1 4 13 FB_TXT RA22 CA11 TXT_Video 8
1A 4B2
10K 0.1uF
Scart1_G 5 12 FB_IN1 RA24
2B1 4A 180 QA3 GND CON8
Teltext_G 6 11 Scart1_B 2SC2712C
2B2 3B1
CA12
G_IN1 7 10 Teltext_B
2A 3B2 QA2 RA28
3D_IN TXT_Video
8 9 B_IN1 2SC1162Y
GND 3A 68
RA26 16V470uF RA30
180 75
VCC5A
U4
TXT_Video 1 16
NO0B VCC
C3
Scart1VideoIN 2 15 10uF/16V
NO1B NO1A
SCARTVideo1&TXT_Video 3 14
COMB NO2A
4 13
NO3B COMA
5 12
NO2B NO0A
6 11
Inhibit NO3A
7 10 +5V_MUX
VEE ADDB
8 9
GND ADDA RA25
NLAS4052 0
RA23
4.7k
NLAS4052 Truth Table
B A FUNCTION RA27 TXT_or_Video1_SEL

0 0 COMA=NO0A; COMB=NO0B 22
0 1 COMA=NO1A; COMB=NO1B H Video1 Y
L TXT Video
1 0 COMA=NO2A; COMB=NO2B
1 1 COMA=NO3A; COMB=NO3B
Inhabit=1:All output is open.

Version: 1.0
-65 -
RA408
47K
Component Video Inputs
CA406 100pF
Y CA407 100pF
JPY400 1 Y_YPBPR CA404 CA405
RY401
2 75 100pF 100pF RA407 47K
JPA400
3 SC1_OR SC1_OR RA431 330 1 2 RA422 1K SC1_Raudio SC1_Raudio
SC1_OL SC1_OL RA432 330 3 4
SCART
5 6 RA423 1K SC1_Laudio SC1_Laudio
4 SC1_BIN RA428 10 7 8 AVS1
SC1_BIN 9 10 AVS1
YPbPr 5 Pr R_YPBPR RA402 10K
SC1_GIN SC1_GIN RA429 10 11 12
13 14 RA426
RY402 SC1_RIN RA430 10 15 16 100 FBLIN1
6 75 SC1_RIN 17 18 FBLIN1
AV-1-3PR
19 20 0 Scart1VideoIN Scart1VideoIN
21 22
RA404 CA409
CA408
GND Pb B_YPBPR RA412 RA413 100pF CA410
CA401 CA402 CA403 RA411 RC-2114 100pF RA420 100pF
3.3K +12V_PORT
RY400 100pF 100pF 100pF
75 75 75 75 75 75
RA400 CA426
10K 0.1uF
RA414 RA415 RA435
180 QA400
2SC2712C
CA429
JPY401 3 RA418 SC1_AVOUT AVOUT QA406 SC1_AVOUT
2 RY403 75 2SC1162Y
YPbPr Left Audio 16V470uF
22K RA437
1 RY405 YPbPr_L 180
AV-1-1PW-1
10k
JPY402 3 CA414 100pF

YPbPr Right Audio 2 RY404 CA415 100pF +12V_PORT
1 22K CA412 CA413
RY406 YPbPr_R
AV-1-1PR-1 100pF 100pF RA409 47K
10k JPA401 RA401 CA427
10K 0.1uF
SC2_OR SC2_OR RA433 330 1 2 RA424 1K SC2_RIN SC2_RIN RA436
SC2_OL RA434 330 3 4 RA410 47K 180 QA401
SC2_OL 5 6 RA425 1K SC2_LIN
SCART
SC2_LIN 2SC2712C
7 8 RA403 10K AVS2 AVS2
9 10
11 12 QA407 SC2_AVOUT
RA405 13 14 2SC1162Y
Scart2_CIn 0 15 16 RA438
SC2_CIn 17 18 RA406 0 180
19 20 Scart2_VideoIn SC2_YIN
CA411 RA416 21 22
RA419 CA416 RA421
3.3K CA417
100pF RC-2114 75 100pF 100pF
+5VB JP400 75
1
2
SubchannelTV 3
+32V 4
5
6
UOC_SW2 7 CA430
RA417
UOC_SW1 8 SC2_AVOUT
9 75 16V470uF
CON-9
JP401
1 +12V_dc +12V_PORT +12V_PORT
Tuner_IF 2 RA427
3 100 CA400
AGC 4
UOCIII_SDA 5 + 0.1uF
RA439 CA431 CA428
UOCIII_SCL 6 +12V_dc 470uF 0.1uF
7 12k RA440 RA441 RA442
12k 12k 12k
CON-7 CA418 QA402 QA403 CA422 QA404 QA405
SCOL SCOL 2SC2712C 2SC2712C SCOL 2SC2712C 2SC2712C
+
10uF 10uF
RA443 CA420 CA421 CA424 SC2_OL CA425
SC1_OR SC2_OR
+
6.8k RA445
10uF RA444 10uF 6.8k 10uF 10uF
6.8k RA446
6.8k RA450
RA447 RA448 RA449 1k
1k 1k
1k
CA419
SC1_OL CA423
SCOR 10uF SCOR
SCOR
+
+
10uF
J400B J400A
Y_YPBPR 26 SC1_BIN 1
B_YPBPR 27 AVS1 2
R_YPBPR 28 SC1_GIN 3
SC1_Laudio 29 SC1_RIN 4
SC1_Raudio 30 FBLIN1 5
YPbPr_L 31 Scart1VideoIN 6
YPbPr_R 32 7
SCOL 33 8
34 +12V_dc 9
SCOR 35 AVOUT 10
36 11
37 12
+32V 38 13
39 SC2_RIN 14
40 SC2_LIN 15
41 AVS2 16
42 Scart2_CIn 17
43 +5VB 18
44 Scart2_VideoIn 19
SubchannelTV 45 20
46 21
UOC_SW1 47 22
UOC_SW2 48 23
Tuner_IF 49 UOCIII_SDA 24
AGC 50 UOCIII_SCL 25
50PIN_12
50PIN_12

Version: 1.0
-66 -
WIRING DIAGRAM

Version: 1.0
-67 -
EXPLODED VIEW
1. Connect each line bouquet and plug with line according to final wiring connection diagram.
2. Routing of the bouguet and plug with line is confirmed by professional technologist and paste adhensive
tape at suitable position to fix them and require routing not dispersedness.
3. Conductive sponge is posted at back of TFT panel first. Then fasten it using chassis module.
4. Check each key flexible or not, switch reliable or not, not permit block phenomenon to appear. If has no
problem, assemble back cover module.
5. After finish unit assembly, fix protect corner cushion on the four corner of front frame using blue
adhensive tape.
6. After unit is passed examination, paste certification, DVD label and fragile label on the surface of back
cover. Require position of pasting should be consistent.

Version: 1.0
-68 -
PART LIST
NO PART NAME
1 Chassis module
2 Front frame module
3 Back cover module
4 Pedestal module
5 Plug with line
6 Power bracket
11 Power filter
12 Screw M3x6
13 Screw M3x8
14 Screw M3x8
15 Screw M4x8
16 Screw M4x20
17 Screw M3x10
18 Screw M3x12
19 Screw 6x16

Version: 1.0

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LCT TV

Model No.: LCT-32CHSTP

MAIN ICS FUNCTION INTRODUCTION ............................................................................................ 8

SYMPTOMS AND CORRECTION ...................................................................................................... 46

LIST OF BREAKABLE AND MAINTENANCE PARTS .................................................................... 47

FACTORY MODE AND NOTICE ........................................................................................................ 49

CIRCUIT DIAGRAM ............................................................................................................................ 53

WIRING DIAGRAM ............................................................................................................................. 66

PART LIST ............................................................................................................................................. 68

Model No.: LCT-32CHSTP

Radio Frequency input; support CATV

Model No.: LCT-32CHSTP

Auto Off if no signal input

Model No.: LCT-32CHSTP

Model No.: LCT-32CHSTP

No. Parts Description

Model No.: LCT-32CHSTP

MAIN ICS FUNCTION INTRODUCTION

Model No.: LCT-32CHSTP

ICs FUNCTION INTRODUCTION IN DETAILS

Sub Tuner (TMD2-E49IPIWA):

Model No.: LCT-32CHSTP

Model No.: LCT-32CHSTP

Pin Name Description

Model No.: LCT-32CHSTP

AB1~AB3, AC1~AC3, OCMDATA0~ Data input output port

Model No.: LCT-32CHSTP

D26, C25, C26 PWM2 ~PWM0 Pulse width modulation output

Model No.: LCT-32CHSTP

Frame Memorizer Interface

Model No.: LCT-32CHSTP

D23, W4, Y4, AA4, IO_3.3 3.3V power supply

Model No.: LCT-32CHSTP

GM1501Internal Block Diagram：

Model No.: LCT-32CHSTP

Model No.: LCT-32CHSTP

TDA8759 Block Diagram

Model No.: LCT-32CHSTP

Pin Name Description

Model No.: LCT-32CHSTP

105~107 VSYNC1~VSYNC3 Vertical synchronization input

Model No.: LCT-32CHSTP

Pin Name Description

5 LINP Positive differential audio input for left channel

16，17 LOUTN Class-D 1/2-H-bridge negative output for left channel

Model No.: LCT-32CHSTP

12 REFGND Ground for gain control circuitry. Connect to AGND. If using a

Model No.: LCT-32CHSTP

TPA3002D2 External Block Diagram：

Model No.: LCT-32CHSTP

SM5301AS Internal Block Diagram：

Model No.: LCT-32CHSTP

Pin Name Description

10, 13, 16, 19 GND Ground

12, 15, 18, 24 VCC Analog 5V supply

22 MUXSEL Input select signal

Model No.: LCT-32CHSTP

Model No.: LCT-32CHSTP