University Questions

Subject: -VLSI Design (T.E. ETRX) Sem:- VI

Ch-1Technology Trend
Dec 2018 (KT Paper)
Q.N. Question Marks
1 Compare Bipolar,NMOS & CMOS technologies 05
2 Compare full scaling model with constant voltage scaling 10
model.

May 2018 (Regular)

1 What are different MOS capacitances? Explain in brief 05
2 Define Scaling. Explain significance of scaling in VLSI 05
circuits
3 Write a short note on level 1 & level 2 MOSFET models 05

Dec 2017 (KT Paper)

1 Compare BJT and CMOS technology in VLSI design 05
2 What are different MOSFET models? Give importance of 10
MOSFET capacitance related to MOSFET performance.

May 2017 (Regular)

1 Compare NMOS and CMOS technology in VLSI design 05
2 Compare full scaling model with constant voltage scaling 10
model.

Dec 2016 (KT Paper)

1 Define scaling. Explain various types of scaling in detail. 10

May 2016 (Regular)

1 Define scaling. Explain various types of scaling in detail. 10

Dec 2015 (KT Paper)

1 Define Scaling. Explain significance of scaling in VLSI 5
circuits

May 2015 (Regular)

1 Explain the effect on drain current due to channel length
modulation and velocity saturation. 05

Prepared by YP Sir (VESIT) Page 1

 2 Compare constant voltage and constant field scaling with 10
their merits and demerits.

Ch-2 MOSFET Inverters

Dec 2018 (KT Paper)
Q.N. Question Marks
1 Sketch and explain general shape of transfer characteristics 10
of NMOS inverter. Compare different types of inverter.
2 Write a short note on CMOS latch up and its prevention 05

May 2018 (Regular)

1 Explain CMOS inverter characteristic mentioning all regions 10
of operation. What is the effect of changing W/L ratio on it?
Explain with example
2 Derive equation of noise margin for CMOS inverter. 10

Dec 2017 (KT Paper)

1 Explain transfer characteristics of CMOS inverter showing 10
different regions. What is the effect of variation in W/L
ratio?
2 Write a short note on CMOS latch up 05

May 2017 (Regular)

1 Explain transfer characteristics of CMOS inverter showing 10
different regions. What is the effect of variation in W/L
ratio?
2 Consider CMOS inverter circuit with following parameters 10
Vdd=3V, VTo,n=0.6V, VTo,p=-0.7V,Kn=200µA/V2 ,
Kp=60µA/V2.Calculate Noise margins of the
circuit.Consider KR=2.5
3 Write a short note on CMOS latch up 05

Dec 2016 (KT Paper)

1 Explain CMOS inverter characteristic mentioning all regions 05
of operation.
2 Explain latch up in CMOS in detail. What are remedies to 10
avoid it.

Prepared by YP Sir (VESIT) Page 2

 3 Implement following function using CMOS. 05
F = A̅B + Ā̅C+ A B

May 2016 (Regular)

1 Explain latch up condition in CMOS in detail. What are 10
remedies to avoid latch up.
2 Consider a CMOS inverter circuits with following 10
parameters VDD=3.3v Ton=0.6v VTop=0.7v,u C=60u
A/v^2, (W/L) =8 ,uC=20uA/V^2, [W/L] =12. Calculate the
noise margin.

Dec 2015 (KT Paper)

1 Explain latch-up in CMOS inverter. 05
2 Explain operating regions of CMOS inverter with equations. 10

May 2015 (Regular)

1 Draw voltage transfer characteristic for CMOS inverter and 05
explain all regions.
2 For equal rise and tall delay five assume un =2up draw an 10
inverter equivalent circuit of 3 i/p NAND and 2 i/p XOR.
3 Consider a CMOS inverter with following parameters 10
Nmos V to, n=0.6V un Cox=60ua/v2 and (W/L)n=8
Pmos V to, p=0.7V un Cox=25ua/v2 and (W/L)p=12
Calculate the noise margin and switching threshold (VTH)
of the circuit, VDD=3V.
4 CMOS latch up and its prevention. 05

Ch-3 MOS Circuit Design Styles

Dec 2018 (KT Paper)
Q.N. Question Marks
1 Design 2:1 MUX using transmission gates and discuss 05
advantages of use of transmission gate logic
2 Implement Y=[(A.B)+(C.D)]’ using Dynamic logic 05
3 Implement D flip flop using static CMOS.What are other 10
design methods for it?
4 Write a short note on NORA,Zipper logic design 05

May 2018 (Regular)

Prepared by YP Sir (VESIT) Page 3
 1 Implement Y=[(A+B).(C+D)]’ using Pseudo NMOS logic 05
2 Implement 4:1 MUX using pass transistor logic. Explain 10
advantages of using pass transistor logic
3 Explain Pseudo NMOS logic & hence implement 2 i/p 10
NAND gate

Dec 2017 (KT Paper)

1 Implement Y=[(A+B).(C+D)]’ using Static CMOS logic 05
2 Implement 4:1 MUX using NMOS pass transistor logic 10
3 Draw D flip flop using CMOS and explain the working 10

May 2017 (Regular)

1 Implement Y=[A(B+C)]’ using Dynamic CMOS logic 05
2 Draw JK flip flop using CMOS and explain its working 10

Dec 2016 (KT Paper)

1 Draw and explain AND gate using pass transistor logic. 05
2 Draw D and JK latch using CMOS transmission gate and 10
explain the working.
3 Comparison of pseudo NMOS, Dynamic Static CMOS logic. 05

May 2016 (Regular)

1 Draw and explain AND gate using pass transistor logic. 05
2 Explain drawbacks of dynamic CMOS design. 05

Dec 2015 (KT Paper)

1 Draw CMOS implementation of D flip flop. 05
2 Implement Y=A+B.C using dynamic CMOS logic. 05
3 What are the drawbacks of dynamic CMOS logic? Show the 10
modification in dynamic CMOS logic to overcome its
drawbacks.

May 2015 (Regular)

1 Compare pass transistor logic, NMOS logic and CMOS 10
logic.
2 Implement using CMOS inverters. F=A.B+C 05
3 Implement 4:1 multiplexer using pass transistor logic. 10

Prepared by YP Sir (VESIT) Page 4

 Ch-4 Semiconductor Memories
Dec 2018 (KT Paper)
Q.N. Question Marks
1 Compare ROM and RAM 05
2 Explain read & write operation of 6T SRAM cell in detail 10
3 What are various decoders used in memory structures? 10
Explain any one in detail.

May 2018 (Regular)

1 Explain working of 1-T DRAM cell 05
2 Explain working of 6-T SRAM cell 10
3 Write a short note on NOR based ROM array 05

Dec 2017 (KT Paper)

1 Implement 4*4 NAND based ROM array 05
2 Draw 6T SRAM cell and explain its read and write operation 10
3 Write a short note on decoder in memory structure 05

May 2017 (Regular)

1 Explain working principle of Flash memory 05
2 Draw 1T DRAM cell and explain its read and write 10
operation
3 Write a short note on Sense amplifier 05

Dec 2016 (KT Paper)

1 What are various programming techniques used for 05
EEPROM.
2 Draw 6T SRAM cell and explain its read & write operation. 10
3 Decoder circuits for ROM array 05
4 Sense amplifier 05

May 2016 (Regular)

1 What are various programming techniques used for 05
EEPROM. Explain them in short.
2 Draw 6T SRAM cell and explain its read and write 10
operation.

Prepared by YP Sir (VESIT) Page 5

 3 Write a short note on Sense amplifier 05

Dec 2015 (KT Paper)

1 Draw 1T DRAM cell and Explain its read write and refresh 10
operation.
2 Explain programming techniques used in EEPROM. 10

May 2015 (Regular)

1 Give the read and write stability criteria for 6T RAM if the 05
pull up transistor and replaced by resistors.
2 Write a short note on Sense amplifier. 05

Ch-5 Data Path Design

Dec 2018 (KT Paper)
Q.N. Question Marks
1 Explain carry look ahead adder and its advantages 10

May 2018 (Regular)

1 What is fast adder? Explain any one scheme of fast adder 10
2 Write a short note on Barrel shifter 05

Dec 2017 (KT Paper)

1 Explain half adder circuit using static CMOS 05
2 Explain scheme of multiplication of 110*100 10
3 Draw CLA carry chain using static CMOS logic 10

May 2017 (Regular)

1 Compare Ripple carry adder with CLA 05
2 Explain scheme for multiplication of 101*010 10
3 Draw CLA carry chain using static CMOS logic 10
4 Write a short note on 4*4 barrel shifter 05

Dec 2016 (KT Paper)

1 Implement 4 x 4 barrel shifter. 05
2 Compare Ripple carry adder and carry look ahead adder. 10
Explain 4 bit CLA adder implementation
3 Write a short note on Array multiplier 05

Prepared by YP Sir (VESIT) Page 6

 May 2016 (Regular)
1 Draw and explain Manchester carry circuit. 05
2 Give and explain the drawback of ripple carry adder. 10
Explain 4 bit CLA adder with its carry equations, logical
network using dynamic CMOS logic.
3 Write a short note on Barrel shifter 05

Dec 2015 (KT Paper)

1 Draw CLA(Carry Look ahead Adder)carry chain using: 10
Static CMOS logic, Dynamic CMOS and Pseudo NMOS
logic.
2 Implement 4x4 barrel shifter using transmission gate. 10
Explain various operations using the same.
3 Write a short note on Array Multiplier 05

May 2015 (Regular)

1 Explain concept of carry look ahead adder with equation and 10
how does it achieve better speed compare to ripple carry
Adder.
2 Write a short on Array multiplier (4*4) 05

Ch-6 VLSI Clocking and System Design

Dec 2018 (KT Paper)
Q.N. Question Marks
1 Explain clock generation techniques 05
2 What is ESD protection? Explain with example 10
3 What are different clock distribution schemes? Explain 10
concept of Global & Local clock

May 2018 (Regular Paper)

1 What is low power design in VLSI circuits? 05
2 Explain clock generations and distribution networks used in 10
VLSI circuits
3 Explain various ESD protection schemes 05
4 Write a short note on interconnect scaling 05

Dec 2017 (KT Paper)

Prepared by YP Sir (VESIT) Page 7

 1 Explain importance of low power design 05
2 Explain various techniques of clock generations and 10
distribution
3 Write a short note on interconnect scaling 05

May 2017 (Regular Paper)

1 Explain importance of low power design 05
2 Explain various techniques of clock generations and 10
distribution
3 Write a short note on interconnect scaling 05

Dec 2016 (KT Paper)

1 Explain clock skew and describe techniques to minimize it. 10
2 What is ESD protection? Explain in detail. 10
3 Explain different clock generation schemes. Explain one 10
clock distribution scheme in detail.
4 Write a short note on Inter connect scaling 05

May 2016 (Regular)

1 Explain how ESD (electrostatic discharge) affect the 10
MOSFET. Give and explain input protection circuits.
2 Give and explain interconnect scaling with its width, length, 10
thickness and Capacitances.
3 Explain various technique of clock generation. Discuss ‘H’ 10
tree clock distribution.
4 Write a short note on Interconnect parameters 05

Dec 2015 (KT Paper)

1 Explain clock generation networks and distribution networks 10
use in VLSI circuits.
2 Give and Explain CMOS input and output protection 10
circuits.
3 Write a short note on Interconnect scaling. 05
4 Write a short note on Cross talk. 05

May 2015 (Regular)

Prepared by YP Sir (VESIT) Page 8

 1 Explain low power design considerations. 05
2 Write short note on clock generation, stabilization and 10
distribution.
3 Explain concept of charger sharing and charge leakage. 10
4 Write a short note on Resistance and capacitance estimation. 05

Weightage of Chapters

Chapter Dec- May- Dec- May- Dec- May- Dec - May-

No. 18 18 17 17 16 16 15 15
1 15 15 15 15 10 10 05 15
2 15 20 15 25 20 20 15 30
3 25 25 25 15 20 10 20 25
4 25 20 20 20 25 20 20 10
5 10 15 25 30 20 20 25 15
6 25 25 20 20 35 35 30 30

Prepared by YP Sir (VESIT) Page 9

 Avg. Marks

Ch-1
Ch-6 12
28 Ch-2 1

20
2
3
4

Ch-5 5

20 Ch-3 6

Ch-4 20
20

Prepared by YP Sir (VESIT) Page 10