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Volume 6, Issue 12, December (2016)

Design and Implementation of Domino Logic Circuit

in CMOS
Ankita Sharma
M. Tech (Student), Dept. of Electronics and Communication, SRIT, Jabalpur, India.

.Divyanshu Rao
Assistant Professor, Dept. of Electronics and Communication, SRIT, Jabalpur, India.

Ravi Mohan
Assistant Professor, Dept. of Electronics and Communication, SRIT, Jabalpur, India.

Abstract – Domino logic is a CMOS-based evolution of the design, where the extra design cost of higher performance logic
dynamic logic techniques. It allows a rail-to-rail logic swing. It was is often not justified by the relatively low volumes, and where
developed to speed up circuits. In integrated circuit design, ultimate performance is often not required. The simplicity of
dynamic logic (or sometimes clocked logic) is a design static CMOS generally leads to relatively low power
methodology in combinatorial logic circuits, particularly those
dissipation, especially for low fan-in gates
implemented in MOS technology. This work is oriented towards
implementing the domino logic circuits and static CMOS logic B. Domino Logic
circuits and comparing these technologies to show that the domino
logic technology is much better than static CMOS technology. The Domino logic is one of the most effective circuit configurations
proposed methodology is simple in designing; easy to understand for implementing high speed logic designs. Domino circuits
and it is very low power technology. In this work, we have offer the advantages of faster transitions and glitch-free
designed the various Domino logic gates such as AND, OR, NAND, operation. Domino logic is a CMOS-based evolution of
NOR and here we have analyzed the performance of these gates the dynamic logic techniques based on either PMOS or
in the terms of number of transistors, area, and Power. NMOS transistors. It runs 1.5-2 times faster than static CMOS
Index Terms – VLSI, Static CMOS, Dynamic CMOS, Domino logic because dynamic gates present much lower input
logic, MOSFET, Simulation. capacitance for the same output current and a lower switching
1. INTRODUCTION threshold. In Domino logic a single clock is used to precharge
and evaluate a cascaded set of dynamic logic blocks.
In integrated circuit design, dynamic logic is a design
methodology in combinatorial logic circuits, particularly those
implemented in MOS technology. Dynamic logic circuits are
usually faster than static counterparts, and require less surface
area, but are more difficult to design, and have higher power
dissipation. Domino logic circuit techniques are extensively
applied in high-performance microprocessors due to the
superior speed and area characteristics of dynamic CMOS
circuits as compared to static CMOS circuits. High-speed
operation of domino logic circuits is primarily due to the lower
noise margins of domino circuits as compared to static gates.
Domino logic offers speed and area advantages over
conventional static CMOS and is especially useful for
implementing complex logic gates with large fan-outs. Figure 1: A Domino Logic Circuit
A. Static CMOS 2. RELATED WORK
A static CMOS logic network is composed of static CMOS Dynamic logic requires two phases, the first phase is set up
gates which are a combination of two networks a pull-up phase or precharge phase, in this phase the output is
network, consisting of PMOS transistors, connected to power, unconditionally go to high (no matter the values of the inputs
and a pull-down network, consisting of NMOS transistors, A and B). The capacitor which represents the load capacitance
connected to ground. Static CMOS logic is common in ASIC

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Volume 6, Issue 12, December (2016)

of this gate becomes charged. During the evaluation phase, as dominos, once fallen, cannot stand up. The structure is hence
CLK is high. called Domino CMOS Logic.
4. RESULTS AND DISCUSSIONS
Here in the implementation of static CMOS, we designed the
basic gates such as INVERTER, AND, NAND, OR and NOR.
The implementation is done with the help of Berkeley Short
Channel Igfet Model (BSIM4) and transient. The design and
simulation of the gates are shown below.
1. INVERTER .

Figure 2: Example of static logic NAND gate

Domino logic is a CMOS based evaluation of the dynamic
logic techniques which are based on the either PMOS or
NMOS transistors. The dynamic gate outputs connect to one
inverter, in domino logic. In domino logic, cascade structure
consisting of several stages, the evaluation of each stage ripples
the next stage evaluation, similar to a domino falling one after
the other. Once fallen, the node states cannot return to “1” (until
the next CLK cycle), just as dominos, once fallen, cannot stand
up. The structure is hence called Domino CMOS logic.

Figure 4 : Simulation result for inverter

2.AND Gate

Figure 3: Example of Dynamic logic NAND gate

3. PROPOSED MODELLING
In Dynamic Logic, a problem arises when cascading one gate
to the next. The precharge "1" state of the first gate may cause
the second gate to discharge prematurely, before the first gate
has reached its correct state. This uses up the "precharge" of the
second gate, which cannot be restored until the next clock
cycle, so there is no recovery from this error. While this might
seem to defeat the point of dynamic logic, since the inverter has
a PFET (one of the main goals of Dynamic Logic is to avoid
PFETs where possible, due to speed), there are two reasons it
works well. First, there is no fan-out to multiple PFETs.In a
domino logic cascade structure consisting of several stages, the
evaluation of each stage ripples the next stage evaluation,
similar to a domino falling one after the other. Once fallen, the
node states cannot return to "1" (until the next clock cycle) just Figure 5 : simulation result for AND gate

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Volume 6, Issue 12, December (2016)

3.NAND Gate 5. NOR Gate

Figure 8: Simulation result for NOR gate

Figure 6 : Simulation result for NAND gate 5. CONCLUSION
4. OR Gate Simulation of gates was done on Microwind software and
DSCH. The simulation result shows that for an OR gate, the
delay has reduced from 15ps to 5 ps when implemented in
Domino logic. Thus Domino logic can be used in implementing
high speed logic designs. Domino circuits offer the advantages
of faster transitions and glitch-free operation. The detailed
simulation result is shown in the following table.
REFERENCES
[1] Neil H.E Weste, David Harris, Ayan Banerjee, “CMOS VLSI DESIGN”
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[2] www.cambridge.org “An Introduction to Domino Logic”
[3] Kaveh Shakeri and James D. Meindl, “Three Phase Domino Logic
Circuit”, In IEEE Journal of solid-state circuits.
[4] Vojin G. Oklobdzija and Robert K. Montoye, “Design-Performance
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[5] Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad, P.Rangappa , “Low
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[6] Jacobus A. Pretorius and Andre T. Salama, “Latched Domino CMOS
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[7] Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee,
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[8] Salendra.Govindarajulu, Dr.T.Jayachandra Prasad, C.Sreelakshmi,
Figure 7: Simulation result for OR gate Chandrakala, U.Thirumalesh, “Energy-Efficient, Noise-Tolerant CMOS
Domino VLSI Circuits in VDSM Technology”, (IJACSA) International

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Volume 6, Issue 12, December (2016)

Journal of Advanced Computer Science and Applications, Volume 2, No. [12] Th. Haniotakis, Y. Tsiatouhas and A. Arapoyanni, “Novel Domino Logic
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Sr.
No. Circuits Static CMOS Logic Domino Logic
Transistor Power Transistor Power
Count Delay Dissipation Count Delay Dissipation
1 Inverter 2 2ps 3.132uW 4 4p 2.501u
2 NAND 4 2ps 3.132uW 4 2ps 3.53u
3 AND 6 6ps 9.8uW 6 5ps 9.029u
4 OR 6 15ps 10.259uW 6 5ps 19.250u
5 NOR 4 7ps 3.924uW 4 2ps 7.391u

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