CMOS Differential Logic Family For Low Power Application

CHAPTER 1

INTRODUCTION
In this paper, a set of CMOS differential logic circuits are introduced for low power
applications. They perform a conditional operation for statistical power reduction in logic
operations. The measurement results indicate that the counter with the proposed logic
family achieves 50% power reduction compared with conventional logic family. Among
many components contributing to overall power consumption, the switching power
component, which is caused by charging and discharging internal capacitive nodes is a
dominant part. Since, the amount of switching power consumption linearly depends on the
operating clock frequency, minimising this type of power component will become a very
important issue in next generation SoCs.

1.1 LOGIC FAMILY

A logic family may refer to one of two related concepts. A logic family of monolithic
digital integrated circuit devices is a group of electronic logic gates constructed using one of
several different designs, usually with compatible logic levels and power supply
characteristics within a family. Many logic families were produced as individual components,
each containing one or a few related basic logical functions, which could be used as
"building-blocks" to create systems or as so-called "glue" to interconnect more complex
integrated circuits.

A "logic family" may also refer to a set of techniques used to implement logic
within large scale integrated circuits such as a central processor, memory, or other complex
function. Some such logic families, such as Complementary Pass-transistor Logic, use static
techniques to minimize power consumption. Other such logic families, such as domino logic,
use clocked dynamic techniques to minimize size, power consumption, and delay.

1.2 DIFFERENT LOGIC FAMILY

 Diode logic ( DL)

 Direct-coupled transistor logic (DCTL)
 Resistor–transistor logic (RTL)
 Resistor-capacitor transistor logic (RCTL)
 Diode–transistor logic (DTL)
 Emitter coupled logic (ECL) also known as Current-mode logic (CML)
o Positive emitter-coupled logic (PECL)
o Low-voltage positive emitter-coupled logic (LVPECL)
 Transistor–transistor logic (TTL) and variants
 P-type metal–oxide–semiconductor logic (PMOS)
 N-type metal–oxide–semiconductor logic (NMOS)
 Complementary metal–oxide–semiconductor logic (CMOS)
 Bipolar complementary metal–oxide–semiconductor logic (BiCMOS)
 Integrated injection logic (I2L)

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CHAPTER 2

CMOS

Complementary metal–oxide–semiconductor (CMOS) is a technology for making

integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static
RAM, and other digital logic circuits. CMOS technology is also used for a wide variety of
analog circuits such as image sensors, data converters, and highly integrated transceivers for
many types of communication.

Fig1: structure

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or

COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design
style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions.

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Two important characteristics of CMOS devices are

high noise immunity and low static power consumption. Significant power is only drawn
when the transistors the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices
without p-channel devices. CMOS also allows a high density of logic functions on a chip. It
was primarily this reason why CMOS won the race in the eighties and became the most used

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of certain

field-effect transistors, having a metal gate electrode placed on top of an oxide insulator,
which in turn is on top of a semiconductor material. Aluminium was once used but now the
material is poly silicon.

Besides these static CMOS logic circuits there are also dynamic CMOS logic circuits
that have some advantages in certain circumstances.

STATIC CMOS

The principle of static CMOS logic is shown in Fig: the output is connected to ground

through an n-block and to through a dual p-block. Without changes of the inputs this
gate consumes only the leakage currents of some transistors. When it is switching it draws an
additional current which is needed to charge and discharge the internal capacitances and the
load. Although the gate's logic function is ideally independent of the transistor channel
widths, they determine the dynamic behaviour essentially: wider transistors will switch a
capacitive load faster, but they will also cause a larger input capacitance of the gate. Unless
otherwise noted, minimum-width and, of course, minimum-channel-length transistors are

assumed. For given capacitances the transistors' on-state current will limit the switching
speed of the gate and, consequently, the maximum clock frequency of a synchronous circuit

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Static-CMOS NAND gate with three input

Two other important parameters determining the speed are the so-called fan-in which is the

number of inputs of a gate, and the fan-out which is the number of unity loads

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(i.e., inputs) connected to a gate's output. For a static-CMOS NAND gate as shown in Fig. 
Fin=3,means that three transistors are connected in series, which is roughly equivalent to one longer
transistor which can conduct on lon/Fin=Ion/3. The effect of Fout is an Fout-fold load capacitance.
This could lead to the assumption that the gate delay is is proportional to both Fin andFout.
However, the situation is more complex. Another fact to be considered is that a large fan-in will
degrade the normalized noise margins if the transistor sizes W are not adapted accordingly.

One way to improve speed is to make the output less sensitive to the capacitive load
by inserting a buffer as shown in Fig. Note that the input must be inverted and the logic
blocks must be replaced by their duals in order to perform the same logic function

F(x)=FT(x).

2.2DYNAMIC CMOS

As an example, consider first the static logic implementation of a NAND gate (here in
CMOS):

This circuit implements the logic function

If A and B are both high, the output will be pulled low, whereas if one of A and B are
low, the output will be pulled high. Most importantly, though, at all times, the output is
pulled either low or high.

The advantages of this type of logic are that the inputs are connected only to NMOS
transistors so that the input load capacitance is much smaller. Therefore, dynamic logic is
faster than static CMOS. Furthermore, for complex functions the transistor count is almost
halved. The big disadvantages of this type of logic is the need for repeated charging and

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discharging even when the inputs do not change their state. Therefore, dynamic logic
consumes more power than static CMOS despite the lower transistor count. These problems
can be alleviated to some extent by using a positive feedback with a narrow PMOS transistor
at the output buffer, which then works like a latch .The extra charge needed to change the
latch causes a usually small speed penalty.

Static versus dynamic logic

Perhaps the most well-known examples of the distinction between "static logic" and
"dynamic logic" is in memory -- static random access memory (SRAM) uses a form of static
logic, while dynamic random access memory (DRAM) uses a form of dynamic logic.

The largest difference between static and dynamic logic is that in dynamic logic, a clock
signal is used to evaluate combinational logic. However, to truly comprehend the importance
of this distinction, the reader will need some background on static logic.

In most types of logic design, termed static logic, there is at all times some mechanism to
drive the output either high or low. In many of the popular logic styles, such as TTL and
traditional CMOS, this principle can be rephrased as a statement that there is always a low-
impedance path between the output and either the supply voltage or the ground. As a
sidenote, there is of course an exception in this definition in the case of high impedance
outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be
used within a larger system where some mechanism will drive the output, and they do not
qualify as distinct from static logic.

In contrast, in dynamic logic, there is not always a mechanism driving the output high or low.
In the most common version of this concept, the output is driven high or low during distinct
parts of the clock cycle.

Dynamic logic requires a minimum clock rate fast enough that the output state of each
dynamic gate is used before it leaks out of the capacitance holding that state, during the part
of the clock cycle that the output is not being actively driven.

Static logic has no minimum clock rate -- the clock can be paused indefinitely. While it may
seem that doing nothing for long periods of time is not particularly useful, it leads to two
advantages:

 being able to pause a system at any time makes debugging and testing much easier, enabling
techniques such as single stepping.
 being able to run a system at extremely low clock rates allows low-power electronics to run
longer on a given battery.

Advantages

1. Dynamic logic is over twice as fast as normal logic.

2. It uses only fast N transistors, and is amenable to transistor sizing optimizations.

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3. Static logic is slower because it has twice the loading, higher thresholds, and actually
uses slow P transistors to compute things.

4.Dynamic logic may be harder to work with, but if you need the speed, there is no other
choice. Most electronics running at over 2 GHz these days uses dynamic logic, although
some manufacturers, such as Intel, have completely switched to static logic to save on power.

Dynamic logic too has techniques for reducing power consumption. A dynamic logic circuit
running at 1/2 voltage could consume 1/4 the power of normal. Also each rail can convey an
arbitrary number of bits, and there are no power-wasting glitches. Additionally, power-saving
clock gating and asynchronous techniques are much more natural in dynamic logic. In
practical use, however, dynamic logic still greatly increases the number of transistors that are
switching at any given time, which greatly increases power consumption over static CMOS.

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COMPLEMENTARY CMOS LOGIC

Complementary CMOS logic is composed of pull-up and pull-down networks. The pull
up and pull down networks are duals of each other. Each network is composed of NAND
(series connection) and/or NOR (parallel connection) functions. Pull up network is connected
to supply voltage, whereas pull down network is connected to the ground. Separate input is
given to pull up and pull down networks. The output is taken from the junction of pull up and
pulls down networks. The advantage of this circuit is that there is no static power dissipation.

EXAMPLE: NOR GATE

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Complementary CMOS logic can be implemented with the help of an example(NOR

gate).The Boolean function of the NOR gate is given by

Y =A+B

The pull down network performs the NOR operation which is given by

PDN=A+B

i.e. it act as a parallel NMOS

PUN performs the dual operation of PDN i.e., PUN performs the NAND operation.

PUN =PDN=A+B=A.B

i.e. it act as a series PMOS

CMOS AS AN INVERTER

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In CMOS circuits, p-type and n-type metal–oxide–semiconductor field-effect transistors

serve as pull-down and pull-up elements. Standard CMOS logic gates are constructed with a
network of PMOS transistors connecting the output to the positive supply and a network of
NMOS transistors connecting the output to the negative supply (or ground, typically); the two
networks are generally designed to be complementary, in the sense that the output will also
we pulled high or low, and not both at once. Thus CMOS can be thought as a system
combining NMOS and PMOS subcomponents. The composition of a PMOS transistor creates
low resistance when a low gate voltage is applied and high resistance when a high gate
voltage is applied, and the NMOS the other way around. This duality allows obtaining the
most elementary logic gate NOT by connecting the input to both a PMOS transistor and an
NMOS transistor.

OPERATION

If the voltage of input A is low, the NMOS transistor has high resistance so it stops voltage
from leaking into ground, while the PMOS transistor has low resistance so it allows the
voltage source to transfer voltage through the PMOS transistor to the output. The output
would therefore register a high voltage.

When the voltage of input A is high, the PMOS transistor would have high resistance so it
would block voltage source from the output, while the NMOS transistor would have low
resistance allowing the output to drain to ground. This would result in the output registering a
low voltage. In short, the outputs of the PMOS and NMOS transistors are complementary
such that when the input is low, the output would be high, and when the input is high, the
output would be low. Because of this, the CMOS circuits' output is by default the inversion of
the input.

In the transition region, where the input voltage is half the supply voltage, both the transistors
conduct; they operate in active mode and the whole circuit behaves as an inverting amplifier
with very high gain. The two transistors may be thought as two voltage-driven current
sources (current-stable resistors) that are connected in series and are driven by opposite-
varying complementary input voltages. They try to set the desired current magnitudes by
changing significantly their present resistances in opposite directions. As a result of this
interaction, the output voltage changes significantly; the gain is high and the transition zone
is narrow. From this viewpoint, each of the two transistors serves as an active load for the
other one.

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SYSTEM ON CHIP (SoC)

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System on chip (SoC OR SOC) refers to integrating all components of a computer or other
electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-
signal, and often radio-frequency functions – all on one chip. A typical application is in the
area of embedded systems.

Microcontrollers typically have under 100K of RAM (often just a few Kbytes) and often
really are single-chip-systems; whereas the term SoC is typically used with more powerful
processors, capable of running software such as Windows or Linux, which need external
memory chips (flash, RAM) to be useful, and which are used with various external
peripherals. In short, for larger systems System-on-a-chip is hyperbole, indicating technical
direction more than reality: increasing chip integration to reduce manufacturing costs and to
enable smaller systems.

A typical SoC consists of:

 One microcontroller, microprocessor or DSP core(s). Some SOCs – called multiprocessor

System-on-Chip (MPSoC) – include more than one processor core.
 Memory blocks including a selection of ROM, RAM, EEPROM and Flash.
 Timing sources including oscillators and phase-locked loops.
 Peripherals including counter-timers, real-time timers and power-on reset generators.
 External interfaces including industry standards such as USB, FireWire, Ethernet, USART, and
SPI.
 Analog interfaces including ADCs and DACs.
 Voltage regulators and power management circuits.

These blocks are connected by either a proprietary or industry-standard bus such as the
AMBA bus from ARM. DMA controllers route data directly between external interfaces
and memory, by-passing the processor core and thereby increasing the data throughput of
the SoC

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Microcontroller-based System-on-a-Chip

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TECHNIQUE 1: PSEUDO NMOS

It is employed to eliminate pull up network. Here clock input is given only to pull
down network. Pull down network can be implemented using any gate.

Pseudo NMOS logic uses fewer transistors as only the NMOS logic block is needed to
create the logic. For N inputs it requires N+1 FET’S. The basic topology of a pseudo NMOS
gate is shown in the figure.

The single PMOSFET is biased active since the grounded gate gives gate voltage is
equal to the supply voltage. It acts as a pull up device that tries to pull the output to the power
supply voltage. Logic is performed by the PDN network.

The pseudo-NMOS logic must be ratio sensitive so as to minimize the loss in power
dissipation. In other words, the PMOS must be ‘weak’ or small so as to have less capacitance
associated with the device. In this configuration, the charge will be pulled up much more
slowly by the PMOS than it can be discharged through the NMOS devices. In this way, a
pull-down path to ground through the NMOS logic block should easily pull down the output.
When no pull-down path to ground exists via the NMOS logic, the output is then pulled high
through the PMOS load. Although pseudo-NMOS logic can be utilized to reduce the number
of PMOS components in the system, not only does the static power dissipation serve as a
detriment, but the speed of the circuit is limited by the time necessary for the weak PMOS to
charge up the output node

BENEFITS

1. Substantial reduction in input capacitances-faster speed

ISSUES

1. Static power dissipation.

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2. Asymmetric propagation delays (falling edge faster).

TECHNIQUE 2: DCVSL

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DCVSL stands for differential cascade voltage switch logic. CVSL provides dual-rail
logic gates that have latching characteristics build into the circuit itself. The output results f
and f are held until the inputs induce a change. A DCVSL is shown ion the above figure.

The circuit consists of 2 PMOS transistors and 2 PDN networks. The 2 PMOSFETS are
connected to the supply voltage whereas the 2 PDN networks are grounded. The inputs given
to the 2 PDN networks are complements of each other. The logic tree is modeled as a pair of
complementary switches such that one is closed while the other is open as determined by the

BENEFITS

1. Faster speed

2. No static power dissipation

3. It provides much lower input capacitance for the same output current

4. It provides lower switching threshold

5. It also increases the performance when there are interdependencies among

the minterms of a logical expression

ISSUES

1. Slower than Pseudo NMOS requires more power than Complementary

CMOS

2. Data switching activity is low

3. It cannot be used with a global clock having voltage swing less than supply
voltage

APPLICATION

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1. Natural choice for the implementation of timing-critical logic functions in

SoCs

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TECHNIQUE 3: DYNAMIC LOGIC CIRCUIT

Dynamic logic gate uses clocking and charge storage properties of MOSFETs to implement
logic operations. The clock provides a synchronized data flow which makes the technique
useful in designing sequential networks. The characterizing feature of a dynamic logic gate is
that the result of calculation is valid only for a short period of time.

This circuit consists of two transistors, PMOS and NMOS.The PMOS transistor is
connected to the supply voltage, whereas NMOS transistor is connected to the ground. The
clock φ drives a complementary pair of transistors. The clocking signal φ defines two distinct
modes of operation during every cycle. When φ=0, the circuit is in precharge with PMOS
transistor on and NMOS transistor off. This establishes a conducting path between supply
voltage and the output. The PMOS transistor is called pre charge FET.

A clock transition to φ =1 drives the circuit into evaluation mode where PMOS is off and
NMOS is on. NMOS transistor is usually called the evaluate transistor.

BENEFITS

1. The elimination of the complimentary PMOS transistors significantly reduces the

surface area needed to implement the various logic functions not only because the
physical number of transistors is nearly cut in half, but because the physical size of the
PMOS transistors tend to be much larger than the size of an NMOS transistor.

2. The switching speeds are also increased using the dynamic logic configuration since the
speed bottleneck caused by the lengthier time the PMOS requires to pull-up the output
node is eliminated. Since this node is already precharged high through the PMOS during
the precharge phase, the output node needs only to be selectively discharged during the
evaluation phase. Discharging the output node through the NMOS devices is
significantly faster than the time needed to charge up the output node through the PMOS
device.

3. No static power dissipation

4. Less number of components

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ISSUES

1. The basic dynamic CMOS logic configuration causes the output node to be
disconnected from VDD during the evaluation phase, even if the output is also
disconnected from GND, the charge of the output node will begin to diminish due to
the non-ideal effects of the system.

2. Parasitic capacitances, for example, may leak the charge away from the output node
and eventually cause a logic error. Since there is, a finite time needed for the charge to
erroneously escape, the use of faster the clock speeds will eliminate this kind of error.
This implies that there is a minimum clock speed at which dynamic CMOS logic
structures may be operated.

3. It also eliminates the possibility to idle the basic dynamic CMOS logic circuit.

4. High design complexity.

5. Cascading requires care.

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PROBLEM ENCOUNTERED IN THE DESIGN OF DYNAMIC CMOS

Other characteristics of dynamic CMOS logic that must be taken into consideration when
designing dynamic logic are the problems that can occur when cascading the dynamic logic
blocks. Due to the finite pull down time of the NMOS logic block, during the very first
portion of the evaluation phase, the output will always register an output high state for at least
a brief moment in time before the output charge can be removed via the pull-down path to
GND. This is considered a ‘racing’ problem since the logic is evaluated correctly only when
the time to pull down the output node is faster than the time needed for the briefly high output
caused by the precharge phase to propagate as an erroneous logic signal to the next stage.
Since the output node of one dynamic CMOS logic block is connected to an input of the next
dynamic CMOS stage, an output high state however brief could complete a pull-down path to
GND in the following stage and erroneously cause a discharge in the output of this next
stage. Since the charge on the output node cannot be recovered until the next precharge
phase, the logic error would remain and propagate through the system. Dynamic CMOS logic
blocks should therefore not be directly cascaded. Note that care must also be taken to insure
that the input logic signals to the NMOS logic block are correct and stable for the complete
duration of the evaluation stage or a similar logic error could occur.

The errors occurring due to cascaded dynamic logic blocks can be overcome by adding an
inverter stage between the output of one stage and the input of another (see Fig. 9).

This inverter then would start out low at the very beginning of the evaluation phase.
The output low state of the inverter would cutoff the NMOS logic gates in the next
stage preventing any erroneous pull-down path. If a pull-down path is formed by the
NMOS logic block of the first stage, the output of the inverter buffer would
conditionally charge from low to high. Only if the inputs to the first stage NMOS logic

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block warrant a discharge of the output node would the output inverter make the low to
high transition. When the output of this inverter buffer goes high, the following stage
of NMOS logic would conditionally form a pull-down path to ground. In this way, the
addition of the inverter buffer eliminates any logic errors caused by the finite pull-
down time of the NMOS logic block. This kind of design is referred to as Domino
Logic since the pull-down of one stage can conditionally cause the pull-down of
succeeding stages and so on like falling dominoes. The number of Domino Logic
stages that may be cascaded is limited only by the sum of the total pull-down times in
all cascaded logic blocks which must be contained within the evaluation clock phase.
Drawbacks to this design are of course the addition of two additional components to
each dynamic block. Extra design consideration must also be observed when using
dynamic CMOS logic blocks in conjunction with static CMOS logic blocks. Since the
final output to the Domino logic blocks is the inverted form of the origonal output due
to the additional inverter buffer stage, only non-inverting logic may be used between
the output and input of dynamic logic. That is, since the inverter must make only one
conditional state change from logic low to high (not high to low) during the evaluation
phase only an even number of static logic blocks may be used in between dynamic
logic blocks.

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CHARACTERISTICS OF CMOS

1. Low power consumption – 10 nw per gate

2. Propagation delay – 25ns to 50 ns

3. Controlled rise time

4. Noise immunity

5. Temperature range - -55 to 1250c

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COMPARISON
CMOS TTL

1. Simple 1. Complex

2. Cheaper in fabrication 2. Costlier in fabrication

3. Small in size 3.Large in size

4. Consumes less power 4.More power

5. Fabrication is easy 5.Difficult

6. Less space on chip 6.More space

7. Low operating speed 7.High speed

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CONCLUSION

In this paper, a set of CMOS differential logic family is designed for low power applications.
It discusses about the three techniques namely, pseudo NMOS, DCVSL (differential cascade
voltage switch logic), dynamic logic circuits. Each of these techniques is having its own
advantages and disadvantages. The dynamic logic circuit is found to provide better low
power design. This type of logic is of great interest because it can provide striking
improvements in switching speed.

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REFERENCE
1. Introduction to VLSI Circuits and Systems by John P Uyemura.

2. VLSI circuits by Botkar

3. CMOS circuits layout and design by R.Jacob Baker, Harry w.Li, David.e.Bayce

4. IEEE journals

5. IEEE website

6. http://www. Google.com

7. http://www.wikipedia.com

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