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    Embedded Systems Engineering EE292C - Lecture 15

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    John Hallows
    This document provides an overview of Cadence Allegro Design Entry CIS for schematic capture as part of a lecture on embedded systems engineering. It discusses the Cadence toolchain available at Stanford, basic schematic symbols, schematic nomenclature, and keyboard shortcuts for Cadence Design Entry. The live demo section indicates that a screen-cast demo of schematic capture in Design Entry CIS will be shown.

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    Embedded Systems Engineering EE292C - Lecture 15

    Uploaded by

    John Hallows
    76 views6 pages
    This document provides an overview of Cadence Allegro Design Entry CIS for schematic capture as part of a lecture on embedded systems engineering. It discusses the Cadence toolchain available at Stanford, basic schematic symbols, schematic nomenclature, and keyboard shortcuts for Cadence Design Entry. The live demo section indicates that a screen-cast demo of schematic capture in Design Entry CIS will be shown.

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    Schematic Symbols Cadence Allegro Design Entry CIS Tutorial Max Klein

    Original Title

    Embedded Systems Engineering EE292C - Lecture 15

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    This document provides an overview of Cadence Allegro Design Entry CIS for schematic capture as part of a lecture on embedded systems engineering. It discusses the Cadence toolchain available at Stanford, basic schematic symbols, schematic nomenclature, and keyboard shortcuts for Cadence Design Entry. The live demo section indicates that a screen-cast demo of schematic capture in Design Entry CIS will be shown.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    76 views6 pages

    Embedded Systems Engineering EE292C - Lecture 15

    Uploaded by

    John Hallows
    This document provides an overview of Cadence Allegro Design Entry CIS for schematic capture as part of a lecture on embedded systems engineering. It discusses the Cadence toolchain available at Stanford, basic schematic symbols, schematic nomenclature, and keyboard shortcuts for Cadence Design Entry. The live demo section indicates that a screen-cast demo of schematic capture in Design Entry CIS will be shown.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    EE292C - Lecture 15

    Embedded Systems Engineering


    Schematic Symbols
    Cadence Allegro Design Entry CIS Tutorial
    May 22, 2007

    Max Klein
    STARLab - VLF Group
    Office: Packard 351, x33789
    Lab: Packard 075, x60333
    [email protected]

    EE292C - Klein 1
    Schematic and PCB Design

     Cadence tool chain


     300-600 seats at Stanford for each tool
     Allegro / SPB 15.7
     Industry Standard (Allegro or OrCAD)
     Design Entry CIS for Schematic Capture
     AKA PCB Design Studio / PCB Design Expert, Capture CIS, OrCAD
    Capture
     Layout Plus for PCB Layout
     No networked parts library for this class

     Be patient when starting program


     Licenses may take up to 15mins to check out
     Before license acquired, no window on screen
     Do NOT run multiple times! Look for capture.exe task first.
     License Info: http://www-vlsi.stanford.edu/cadtools/old_index.html
     Cadence: everything link for LM Status
     Cadtools mailing list for licensing issues

    EE292C - Klein 2
    Basic Schematic
    Symbols & Designators

    R1
    RESISTOR Y1 R2 POT VCC
    CRYSTAL

    J1
    C1 D1
    CAP NP LED U2 1
    1 2
    Vout 2 3
    + C2 Vin 3 4
    CAP POL GND 5
    AN77Lxx 6
    D2 7
    DIODE SW1 8
    9
    L1
    INDUCTOR
    SW PUSHBUTTON CON9

    EE292C - Klein 3
    Schematic Nomenclature

    Parts are actual components


    Nets connect parts at pins or nodes
    Net Aliases name the nets
     All nets with same alias are connected electrically!
    Busses are a collection of nets with a common base
    name
     Mem[0..15] is 16 nets in a bus
    Use Off-Page connectors with nets and busses going
    to other schematic pages
    Power (Vcc, etc) and GND Symbols
     Makes it clear which nets are for power
     Gives hints to PCB Layout program
    Use No-connects to indicate pins with no connection
     Helps when checking schematic for unconnected pins

    EE292C - Klein 4
    Cadence Design Entry / Capture
    Keyboard Shortcuts

    p: add part x: place no-connect


    w: create wire/net r: rotate part
    b: create bus i: zoom in
    e: create bus entry o: zoom out
    n: create net/bus alias c: center on mouse
    f: create power / VCC F5: redraw screen
    g: create ground / GND

    EE292C - Klein 5
    Live / Screen-Cast Demo:

    Schematic Capture with


    Design Entry CIS

    EE292C - Klein 6

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